stratixII.c 4.8 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190
  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * (C) Copyright 2007
  4. * Eran Liberty, Extricom , eran.liberty@gmail.com
  5. */
  6. #include <common.h> /* core U-Boot definitions */
  7. #include <altera.h>
  8. #include <linux/delay.h>
  9. int StratixII_ps_fpp_load (Altera_desc * desc, void *buf, size_t bsize,
  10. int isSerial, int isSecure);
  11. int StratixII_ps_fpp_dump (Altera_desc * desc, void *buf, size_t bsize);
  12. /****************************************************************/
  13. /* Stratix II Generic Implementation */
  14. int StratixII_load (Altera_desc * desc, void *buf, size_t bsize)
  15. {
  16. int ret_val = FPGA_FAIL;
  17. switch (desc->iface) {
  18. case passive_serial:
  19. ret_val = StratixII_ps_fpp_load (desc, buf, bsize, 1, 0);
  20. break;
  21. case fast_passive_parallel:
  22. ret_val = StratixII_ps_fpp_load (desc, buf, bsize, 0, 0);
  23. break;
  24. case fast_passive_parallel_security:
  25. ret_val = StratixII_ps_fpp_load (desc, buf, bsize, 0, 1);
  26. break;
  27. /* Add new interface types here */
  28. default:
  29. printf ("%s: Unsupported interface type, %d\n", __FUNCTION__,
  30. desc->iface);
  31. }
  32. return ret_val;
  33. }
  34. int StratixII_dump (Altera_desc * desc, void *buf, size_t bsize)
  35. {
  36. int ret_val = FPGA_FAIL;
  37. switch (desc->iface) {
  38. case passive_serial:
  39. case fast_passive_parallel:
  40. case fast_passive_parallel_security:
  41. ret_val = StratixII_ps_fpp_dump (desc, buf, bsize);
  42. break;
  43. /* Add new interface types here */
  44. default:
  45. printf ("%s: Unsupported interface type, %d\n", __FUNCTION__,
  46. desc->iface);
  47. }
  48. return ret_val;
  49. }
  50. int StratixII_info (Altera_desc * desc)
  51. {
  52. return FPGA_SUCCESS;
  53. }
  54. int StratixII_ps_fpp_dump (Altera_desc * desc, void *buf, size_t bsize)
  55. {
  56. printf ("Stratix II Fast Passive Parallel dump is not implemented\n");
  57. return FPGA_FAIL;
  58. }
  59. int StratixII_ps_fpp_load (Altera_desc * desc, void *buf, size_t bsize,
  60. int isSerial, int isSecure)
  61. {
  62. altera_board_specific_func *fns;
  63. int cookie;
  64. int ret_val = FPGA_FAIL;
  65. int bytecount;
  66. char *buff = buf;
  67. int i;
  68. if (!desc) {
  69. printf ("%s(%d) Altera_desc missing\n", __FUNCTION__, __LINE__);
  70. return FPGA_FAIL;
  71. }
  72. if (!buff) {
  73. printf ("%s(%d) buffer is missing\n", __FUNCTION__, __LINE__);
  74. return FPGA_FAIL;
  75. }
  76. if (!bsize) {
  77. printf ("%s(%d) size is zero\n", __FUNCTION__, __LINE__);
  78. return FPGA_FAIL;
  79. }
  80. if (!desc->iface_fns) {
  81. printf
  82. ("%s(%d) Altera_desc function interface table is missing\n",
  83. __FUNCTION__, __LINE__);
  84. return FPGA_FAIL;
  85. }
  86. fns = (altera_board_specific_func *) (desc->iface_fns);
  87. cookie = desc->cookie;
  88. if (!
  89. (fns->config && fns->status && fns->done && fns->data
  90. && fns->abort)) {
  91. printf
  92. ("%s(%d) Missing some function in the function interface table\n",
  93. __FUNCTION__, __LINE__);
  94. return FPGA_FAIL;
  95. }
  96. /* 1. give board specific a chance to do anything before we start */
  97. if (fns->pre) {
  98. if ((ret_val = fns->pre (cookie)) < 0) {
  99. return ret_val;
  100. }
  101. }
  102. /* from this point on we must fail gracfully by calling lower layer abort */
  103. /* 2. Strat burn cycle by deasserting config for t_CFG and waiting t_CF2CK after reaserted */
  104. fns->config (0, 1, cookie);
  105. udelay(5); /* nCONFIG low pulse width 2usec */
  106. fns->config (1, 1, cookie);
  107. udelay(100); /* nCONFIG high to first rising edge on DCLK */
  108. /* 3. Start the Data cycle with clk deasserted */
  109. bytecount = 0;
  110. fns->clk (0, 1, cookie);
  111. printf ("loading to fpga ");
  112. while (bytecount < bsize) {
  113. /* 3.1 check stratix has not signaled us an error */
  114. if (fns->status (cookie) != 1) {
  115. printf
  116. ("\n%s(%d) Stratix failed (byte transferred till failure 0x%x)\n",
  117. __FUNCTION__, __LINE__, bytecount);
  118. fns->abort (cookie);
  119. return FPGA_FAIL;
  120. }
  121. if (isSerial) {
  122. int i;
  123. uint8_t data = buff[bytecount++];
  124. for (i = 0; i < 8; i++) {
  125. /* 3.2(ps) put data on the bus */
  126. fns->data ((data >> i) & 1, 1, cookie);
  127. /* 3.3(ps) clock once */
  128. fns->clk (1, 1, cookie);
  129. fns->clk (0, 1, cookie);
  130. }
  131. } else {
  132. /* 3.2(fpp) put data on the bus */
  133. fns->data (buff[bytecount++], 1, cookie);
  134. /* 3.3(fpp) clock once */
  135. fns->clk (1, 1, cookie);
  136. fns->clk (0, 1, cookie);
  137. /* 3.4(fpp) for secure cycle push 3 more clocks */
  138. for (i = 0; isSecure && i < 3; i++) {
  139. fns->clk (1, 1, cookie);
  140. fns->clk (0, 1, cookie);
  141. }
  142. }
  143. /* 3.5 while clk is deasserted it is safe to print some progress indication */
  144. if ((bytecount % (bsize / 100)) == 0) {
  145. printf ("\b\b\b%02d\%", bytecount * 100 / bsize);
  146. }
  147. }
  148. /* 4. Set one last clock and check conf done signal */
  149. fns->clk (1, 1, cookie);
  150. udelay(100);
  151. if (!fns->done (cookie)) {
  152. printf (" error!.\n");
  153. fns->abort (cookie);
  154. return FPGA_FAIL;
  155. } else {
  156. printf ("\b\b\b done.\n");
  157. }
  158. /* 5. call lower layer post configuration */
  159. if (fns->post) {
  160. if ((ret_val = fns->post (cookie)) < 0) {
  161. fns->abort (cookie);
  162. return ret_val;
  163. }
  164. }
  165. return FPGA_SUCCESS;
  166. }