spartan3.c 13 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * (C) Copyright 2002
  4. * Rich Ireland, Enterasys Networks, rireland@enterasys.com.
  5. */
  6. /*
  7. * Configuration support for Xilinx Spartan3 devices. Based
  8. * on spartan2.c (Rich Ireland, rireland@enterasys.com).
  9. */
  10. #include <common.h> /* core U-Boot definitions */
  11. #include <spartan3.h> /* Spartan-II device family */
  12. /* Define FPGA_DEBUG to get debug printf's */
  13. #ifdef FPGA_DEBUG
  14. #define PRINTF(fmt,args...) printf (fmt ,##args)
  15. #else
  16. #define PRINTF(fmt,args...)
  17. #endif
  18. #undef CONFIG_SYS_FPGA_CHECK_BUSY
  19. /* Note: The assumption is that we cannot possibly run fast enough to
  20. * overrun the device (the Slave Parallel mode can free run at 50MHz).
  21. * If there is a need to operate slower, define CONFIG_FPGA_DELAY in
  22. * the board config file to slow things down.
  23. */
  24. #ifndef CONFIG_FPGA_DELAY
  25. #define CONFIG_FPGA_DELAY()
  26. #endif
  27. #ifndef CONFIG_SYS_FPGA_WAIT
  28. #define CONFIG_SYS_FPGA_WAIT CONFIG_SYS_HZ/100 /* 10 ms */
  29. #endif
  30. static int spartan3_sp_load(xilinx_desc *desc, const void *buf, size_t bsize);
  31. static int spartan3_sp_dump(xilinx_desc *desc, const void *buf, size_t bsize);
  32. /* static int spartan3_sp_info(xilinx_desc *desc ); */
  33. static int spartan3_ss_load(xilinx_desc *desc, const void *buf, size_t bsize);
  34. static int spartan3_ss_dump(xilinx_desc *desc, const void *buf, size_t bsize);
  35. /* static int spartan3_ss_info(xilinx_desc *desc); */
  36. /* ------------------------------------------------------------------------- */
  37. /* Spartan-II Generic Implementation */
  38. static int spartan3_load(xilinx_desc *desc, const void *buf, size_t bsize,
  39. bitstream_type bstype)
  40. {
  41. int ret_val = FPGA_FAIL;
  42. switch (desc->iface) {
  43. case slave_serial:
  44. PRINTF ("%s: Launching Slave Serial Load\n", __FUNCTION__);
  45. ret_val = spartan3_ss_load(desc, buf, bsize);
  46. break;
  47. case slave_parallel:
  48. PRINTF ("%s: Launching Slave Parallel Load\n", __FUNCTION__);
  49. ret_val = spartan3_sp_load(desc, buf, bsize);
  50. break;
  51. default:
  52. printf ("%s: Unsupported interface type, %d\n",
  53. __FUNCTION__, desc->iface);
  54. }
  55. return ret_val;
  56. }
  57. static int spartan3_dump(xilinx_desc *desc, const void *buf, size_t bsize)
  58. {
  59. int ret_val = FPGA_FAIL;
  60. switch (desc->iface) {
  61. case slave_serial:
  62. PRINTF ("%s: Launching Slave Serial Dump\n", __FUNCTION__);
  63. ret_val = spartan3_ss_dump(desc, buf, bsize);
  64. break;
  65. case slave_parallel:
  66. PRINTF ("%s: Launching Slave Parallel Dump\n", __FUNCTION__);
  67. ret_val = spartan3_sp_dump(desc, buf, bsize);
  68. break;
  69. default:
  70. printf ("%s: Unsupported interface type, %d\n",
  71. __FUNCTION__, desc->iface);
  72. }
  73. return ret_val;
  74. }
  75. static int spartan3_info(xilinx_desc *desc)
  76. {
  77. return FPGA_SUCCESS;
  78. }
  79. /* ------------------------------------------------------------------------- */
  80. /* Spartan-II Slave Parallel Generic Implementation */
  81. static int spartan3_sp_load(xilinx_desc *desc, const void *buf, size_t bsize)
  82. {
  83. int ret_val = FPGA_FAIL; /* assume the worst */
  84. xilinx_spartan3_slave_parallel_fns *fn = desc->iface_fns;
  85. PRINTF ("%s: start with interface functions @ 0x%p\n",
  86. __FUNCTION__, fn);
  87. if (fn) {
  88. size_t bytecount = 0;
  89. unsigned char *data = (unsigned char *) buf;
  90. int cookie = desc->cookie; /* make a local copy */
  91. unsigned long ts; /* timestamp */
  92. PRINTF ("%s: Function Table:\n"
  93. "ptr:\t0x%p\n"
  94. "struct: 0x%p\n"
  95. "pre: 0x%p\n"
  96. "pgm:\t0x%p\n"
  97. "init:\t0x%p\n"
  98. "err:\t0x%p\n"
  99. "clk:\t0x%p\n"
  100. "cs:\t0x%p\n"
  101. "wr:\t0x%p\n"
  102. "read data:\t0x%p\n"
  103. "write data:\t0x%p\n"
  104. "busy:\t0x%p\n"
  105. "abort:\t0x%p\n",
  106. "post:\t0x%p\n\n",
  107. __FUNCTION__, &fn, fn, fn->pre, fn->pgm, fn->init, fn->err,
  108. fn->clk, fn->cs, fn->wr, fn->rdata, fn->wdata, fn->busy,
  109. fn->abort, fn->post);
  110. /*
  111. * This code is designed to emulate the "Express Style"
  112. * Continuous Data Loading in Slave Parallel Mode for
  113. * the Spartan-II Family.
  114. */
  115. #ifdef CONFIG_SYS_FPGA_PROG_FEEDBACK
  116. printf ("Loading FPGA Device %d...\n", cookie);
  117. #endif
  118. /*
  119. * Run the pre configuration function if there is one.
  120. */
  121. if (*fn->pre) {
  122. (*fn->pre) (cookie);
  123. }
  124. /* Establish the initial state */
  125. (*fn->pgm) (true, true, cookie); /* Assert the program, commit */
  126. /* Get ready for the burn */
  127. CONFIG_FPGA_DELAY ();
  128. (*fn->pgm) (false, true, cookie); /* Deassert the program, commit */
  129. ts = get_timer (0); /* get current time */
  130. /* Now wait for INIT and BUSY to go high */
  131. do {
  132. CONFIG_FPGA_DELAY ();
  133. if (get_timer (ts) > CONFIG_SYS_FPGA_WAIT) { /* check the time */
  134. puts ("** Timeout waiting for INIT to clear.\n");
  135. (*fn->abort) (cookie); /* abort the burn */
  136. return FPGA_FAIL;
  137. }
  138. } while ((*fn->init) (cookie) && (*fn->busy) (cookie));
  139. (*fn->wr) (true, true, cookie); /* Assert write, commit */
  140. (*fn->cs) (true, true, cookie); /* Assert chip select, commit */
  141. (*fn->clk) (true, true, cookie); /* Assert the clock pin */
  142. /* Load the data */
  143. while (bytecount < bsize) {
  144. /* XXX - do we check for an Ctrl-C press in here ??? */
  145. /* XXX - Check the error bit? */
  146. (*fn->wdata) (data[bytecount++], true, cookie); /* write the data */
  147. CONFIG_FPGA_DELAY ();
  148. (*fn->clk) (false, true, cookie); /* Deassert the clock pin */
  149. CONFIG_FPGA_DELAY ();
  150. (*fn->clk) (true, true, cookie); /* Assert the clock pin */
  151. #ifdef CONFIG_SYS_FPGA_CHECK_BUSY
  152. ts = get_timer (0); /* get current time */
  153. while ((*fn->busy) (cookie)) {
  154. /* XXX - we should have a check in here somewhere to
  155. * make sure we aren't busy forever... */
  156. CONFIG_FPGA_DELAY ();
  157. (*fn->clk) (false, true, cookie); /* Deassert the clock pin */
  158. CONFIG_FPGA_DELAY ();
  159. (*fn->clk) (true, true, cookie); /* Assert the clock pin */
  160. if (get_timer (ts) > CONFIG_SYS_FPGA_WAIT) { /* check the time */
  161. puts ("** Timeout waiting for BUSY to clear.\n");
  162. (*fn->abort) (cookie); /* abort the burn */
  163. return FPGA_FAIL;
  164. }
  165. }
  166. #endif
  167. #ifdef CONFIG_SYS_FPGA_PROG_FEEDBACK
  168. if (bytecount % (bsize / 40) == 0)
  169. putc ('.'); /* let them know we are alive */
  170. #endif
  171. }
  172. CONFIG_FPGA_DELAY ();
  173. (*fn->cs) (false, true, cookie); /* Deassert the chip select */
  174. (*fn->wr) (false, true, cookie); /* Deassert the write pin */
  175. #ifdef CONFIG_SYS_FPGA_PROG_FEEDBACK
  176. putc ('\n'); /* terminate the dotted line */
  177. #endif
  178. /* now check for done signal */
  179. ts = get_timer (0); /* get current time */
  180. ret_val = FPGA_SUCCESS;
  181. while ((*fn->done) (cookie) == FPGA_FAIL) {
  182. /* XXX - we should have a check in here somewhere to
  183. * make sure we aren't busy forever... */
  184. CONFIG_FPGA_DELAY ();
  185. (*fn->clk) (false, true, cookie); /* Deassert the clock pin */
  186. CONFIG_FPGA_DELAY ();
  187. (*fn->clk) (true, true, cookie); /* Assert the clock pin */
  188. if (get_timer (ts) > CONFIG_SYS_FPGA_WAIT) { /* check the time */
  189. puts ("** Timeout waiting for DONE to clear.\n");
  190. (*fn->abort) (cookie); /* abort the burn */
  191. ret_val = FPGA_FAIL;
  192. break;
  193. }
  194. }
  195. /*
  196. * Run the post configuration function if there is one.
  197. */
  198. if (*fn->post)
  199. (*fn->post) (cookie);
  200. #ifdef CONFIG_SYS_FPGA_PROG_FEEDBACK
  201. if (ret_val == FPGA_SUCCESS)
  202. puts ("Done.\n");
  203. else
  204. puts ("Fail.\n");
  205. #endif
  206. } else {
  207. printf ("%s: NULL Interface function table!\n", __FUNCTION__);
  208. }
  209. return ret_val;
  210. }
  211. static int spartan3_sp_dump(xilinx_desc *desc, const void *buf, size_t bsize)
  212. {
  213. int ret_val = FPGA_FAIL; /* assume the worst */
  214. xilinx_spartan3_slave_parallel_fns *fn = desc->iface_fns;
  215. if (fn) {
  216. unsigned char *data = (unsigned char *) buf;
  217. size_t bytecount = 0;
  218. int cookie = desc->cookie; /* make a local copy */
  219. printf ("Starting Dump of FPGA Device %d...\n", cookie);
  220. (*fn->cs) (true, true, cookie); /* Assert chip select, commit */
  221. (*fn->clk) (true, true, cookie); /* Assert the clock pin */
  222. /* dump the data */
  223. while (bytecount < bsize) {
  224. /* XXX - do we check for an Ctrl-C press in here ??? */
  225. (*fn->clk) (false, true, cookie); /* Deassert the clock pin */
  226. (*fn->clk) (true, true, cookie); /* Assert the clock pin */
  227. (*fn->rdata) (&(data[bytecount++]), cookie); /* read the data */
  228. #ifdef CONFIG_SYS_FPGA_PROG_FEEDBACK
  229. if (bytecount % (bsize / 40) == 0)
  230. putc ('.'); /* let them know we are alive */
  231. #endif
  232. }
  233. (*fn->cs) (false, false, cookie); /* Deassert the chip select */
  234. (*fn->clk) (false, true, cookie); /* Deassert the clock pin */
  235. (*fn->clk) (true, true, cookie); /* Assert the clock pin */
  236. #ifdef CONFIG_SYS_FPGA_PROG_FEEDBACK
  237. putc ('\n'); /* terminate the dotted line */
  238. #endif
  239. puts ("Done.\n");
  240. /* XXX - checksum the data? */
  241. } else {
  242. printf ("%s: NULL Interface function table!\n", __FUNCTION__);
  243. }
  244. return ret_val;
  245. }
  246. /* ------------------------------------------------------------------------- */
  247. static int spartan3_ss_load(xilinx_desc *desc, const void *buf, size_t bsize)
  248. {
  249. int ret_val = FPGA_FAIL; /* assume the worst */
  250. xilinx_spartan3_slave_serial_fns *fn = desc->iface_fns;
  251. int i;
  252. unsigned char val;
  253. PRINTF ("%s: start with interface functions @ 0x%p\n",
  254. __FUNCTION__, fn);
  255. if (fn) {
  256. size_t bytecount = 0;
  257. unsigned char *data = (unsigned char *) buf;
  258. int cookie = desc->cookie; /* make a local copy */
  259. unsigned long ts; /* timestamp */
  260. PRINTF ("%s: Function Table:\n"
  261. "ptr:\t0x%p\n"
  262. "struct: 0x%p\n"
  263. "pgm:\t0x%p\n"
  264. "init:\t0x%p\n"
  265. "clk:\t0x%p\n"
  266. "wr:\t0x%p\n"
  267. "done:\t0x%p\n\n",
  268. __FUNCTION__, &fn, fn, fn->pgm, fn->init,
  269. fn->clk, fn->wr, fn->done);
  270. #ifdef CONFIG_SYS_FPGA_PROG_FEEDBACK
  271. printf ("Loading FPGA Device %d...\n", cookie);
  272. #endif
  273. /*
  274. * Run the pre configuration function if there is one.
  275. */
  276. if (*fn->pre) {
  277. (*fn->pre) (cookie);
  278. }
  279. /* Establish the initial state */
  280. (*fn->pgm) (true, true, cookie); /* Assert the program, commit */
  281. /* Wait for INIT state (init low) */
  282. ts = get_timer (0); /* get current time */
  283. do {
  284. CONFIG_FPGA_DELAY ();
  285. if (get_timer (ts) > CONFIG_SYS_FPGA_WAIT) { /* check the time */
  286. puts ("** Timeout waiting for INIT to start.\n");
  287. if (*fn->abort)
  288. (*fn->abort) (cookie);
  289. return FPGA_FAIL;
  290. }
  291. } while (!(*fn->init) (cookie));
  292. /* Get ready for the burn */
  293. CONFIG_FPGA_DELAY ();
  294. (*fn->pgm) (false, true, cookie); /* Deassert the program, commit */
  295. ts = get_timer (0); /* get current time */
  296. /* Now wait for INIT to go high */
  297. do {
  298. CONFIG_FPGA_DELAY ();
  299. if (get_timer (ts) > CONFIG_SYS_FPGA_WAIT) { /* check the time */
  300. puts ("** Timeout waiting for INIT to clear.\n");
  301. if (*fn->abort)
  302. (*fn->abort) (cookie);
  303. return FPGA_FAIL;
  304. }
  305. } while ((*fn->init) (cookie));
  306. /* Load the data */
  307. if(*fn->bwr)
  308. (*fn->bwr) (data, bsize, true, cookie);
  309. else {
  310. while (bytecount < bsize) {
  311. /* Xilinx detects an error if INIT goes low (active)
  312. while DONE is low (inactive) */
  313. if ((*fn->done) (cookie) == 0 && (*fn->init) (cookie)) {
  314. puts ("** CRC error during FPGA load.\n");
  315. if (*fn->abort)
  316. (*fn->abort) (cookie);
  317. return (FPGA_FAIL);
  318. }
  319. val = data [bytecount ++];
  320. i = 8;
  321. do {
  322. /* Deassert the clock */
  323. (*fn->clk) (false, true, cookie);
  324. CONFIG_FPGA_DELAY ();
  325. /* Write data */
  326. (*fn->wr) ((val & 0x80), true, cookie);
  327. CONFIG_FPGA_DELAY ();
  328. /* Assert the clock */
  329. (*fn->clk) (true, true, cookie);
  330. CONFIG_FPGA_DELAY ();
  331. val <<= 1;
  332. i --;
  333. } while (i > 0);
  334. #ifdef CONFIG_SYS_FPGA_PROG_FEEDBACK
  335. if (bytecount % (bsize / 40) == 0)
  336. putc ('.'); /* let them know we are alive */
  337. #endif
  338. }
  339. }
  340. CONFIG_FPGA_DELAY ();
  341. #ifdef CONFIG_SYS_FPGA_PROG_FEEDBACK
  342. putc ('\n'); /* terminate the dotted line */
  343. #endif
  344. /* now check for done signal */
  345. ts = get_timer (0); /* get current time */
  346. ret_val = FPGA_SUCCESS;
  347. (*fn->wr) (true, true, cookie);
  348. while (! (*fn->done) (cookie)) {
  349. /* XXX - we should have a check in here somewhere to
  350. * make sure we aren't busy forever... */
  351. CONFIG_FPGA_DELAY ();
  352. (*fn->clk) (false, true, cookie); /* Deassert the clock pin */
  353. CONFIG_FPGA_DELAY ();
  354. (*fn->clk) (true, true, cookie); /* Assert the clock pin */
  355. putc ('*');
  356. if (get_timer (ts) > CONFIG_SYS_FPGA_WAIT) { /* check the time */
  357. puts ("** Timeout waiting for DONE to clear.\n");
  358. ret_val = FPGA_FAIL;
  359. break;
  360. }
  361. }
  362. putc ('\n'); /* terminate the dotted line */
  363. /*
  364. * Run the post configuration function if there is one.
  365. */
  366. if (*fn->post)
  367. (*fn->post) (cookie);
  368. #ifdef CONFIG_SYS_FPGA_PROG_FEEDBACK
  369. if (ret_val == FPGA_SUCCESS)
  370. puts ("Done.\n");
  371. else
  372. puts ("Fail.\n");
  373. #endif
  374. } else {
  375. printf ("%s: NULL Interface function table!\n", __FUNCTION__);
  376. }
  377. return ret_val;
  378. }
  379. static int spartan3_ss_dump(xilinx_desc *desc, const void *buf, size_t bsize)
  380. {
  381. /* Readback is only available through the Slave Parallel and */
  382. /* boundary-scan interfaces. */
  383. printf ("%s: Slave Serial Dumping is unavailable\n",
  384. __FUNCTION__);
  385. return FPGA_FAIL;
  386. }
  387. struct xilinx_fpga_op spartan3_op = {
  388. .load = spartan3_load,
  389. .dump = spartan3_dump,
  390. .info = spartan3_info,
  391. };