socfpga_arria10.c 24 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * Copyright (C) 2017-2019 Intel Corporation <www.intel.com>
  4. */
  5. #include <image.h>
  6. #include <log.h>
  7. #include <asm/io.h>
  8. #include <asm/arch/fpga_manager.h>
  9. #include <asm/arch/reset_manager.h>
  10. #include <asm/arch/system_manager.h>
  11. #include <asm/arch/sdram.h>
  12. #include <asm/arch/misc.h>
  13. #include <altera.h>
  14. #include <asm/arch/pinmux.h>
  15. #include <common.h>
  16. #include <dm.h>
  17. #include <dm/ofnode.h>
  18. #include <errno.h>
  19. #include <fs_loader.h>
  20. #include <wait_bit.h>
  21. #include <watchdog.h>
  22. #include <linux/bitops.h>
  23. #include <linux/delay.h>
  24. #define CFGWDTH_32 1
  25. #define MIN_BITSTREAM_SIZECHECK 230
  26. #define ENCRYPTION_OFFSET 69
  27. #define COMPRESSION_OFFSET 229
  28. #define FPGA_TIMEOUT_MSEC 1000 /* timeout in ms */
  29. #define FPGA_TIMEOUT_CNT 0x1000000
  30. #define DEFAULT_DDR_LOAD_ADDRESS 0x400
  31. DECLARE_GLOBAL_DATA_PTR;
  32. static const struct socfpga_fpga_manager *fpga_manager_base =
  33. (void *)SOCFPGA_FPGAMGRREGS_ADDRESS;
  34. static void fpgamgr_set_cd_ratio(unsigned long ratio);
  35. static uint32_t fpgamgr_get_msel(void)
  36. {
  37. u32 reg;
  38. reg = readl(&fpga_manager_base->imgcfg_stat);
  39. reg = (reg & ALT_FPGAMGR_IMGCFG_STAT_F2S_MSEL_SET_MSD) >>
  40. ALT_FPGAMGR_IMGCFG_STAT_F2S_MSEL0_LSB;
  41. return reg;
  42. }
  43. static void fpgamgr_set_cfgwdth(int width)
  44. {
  45. if (width)
  46. setbits_le32(&fpga_manager_base->imgcfg_ctrl_02,
  47. ALT_FPGAMGR_IMGCFG_CTL_02_CFGWIDTH_SET_MSK);
  48. else
  49. clrbits_le32(&fpga_manager_base->imgcfg_ctrl_02,
  50. ALT_FPGAMGR_IMGCFG_CTL_02_CFGWIDTH_SET_MSK);
  51. }
  52. int is_fpgamgr_user_mode(void)
  53. {
  54. return (readl(&fpga_manager_base->imgcfg_stat) &
  55. ALT_FPGAMGR_IMGCFG_STAT_F2S_USERMODE_SET_MSK) != 0;
  56. }
  57. static int wait_for_user_mode(void)
  58. {
  59. return wait_for_bit_le32(&fpga_manager_base->imgcfg_stat,
  60. ALT_FPGAMGR_IMGCFG_STAT_F2S_USERMODE_SET_MSK,
  61. 1, FPGA_TIMEOUT_MSEC, false);
  62. }
  63. int is_fpgamgr_early_user_mode(void)
  64. {
  65. return (readl(&fpga_manager_base->imgcfg_stat) &
  66. ALT_FPGAMGR_IMGCFG_STAT_F2S_EARLY_USERMODE_SET_MSK) != 0;
  67. }
  68. int fpgamgr_wait_early_user_mode(void)
  69. {
  70. u32 sync_data = 0xffffffff;
  71. u32 i = 0;
  72. unsigned start = get_timer(0);
  73. unsigned long cd_ratio;
  74. /* Getting existing CDRATIO */
  75. cd_ratio = (readl(&fpga_manager_base->imgcfg_ctrl_02) &
  76. ALT_FPGAMGR_IMGCFG_CTL_02_CDRATIO_SET_MSK) >>
  77. ALT_FPGAMGR_IMGCFG_CTL_02_CDRATIO_LSB;
  78. /* Using CDRATIO_X1 for better compatibility */
  79. fpgamgr_set_cd_ratio(CDRATIO_x1);
  80. while (!is_fpgamgr_early_user_mode()) {
  81. if (get_timer(start) > FPGA_TIMEOUT_MSEC)
  82. return -ETIMEDOUT;
  83. fpgamgr_program_write((const long unsigned int *)&sync_data,
  84. sizeof(sync_data));
  85. udelay(FPGA_TIMEOUT_MSEC);
  86. i++;
  87. }
  88. debug("FPGA: Additional %i sync word needed\n", i);
  89. /* restoring original CDRATIO */
  90. fpgamgr_set_cd_ratio(cd_ratio);
  91. return 0;
  92. }
  93. /* Read f2s_nconfig_pin and f2s_nstatus_pin; loop until de-asserted */
  94. static int wait_for_nconfig_pin_and_nstatus_pin(void)
  95. {
  96. unsigned long mask = ALT_FPGAMGR_IMGCFG_STAT_F2S_NCONFIG_PIN_SET_MSK |
  97. ALT_FPGAMGR_IMGCFG_STAT_F2S_NSTATUS_PIN_SET_MSK;
  98. /*
  99. * Poll until f2s_nconfig_pin and f2s_nstatus_pin; loop until
  100. * de-asserted, timeout at 1000ms
  101. */
  102. return wait_for_bit_le32(&fpga_manager_base->imgcfg_stat, mask,
  103. true, FPGA_TIMEOUT_MSEC, false);
  104. }
  105. static int wait_for_f2s_nstatus_pin(unsigned long value)
  106. {
  107. /* Poll until f2s to specific value, timeout at 1000ms */
  108. return wait_for_bit_le32(&fpga_manager_base->imgcfg_stat,
  109. ALT_FPGAMGR_IMGCFG_STAT_F2S_NSTATUS_PIN_SET_MSK,
  110. value, FPGA_TIMEOUT_MSEC, false);
  111. }
  112. /* set CD ratio */
  113. static void fpgamgr_set_cd_ratio(unsigned long ratio)
  114. {
  115. clrbits_le32(&fpga_manager_base->imgcfg_ctrl_02,
  116. ALT_FPGAMGR_IMGCFG_CTL_02_CDRATIO_SET_MSK);
  117. setbits_le32(&fpga_manager_base->imgcfg_ctrl_02,
  118. (ratio << ALT_FPGAMGR_IMGCFG_CTL_02_CDRATIO_LSB) &
  119. ALT_FPGAMGR_IMGCFG_CTL_02_CDRATIO_SET_MSK);
  120. }
  121. /* get the MSEL value, verify we are set for FPP configuration mode */
  122. static int fpgamgr_verify_msel(void)
  123. {
  124. u32 msel = fpgamgr_get_msel();
  125. if (msel & ~BIT(0)) {
  126. printf("Fail: read msel=%d\n", msel);
  127. return -EPERM;
  128. }
  129. return 0;
  130. }
  131. /*
  132. * Write cdratio and cdwidth based on whether the bitstream is compressed
  133. * and/or encoded
  134. */
  135. static int fpgamgr_set_cdratio_cdwidth(unsigned int cfg_width, u32 *rbf_data,
  136. size_t rbf_size)
  137. {
  138. unsigned int cd_ratio;
  139. bool encrypt, compress;
  140. /*
  141. * According to the bitstream specification,
  142. * both encryption and compression status are
  143. * in location before offset 230 of the buffer.
  144. */
  145. if (rbf_size < MIN_BITSTREAM_SIZECHECK)
  146. return -EINVAL;
  147. encrypt = (rbf_data[ENCRYPTION_OFFSET] >> 2) & 3;
  148. encrypt = encrypt != 0;
  149. compress = (rbf_data[COMPRESSION_OFFSET] >> 1) & 1;
  150. compress = !compress;
  151. debug("FPGA: Header word %d = %08x.\n", 69, rbf_data[69]);
  152. debug("FPGA: Header word %d = %08x.\n", 229, rbf_data[229]);
  153. debug("FPGA: Read from rbf header: encrypt=%d compress=%d.\n", encrypt,
  154. compress);
  155. /*
  156. * from the register map description of cdratio in imgcfg_ctrl_02:
  157. * Normal Configuration : 32bit Passive Parallel
  158. * Partial Reconfiguration : 16bit Passive Parallel
  159. */
  160. /*
  161. * cd ratio is dependent on cfg width and whether the bitstream
  162. * is encrypted and/or compressed.
  163. *
  164. * | width | encr. | compr. | cd ratio |
  165. * | 16 | 0 | 0 | 1 |
  166. * | 16 | 0 | 1 | 4 |
  167. * | 16 | 1 | 0 | 2 |
  168. * | 16 | 1 | 1 | 4 |
  169. * | 32 | 0 | 0 | 1 |
  170. * | 32 | 0 | 1 | 8 |
  171. * | 32 | 1 | 0 | 4 |
  172. * | 32 | 1 | 1 | 8 |
  173. */
  174. if (!compress && !encrypt) {
  175. cd_ratio = CDRATIO_x1;
  176. } else {
  177. if (compress)
  178. cd_ratio = CDRATIO_x4;
  179. else
  180. cd_ratio = CDRATIO_x2;
  181. /* if 32 bit, double the cd ratio (so register
  182. field setting is incremented) */
  183. if (cfg_width == CFGWDTH_32)
  184. cd_ratio += 1;
  185. }
  186. fpgamgr_set_cfgwdth(cfg_width);
  187. fpgamgr_set_cd_ratio(cd_ratio);
  188. return 0;
  189. }
  190. static int fpgamgr_reset(void)
  191. {
  192. unsigned long reg;
  193. /* S2F_NCONFIG = 0 */
  194. clrbits_le32(&fpga_manager_base->imgcfg_ctrl_00,
  195. ALT_FPGAMGR_IMGCFG_CTL_00_S2F_NCONFIG_SET_MSK);
  196. /* Wait for f2s_nstatus == 0 */
  197. if (wait_for_f2s_nstatus_pin(0))
  198. return -ETIME;
  199. /* S2F_NCONFIG = 1 */
  200. setbits_le32(&fpga_manager_base->imgcfg_ctrl_00,
  201. ALT_FPGAMGR_IMGCFG_CTL_00_S2F_NCONFIG_SET_MSK);
  202. /* Wait for f2s_nstatus == 1 */
  203. if (wait_for_f2s_nstatus_pin(1))
  204. return -ETIME;
  205. /* read and confirm f2s_condone_pin = 0 and f2s_condone_oe = 1 */
  206. reg = readl(&fpga_manager_base->imgcfg_stat);
  207. if ((reg & ALT_FPGAMGR_IMGCFG_STAT_F2S_CONDONE_PIN_SET_MSK) != 0)
  208. return -EPERM;
  209. if ((reg & ALT_FPGAMGR_IMGCFG_STAT_F2S_CONDONE_OE_SET_MSK) == 0)
  210. return -EPERM;
  211. return 0;
  212. }
  213. /* Start the FPGA programming by initialize the FPGA Manager */
  214. int fpgamgr_program_init(u32 * rbf_data, size_t rbf_size)
  215. {
  216. int ret;
  217. /* Step 1 */
  218. if (fpgamgr_verify_msel())
  219. return -EPERM;
  220. /* Step 2 */
  221. if (fpgamgr_set_cdratio_cdwidth(CFGWDTH_32, rbf_data, rbf_size))
  222. return -EPERM;
  223. /*
  224. * Step 3:
  225. * Make sure no other external devices are trying to interfere with
  226. * programming:
  227. */
  228. if (wait_for_nconfig_pin_and_nstatus_pin())
  229. return -ETIME;
  230. /*
  231. * Step 4:
  232. * Deassert the signal drives from HPS
  233. *
  234. * S2F_NCE = 1
  235. * S2F_PR_REQUEST = 0
  236. * EN_CFG_CTRL = 0
  237. * EN_CFG_DATA = 0
  238. * S2F_NCONFIG = 1
  239. * S2F_NSTATUS_OE = 0
  240. * S2F_CONDONE_OE = 0
  241. */
  242. setbits_le32(&fpga_manager_base->imgcfg_ctrl_01,
  243. ALT_FPGAMGR_IMGCFG_CTL_01_S2F_NCE_SET_MSK);
  244. clrbits_le32(&fpga_manager_base->imgcfg_ctrl_01,
  245. ALT_FPGAMGR_IMGCFG_CTL_01_S2F_PR_REQUEST_SET_MSK);
  246. clrbits_le32(&fpga_manager_base->imgcfg_ctrl_02,
  247. ALT_FPGAMGR_IMGCFG_CTL_02_EN_CFG_DATA_SET_MSK |
  248. ALT_FPGAMGR_IMGCFG_CTL_02_EN_CFG_CTRL_SET_MSK);
  249. setbits_le32(&fpga_manager_base->imgcfg_ctrl_00,
  250. ALT_FPGAMGR_IMGCFG_CTL_00_S2F_NCONFIG_SET_MSK);
  251. clrbits_le32(&fpga_manager_base->imgcfg_ctrl_00,
  252. ALT_FPGAMGR_IMGCFG_CTL_00_S2F_NSTATUS_OE_SET_MSK |
  253. ALT_FPGAMGR_IMGCFG_CTL_00_S2F_CONDONE_OE_SET_MSK);
  254. /*
  255. * Step 5:
  256. * Enable overrides
  257. * S2F_NENABLE_CONFIG = 0
  258. * S2F_NENABLE_NCONFIG = 0
  259. */
  260. clrbits_le32(&fpga_manager_base->imgcfg_ctrl_01,
  261. ALT_FPGAMGR_IMGCFG_CTL_01_S2F_NENABLE_CONFIG_SET_MSK);
  262. clrbits_le32(&fpga_manager_base->imgcfg_ctrl_00,
  263. ALT_FPGAMGR_IMGCFG_CTL_00_S2F_NENABLE_NCONFIG_SET_MSK);
  264. /*
  265. * Disable driving signals that HPS doesn't need to drive.
  266. * S2F_NENABLE_NSTATUS = 1
  267. * S2F_NENABLE_CONDONE = 1
  268. */
  269. setbits_le32(&fpga_manager_base->imgcfg_ctrl_00,
  270. ALT_FPGAMGR_IMGCFG_CTL_00_S2F_NENABLE_NSTATUS_SET_MSK |
  271. ALT_FPGAMGR_IMGCFG_CTL_00_S2F_NENABLE_CONDONE_SET_MSK);
  272. /*
  273. * Step 6:
  274. * Drive chip select S2F_NCE = 0
  275. */
  276. clrbits_le32(&fpga_manager_base->imgcfg_ctrl_01,
  277. ALT_FPGAMGR_IMGCFG_CTL_01_S2F_NCE_SET_MSK);
  278. /* Step 7 */
  279. if (wait_for_nconfig_pin_and_nstatus_pin())
  280. return -ETIME;
  281. /* Step 8 */
  282. ret = fpgamgr_reset();
  283. if (ret)
  284. return ret;
  285. /*
  286. * Step 9:
  287. * EN_CFG_CTRL and EN_CFG_DATA = 1
  288. */
  289. setbits_le32(&fpga_manager_base->imgcfg_ctrl_02,
  290. ALT_FPGAMGR_IMGCFG_CTL_02_EN_CFG_DATA_SET_MSK |
  291. ALT_FPGAMGR_IMGCFG_CTL_02_EN_CFG_CTRL_SET_MSK);
  292. return 0;
  293. }
  294. /* Ensure the FPGA entering config done */
  295. static int fpgamgr_program_poll_cd(void)
  296. {
  297. unsigned long reg, i;
  298. for (i = 0; i < FPGA_TIMEOUT_CNT; i++) {
  299. reg = readl(&fpga_manager_base->imgcfg_stat);
  300. if (reg & ALT_FPGAMGR_IMGCFG_STAT_F2S_CONDONE_PIN_SET_MSK)
  301. return 0;
  302. if ((reg & ALT_FPGAMGR_IMGCFG_STAT_F2S_NSTATUS_PIN_SET_MSK) == 0) {
  303. printf("nstatus == 0 while waiting for condone\n");
  304. return -EPERM;
  305. }
  306. WATCHDOG_RESET();
  307. }
  308. if (i == FPGA_TIMEOUT_CNT)
  309. return -ETIME;
  310. return 0;
  311. }
  312. /* Ensure the FPGA entering user mode */
  313. static int fpgamgr_program_poll_usermode(void)
  314. {
  315. unsigned long reg;
  316. int ret = 0;
  317. if (fpgamgr_dclkcnt_set(0xf))
  318. return -ETIME;
  319. ret = wait_for_user_mode();
  320. if (ret < 0) {
  321. printf("%s: Failed to enter user mode with ", __func__);
  322. printf("error code %d\n", ret);
  323. return ret;
  324. }
  325. /*
  326. * Step 14:
  327. * Stop DATA path and Dclk
  328. * EN_CFG_CTRL and EN_CFG_DATA = 0
  329. */
  330. clrbits_le32(&fpga_manager_base->imgcfg_ctrl_02,
  331. ALT_FPGAMGR_IMGCFG_CTL_02_EN_CFG_DATA_SET_MSK |
  332. ALT_FPGAMGR_IMGCFG_CTL_02_EN_CFG_CTRL_SET_MSK);
  333. /*
  334. * Step 15:
  335. * Disable overrides
  336. * S2F_NENABLE_CONFIG = 1
  337. * S2F_NENABLE_NCONFIG = 1
  338. */
  339. setbits_le32(&fpga_manager_base->imgcfg_ctrl_01,
  340. ALT_FPGAMGR_IMGCFG_CTL_01_S2F_NENABLE_CONFIG_SET_MSK);
  341. setbits_le32(&fpga_manager_base->imgcfg_ctrl_00,
  342. ALT_FPGAMGR_IMGCFG_CTL_00_S2F_NENABLE_NCONFIG_SET_MSK);
  343. /* Disable chip select S2F_NCE = 1 */
  344. setbits_le32(&fpga_manager_base->imgcfg_ctrl_01,
  345. ALT_FPGAMGR_IMGCFG_CTL_01_S2F_NCE_SET_MSK);
  346. /*
  347. * Step 16:
  348. * Final check
  349. */
  350. reg = readl(&fpga_manager_base->imgcfg_stat);
  351. if (((reg & ALT_FPGAMGR_IMGCFG_STAT_F2S_USERMODE_SET_MSK) !=
  352. ALT_FPGAMGR_IMGCFG_STAT_F2S_USERMODE_SET_MSK) ||
  353. ((reg & ALT_FPGAMGR_IMGCFG_STAT_F2S_CONDONE_PIN_SET_MSK) !=
  354. ALT_FPGAMGR_IMGCFG_STAT_F2S_CONDONE_PIN_SET_MSK) ||
  355. ((reg & ALT_FPGAMGR_IMGCFG_STAT_F2S_NSTATUS_PIN_SET_MSK) !=
  356. ALT_FPGAMGR_IMGCFG_STAT_F2S_NSTATUS_PIN_SET_MSK))
  357. return -EPERM;
  358. return 0;
  359. }
  360. int fpgamgr_program_finish(void)
  361. {
  362. /* Ensure the FPGA entering config done */
  363. int status = fpgamgr_program_poll_cd();
  364. if (status) {
  365. printf("FPGA: Poll CD failed with error code %d\n", status);
  366. return -EPERM;
  367. }
  368. /* Ensure the FPGA entering user mode */
  369. status = fpgamgr_program_poll_usermode();
  370. if (status) {
  371. printf("FPGA: Poll usermode failed with error code %d\n",
  372. status);
  373. return -EPERM;
  374. }
  375. printf("Full Configuration Succeeded.\n");
  376. return 0;
  377. }
  378. ofnode get_fpga_mgr_ofnode(ofnode from)
  379. {
  380. return ofnode_by_compatible(from, "altr,socfpga-a10-fpga-mgr");
  381. }
  382. const char *get_fpga_filename(void)
  383. {
  384. const char *fpga_filename = NULL;
  385. ofnode fpgamgr_node = get_fpga_mgr_ofnode(ofnode_null());
  386. if (ofnode_valid(fpgamgr_node))
  387. fpga_filename = ofnode_read_string(fpgamgr_node,
  388. "altr,bitstream");
  389. return fpga_filename;
  390. }
  391. static void get_rbf_image_info(struct rbf_info *rbf, u16 *buffer)
  392. {
  393. /*
  394. * Magic ID starting at:
  395. * -> 1st dword[15:0] in periph.rbf
  396. * -> 2nd dword[15:0] in core.rbf
  397. * Note: dword == 32 bits
  398. */
  399. u32 word_reading_max = 2;
  400. u32 i;
  401. for (i = 0; i < word_reading_max; i++) {
  402. if (*(buffer + i) == FPGA_SOCFPGA_A10_RBF_UNENCRYPTED) {
  403. rbf->security = unencrypted;
  404. } else if (*(buffer + i) == FPGA_SOCFPGA_A10_RBF_ENCRYPTED) {
  405. rbf->security = encrypted;
  406. } else if (*(buffer + i + 1) ==
  407. FPGA_SOCFPGA_A10_RBF_UNENCRYPTED) {
  408. rbf->security = unencrypted;
  409. } else if (*(buffer + i + 1) ==
  410. FPGA_SOCFPGA_A10_RBF_ENCRYPTED) {
  411. rbf->security = encrypted;
  412. } else {
  413. rbf->security = invalid;
  414. continue;
  415. }
  416. /* PERIPH RBF(buffer + i + 1), CORE RBF(buffer + i + 2) */
  417. if (*(buffer + i + 1) == FPGA_SOCFPGA_A10_RBF_PERIPH) {
  418. rbf->section = periph_section;
  419. break;
  420. } else if (*(buffer + i + 1) == FPGA_SOCFPGA_A10_RBF_CORE) {
  421. rbf->section = core_section;
  422. break;
  423. } else if (*(buffer + i + 2) == FPGA_SOCFPGA_A10_RBF_PERIPH) {
  424. rbf->section = periph_section;
  425. break;
  426. } else if (*(buffer + i + 2) == FPGA_SOCFPGA_A10_RBF_CORE) {
  427. rbf->section = core_section;
  428. break;
  429. }
  430. rbf->section = unknown;
  431. break;
  432. WATCHDOG_RESET();
  433. }
  434. }
  435. #ifdef CONFIG_FS_LOADER
  436. static int first_loading_rbf_to_buffer(struct udevice *dev,
  437. struct fpga_loadfs_info *fpga_loadfs,
  438. u32 *buffer, size_t *buffer_bsize)
  439. {
  440. u32 *buffer_p = (u32 *)*buffer;
  441. u32 *loadable = buffer_p;
  442. size_t buffer_size = *buffer_bsize;
  443. size_t fit_size;
  444. int ret, i, count, confs_noffset, images_noffset, rbf_offset, rbf_size;
  445. const char *fpga_node_name = NULL;
  446. const char *uname = NULL;
  447. /* Load image header into buffer */
  448. ret = request_firmware_into_buf(dev,
  449. fpga_loadfs->fpga_fsinfo->filename,
  450. buffer_p, sizeof(struct image_header),
  451. 0);
  452. if (ret < 0) {
  453. debug("FPGA: Failed to read image header from flash.\n");
  454. return -ENOENT;
  455. }
  456. if (image_get_magic((struct image_header *)buffer_p) != FDT_MAGIC) {
  457. debug("FPGA: No FDT magic was found.\n");
  458. return -EBADF;
  459. }
  460. fit_size = fdt_totalsize(buffer_p);
  461. if (fit_size > buffer_size) {
  462. debug("FPGA: FIT image is larger than available buffer.\n");
  463. debug("Please use FIT external data or increasing buffer.\n");
  464. return -ENOMEM;
  465. }
  466. /* Load entire FIT into buffer */
  467. ret = request_firmware_into_buf(dev,
  468. fpga_loadfs->fpga_fsinfo->filename,
  469. buffer_p, fit_size, 0);
  470. if (ret < 0)
  471. return ret;
  472. ret = fit_check_format(buffer_p);
  473. if (!ret) {
  474. debug("FPGA: No valid FIT image was found.\n");
  475. return -EBADF;
  476. }
  477. confs_noffset = fdt_path_offset(buffer_p, FIT_CONFS_PATH);
  478. images_noffset = fdt_path_offset(buffer_p, FIT_IMAGES_PATH);
  479. if (confs_noffset < 0 || images_noffset < 0) {
  480. debug("FPGA: No Configurations or images nodes were found.\n");
  481. return -ENOENT;
  482. }
  483. /* Get default configuration unit name from default property */
  484. confs_noffset = fit_conf_get_node(buffer_p, NULL);
  485. if (confs_noffset < 0) {
  486. debug("FPGA: No default configuration was found in config.\n");
  487. return -ENOENT;
  488. }
  489. count = fit_conf_get_prop_node_count(buffer_p, confs_noffset,
  490. FIT_FPGA_PROP);
  491. if (count < 0) {
  492. debug("FPGA: Invalid configuration format for FPGA node.\n");
  493. return count;
  494. }
  495. debug("FPGA: FPGA node count: %d\n", count);
  496. for (i = 0; i < count; i++) {
  497. images_noffset = fit_conf_get_prop_node_index(buffer_p,
  498. confs_noffset,
  499. FIT_FPGA_PROP, i);
  500. uname = fit_get_name(buffer_p, images_noffset, NULL);
  501. if (uname) {
  502. debug("FPGA: %s\n", uname);
  503. if (strstr(uname, "fpga-periph") &&
  504. (!is_fpgamgr_early_user_mode() ||
  505. is_fpgamgr_user_mode())) {
  506. fpga_node_name = uname;
  507. printf("FPGA: Start to program ");
  508. printf("peripheral/full bitstream ...\n");
  509. break;
  510. } else if (strstr(uname, "fpga-core") &&
  511. (is_fpgamgr_early_user_mode() &&
  512. !is_fpgamgr_user_mode())) {
  513. fpga_node_name = uname;
  514. printf("FPGA: Start to program core ");
  515. printf("bitstream ...\n");
  516. break;
  517. }
  518. }
  519. WATCHDOG_RESET();
  520. }
  521. if (!fpga_node_name) {
  522. debug("FPGA: No suitable bitstream was found, count: %d.\n", i);
  523. return 1;
  524. }
  525. images_noffset = fit_image_get_node(buffer_p, fpga_node_name);
  526. if (images_noffset < 0) {
  527. debug("FPGA: No node '%s' was found in FIT.\n",
  528. fpga_node_name);
  529. return -ENOENT;
  530. }
  531. if (!fit_image_get_data_position(buffer_p, images_noffset,
  532. &rbf_offset)) {
  533. debug("FPGA: Data position was found.\n");
  534. } else if (!fit_image_get_data_offset(buffer_p, images_noffset,
  535. &rbf_offset)) {
  536. /*
  537. * For FIT with external data, figure out where
  538. * the external images start. This is the base
  539. * for the data-offset properties in each image.
  540. */
  541. rbf_offset += ((fdt_totalsize(buffer_p) + 3) & ~3);
  542. debug("FPGA: Data offset was found.\n");
  543. } else {
  544. debug("FPGA: No data position/offset was found.\n");
  545. return -ENOENT;
  546. }
  547. ret = fit_image_get_data_size(buffer_p, images_noffset, &rbf_size);
  548. if (ret < 0) {
  549. debug("FPGA: No data size was found (err=%d).\n", ret);
  550. return -ENOENT;
  551. }
  552. if (gd->ram_size < rbf_size) {
  553. debug("FPGA: Using default OCRAM buffer and size.\n");
  554. } else {
  555. ret = fit_image_get_load(buffer_p, images_noffset,
  556. (ulong *)loadable);
  557. if (ret < 0) {
  558. buffer_p = (u32 *)DEFAULT_DDR_LOAD_ADDRESS;
  559. debug("FPGA: No loadable was found.\n");
  560. debug("FPGA: Using default DDR load address: 0x%x .\n",
  561. DEFAULT_DDR_LOAD_ADDRESS);
  562. } else {
  563. buffer_p = (u32 *)*loadable;
  564. debug("FPGA: Found loadable address = 0x%x.\n",
  565. *loadable);
  566. }
  567. buffer_size = rbf_size;
  568. }
  569. debug("FPGA: External data: offset = 0x%x, size = 0x%x.\n",
  570. rbf_offset, rbf_size);
  571. fpga_loadfs->remaining = rbf_size;
  572. /*
  573. * Determine buffer size vs bitstream size, and calculating number of
  574. * chunk by chunk transfer is required due to smaller buffer size
  575. * compare to bitstream
  576. */
  577. if (rbf_size <= buffer_size) {
  578. /* Loading whole bitstream into buffer */
  579. buffer_size = rbf_size;
  580. fpga_loadfs->remaining = 0;
  581. } else {
  582. fpga_loadfs->remaining -= buffer_size;
  583. }
  584. fpga_loadfs->offset = rbf_offset;
  585. /* Loading bitstream into buffer */
  586. ret = request_firmware_into_buf(dev,
  587. fpga_loadfs->fpga_fsinfo->filename,
  588. buffer_p, buffer_size,
  589. fpga_loadfs->offset);
  590. if (ret < 0) {
  591. debug("FPGA: Failed to read bitstream from flash.\n");
  592. return -ENOENT;
  593. }
  594. /* Getting info about bitstream types */
  595. get_rbf_image_info(&fpga_loadfs->rbfinfo, (u16 *)buffer_p);
  596. /* Update next reading bitstream offset */
  597. fpga_loadfs->offset += buffer_size;
  598. /* Update the final addr for bitstream */
  599. *buffer = (u32)buffer_p;
  600. /* Update the size of bitstream to be programmed into FPGA */
  601. *buffer_bsize = buffer_size;
  602. return 0;
  603. }
  604. static int subsequent_loading_rbf_to_buffer(struct udevice *dev,
  605. struct fpga_loadfs_info *fpga_loadfs,
  606. u32 *buffer, size_t *buffer_bsize)
  607. {
  608. int ret = 0;
  609. u32 *buffer_p = (u32 *)*buffer;
  610. /* Read the bitstream chunk by chunk. */
  611. if (fpga_loadfs->remaining > *buffer_bsize) {
  612. fpga_loadfs->remaining -= *buffer_bsize;
  613. } else {
  614. *buffer_bsize = fpga_loadfs->remaining;
  615. fpga_loadfs->remaining = 0;
  616. }
  617. ret = request_firmware_into_buf(dev,
  618. fpga_loadfs->fpga_fsinfo->filename,
  619. buffer_p, *buffer_bsize,
  620. fpga_loadfs->offset);
  621. if (ret < 0) {
  622. debug("FPGA: Failed to read bitstream from flash.\n");
  623. return -ENOENT;
  624. }
  625. /* Update next reading bitstream offset */
  626. fpga_loadfs->offset += *buffer_bsize;
  627. return 0;
  628. }
  629. int socfpga_loadfs(fpga_fs_info *fpga_fsinfo, const void *buf, size_t bsize,
  630. u32 offset)
  631. {
  632. struct fpga_loadfs_info fpga_loadfs;
  633. struct udevice *dev;
  634. int status, ret, size;
  635. u32 buffer = (uintptr_t)buf;
  636. size_t buffer_sizebytes = bsize;
  637. size_t buffer_sizebytes_ori = bsize;
  638. size_t total_sizeof_image = 0;
  639. ofnode node;
  640. const fdt32_t *phandle_p;
  641. u32 phandle;
  642. node = get_fpga_mgr_ofnode(ofnode_null());
  643. if (ofnode_valid(node)) {
  644. phandle_p = ofnode_get_property(node, "firmware-loader", &size);
  645. if (!phandle_p) {
  646. node = ofnode_path("/chosen");
  647. if (!ofnode_valid(node)) {
  648. debug("FPGA: /chosen node was not found.\n");
  649. return -ENOENT;
  650. }
  651. phandle_p = ofnode_get_property(node, "firmware-loader",
  652. &size);
  653. if (!phandle_p) {
  654. debug("FPGA: firmware-loader property was not");
  655. debug(" found.\n");
  656. return -ENOENT;
  657. }
  658. }
  659. } else {
  660. debug("FPGA: FPGA manager node was not found.\n");
  661. return -ENOENT;
  662. }
  663. phandle = fdt32_to_cpu(*phandle_p);
  664. ret = uclass_get_device_by_phandle_id(UCLASS_FS_FIRMWARE_LOADER,
  665. phandle, &dev);
  666. if (ret)
  667. return ret;
  668. memset(&fpga_loadfs, 0, sizeof(fpga_loadfs));
  669. fpga_loadfs.fpga_fsinfo = fpga_fsinfo;
  670. fpga_loadfs.offset = offset;
  671. printf("FPGA: Checking FPGA configuration setting ...\n");
  672. /*
  673. * Note: Both buffer and buffer_sizebytes values can be altered by
  674. * function below.
  675. */
  676. ret = first_loading_rbf_to_buffer(dev, &fpga_loadfs, &buffer,
  677. &buffer_sizebytes);
  678. if (ret == 1) {
  679. printf("FPGA: Skipping configuration ...\n");
  680. return 0;
  681. } else if (ret) {
  682. return ret;
  683. }
  684. if (fpga_loadfs.rbfinfo.section == core_section &&
  685. !(is_fpgamgr_early_user_mode() && !is_fpgamgr_user_mode())) {
  686. debug("FPGA : Must be in Early Release mode to program ");
  687. debug("core bitstream.\n");
  688. return -EPERM;
  689. }
  690. /* Disable all signals from HPS peripheral controller to FPGA */
  691. writel(0, socfpga_get_sysmgr_addr() + SYSMGR_A10_FPGAINTF_EN_GLOBAL);
  692. /* Disable all axi bridges (hps2fpga, lwhps2fpga & fpga2hps) */
  693. socfpga_bridges_reset();
  694. if (fpga_loadfs.rbfinfo.section == periph_section) {
  695. /* Initialize the FPGA Manager */
  696. status = fpgamgr_program_init((u32 *)buffer, buffer_sizebytes);
  697. if (status) {
  698. debug("FPGA: Init with peripheral bitstream failed.\n");
  699. return -EPERM;
  700. }
  701. }
  702. /* Transfer bitstream to FPGA Manager */
  703. fpgamgr_program_write((void *)buffer, buffer_sizebytes);
  704. total_sizeof_image += buffer_sizebytes;
  705. while (fpga_loadfs.remaining) {
  706. ret = subsequent_loading_rbf_to_buffer(dev,
  707. &fpga_loadfs,
  708. &buffer,
  709. &buffer_sizebytes_ori);
  710. if (ret)
  711. return ret;
  712. /* Transfer data to FPGA Manager */
  713. fpgamgr_program_write((void *)buffer,
  714. buffer_sizebytes_ori);
  715. total_sizeof_image += buffer_sizebytes_ori;
  716. WATCHDOG_RESET();
  717. }
  718. if (fpga_loadfs.rbfinfo.section == periph_section) {
  719. if (fpgamgr_wait_early_user_mode() != -ETIMEDOUT) {
  720. config_pins(gd->fdt_blob, "shared");
  721. puts("FPGA: Early Release Succeeded.\n");
  722. } else {
  723. debug("FPGA: Failed to see Early Release.\n");
  724. return -EIO;
  725. }
  726. /* For monolithic bitstream */
  727. if (is_fpgamgr_user_mode()) {
  728. /* Ensure the FPGA entering config done */
  729. status = fpgamgr_program_finish();
  730. if (status)
  731. return status;
  732. config_pins(gd->fdt_blob, "fpga");
  733. puts("FPGA: Enter user mode.\n");
  734. }
  735. } else if (fpga_loadfs.rbfinfo.section == core_section) {
  736. /* Ensure the FPGA entering config done */
  737. status = fpgamgr_program_finish();
  738. if (status)
  739. return status;
  740. config_pins(gd->fdt_blob, "fpga");
  741. puts("FPGA: Enter user mode.\n");
  742. } else {
  743. debug("FPGA: Config Error: Unsupported bitstream type.\n");
  744. return -ENOEXEC;
  745. }
  746. return (int)total_sizeof_image;
  747. }
  748. void fpgamgr_program(const void *buf, size_t bsize, u32 offset)
  749. {
  750. fpga_fs_info fpga_fsinfo;
  751. fpga_fsinfo.filename = get_fpga_filename();
  752. if (fpga_fsinfo.filename)
  753. socfpga_loadfs(&fpga_fsinfo, buf, bsize, offset);
  754. }
  755. #endif
  756. /* This function is used to load the core bitstream from the OCRAM. */
  757. int socfpga_load(Altera_desc *desc, const void *rbf_data, size_t rbf_size)
  758. {
  759. unsigned long status;
  760. struct rbf_info rbfinfo;
  761. memset(&rbfinfo, 0, sizeof(rbfinfo));
  762. /* Disable all signals from hps peripheral controller to fpga */
  763. writel(0, socfpga_get_sysmgr_addr() + SYSMGR_A10_FPGAINTF_EN_GLOBAL);
  764. /* Disable all axi bridge (hps2fpga, lwhps2fpga & fpga2hps) */
  765. socfpga_bridges_reset();
  766. /* Getting info about bitstream types */
  767. get_rbf_image_info(&rbfinfo, (u16 *)rbf_data);
  768. if (rbfinfo.section == periph_section) {
  769. /* Initialize the FPGA Manager */
  770. status = fpgamgr_program_init((u32 *)rbf_data, rbf_size);
  771. if (status)
  772. return status;
  773. }
  774. if (rbfinfo.section == core_section &&
  775. !(is_fpgamgr_early_user_mode() && !is_fpgamgr_user_mode())) {
  776. debug("FPGA : Must be in early release mode to program ");
  777. debug("core bitstream.\n");
  778. return -EPERM;
  779. }
  780. /* Write the bitstream to FPGA Manager */
  781. fpgamgr_program_write(rbf_data, rbf_size);
  782. status = fpgamgr_program_finish();
  783. if (status)
  784. return status;
  785. config_pins(gd->fdt_blob, "fpga");
  786. puts("FPGA: Enter user mode.\n");
  787. return status;
  788. }