intel_sdm_mb.c 6.8 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright (C) 2018 Intel Corporation <www.intel.com>
  4. */
  5. #include <common.h>
  6. #include <altera.h>
  7. #include <log.h>
  8. #include <watchdog.h>
  9. #include <asm/arch/mailbox_s10.h>
  10. #include <linux/delay.h>
  11. #define RECONFIG_STATUS_POLL_RESP_TIMEOUT_MS 60000
  12. #define RECONFIG_STATUS_INTERVAL_DELAY_US 1000000
  13. static const struct mbox_cfgstat_state {
  14. int err_no;
  15. const char *error_name;
  16. } mbox_cfgstat_state[] = {
  17. {MBOX_CFGSTAT_STATE_IDLE, "FPGA in idle mode."},
  18. {MBOX_CFGSTAT_STATE_CONFIG, "FPGA in config mode."},
  19. {MBOX_CFGSTAT_STATE_FAILACK, "Acknowledgment failed!"},
  20. {MBOX_CFGSTAT_STATE_ERROR_INVALID, "Invalid bitstream!"},
  21. {MBOX_CFGSTAT_STATE_ERROR_CORRUPT, "Corrupted bitstream!"},
  22. {MBOX_CFGSTAT_STATE_ERROR_AUTH, "Authentication failed!"},
  23. {MBOX_CFGSTAT_STATE_ERROR_CORE_IO, "I/O error!"},
  24. {MBOX_CFGSTAT_STATE_ERROR_HARDWARE, "Hardware error!"},
  25. {MBOX_CFGSTAT_STATE_ERROR_FAKE, "Fake error!"},
  26. {MBOX_CFGSTAT_STATE_ERROR_BOOT_INFO, "Error in boot info!"},
  27. {MBOX_CFGSTAT_STATE_ERROR_QSPI_ERROR, "Error in QSPI!"},
  28. {MBOX_RESP_ERROR, "Mailbox general error!"},
  29. {-ETIMEDOUT, "I/O timeout error"},
  30. {-1, "Unknown error!"}
  31. };
  32. #define MBOX_CFGSTAT_MAX ARRAY_SIZE(mbox_cfgstat_state)
  33. static const char *mbox_cfgstat_to_str(int err)
  34. {
  35. int i;
  36. for (i = 0; i < MBOX_CFGSTAT_MAX - 1; i++) {
  37. if (mbox_cfgstat_state[i].err_no == err)
  38. return mbox_cfgstat_state[i].error_name;
  39. }
  40. return mbox_cfgstat_state[MBOX_CFGSTAT_MAX - 1].error_name;
  41. }
  42. /*
  43. * Add the ongoing transaction's command ID into pending list and return
  44. * the command ID for next transfer.
  45. */
  46. static u8 add_transfer(u32 *xfer_pending_list, size_t list_size, u8 id)
  47. {
  48. int i;
  49. for (i = 0; i < list_size; i++) {
  50. if (xfer_pending_list[i])
  51. continue;
  52. xfer_pending_list[i] = id;
  53. debug("ID(%d) added to transaction pending list\n", id);
  54. /*
  55. * Increment command ID for next transaction.
  56. * Valid command ID (4 bits) is from 1 to 15.
  57. */
  58. id = (id % 15) + 1;
  59. break;
  60. }
  61. return id;
  62. }
  63. /*
  64. * Check whether response ID match the command ID in the transfer
  65. * pending list. If a match is found in the transfer pending list,
  66. * it clears the transfer pending list and return the matched
  67. * command ID.
  68. */
  69. static int get_and_clr_transfer(u32 *xfer_pending_list, size_t list_size,
  70. u8 id)
  71. {
  72. int i;
  73. for (i = 0; i < list_size; i++) {
  74. if (id != xfer_pending_list[i])
  75. continue;
  76. xfer_pending_list[i] = 0;
  77. return id;
  78. }
  79. return 0;
  80. }
  81. /*
  82. * Polling the FPGA configuration status.
  83. * Return 0 for success, non-zero for error.
  84. */
  85. static int reconfig_status_polling_resp(void)
  86. {
  87. int ret;
  88. unsigned long start = get_timer(0);
  89. while (1) {
  90. ret = mbox_get_fpga_config_status(MBOX_RECONFIG_STATUS);
  91. if (!ret)
  92. return 0; /* configuration success */
  93. if (ret != MBOX_CFGSTAT_STATE_CONFIG)
  94. return ret;
  95. if (get_timer(start) > RECONFIG_STATUS_POLL_RESP_TIMEOUT_MS)
  96. break; /* time out */
  97. puts(".");
  98. udelay(RECONFIG_STATUS_INTERVAL_DELAY_US);
  99. WATCHDOG_RESET();
  100. }
  101. return -ETIMEDOUT;
  102. }
  103. static u32 get_resp_hdr(u32 *r_index, u32 *w_index, u32 *resp_count,
  104. u32 *resp_buf, u32 buf_size, u32 client_id)
  105. {
  106. u32 buf[MBOX_RESP_BUFFER_SIZE];
  107. u32 mbox_hdr;
  108. u32 resp_len;
  109. u32 hdr_len;
  110. u32 i;
  111. if (*resp_count < buf_size) {
  112. u32 rcv_len_max = buf_size - *resp_count;
  113. if (rcv_len_max > MBOX_RESP_BUFFER_SIZE)
  114. rcv_len_max = MBOX_RESP_BUFFER_SIZE;
  115. resp_len = mbox_rcv_resp(buf, rcv_len_max);
  116. for (i = 0; i < resp_len; i++) {
  117. resp_buf[(*w_index)++] = buf[i];
  118. *w_index %= buf_size;
  119. (*resp_count)++;
  120. }
  121. }
  122. /* No response in buffer */
  123. if (*resp_count == 0)
  124. return 0;
  125. mbox_hdr = resp_buf[*r_index];
  126. hdr_len = MBOX_RESP_LEN_GET(mbox_hdr);
  127. /* Insufficient header length to return a mailbox header */
  128. if ((*resp_count - 1) < hdr_len)
  129. return 0;
  130. *r_index += (hdr_len + 1);
  131. *r_index %= buf_size;
  132. *resp_count -= (hdr_len + 1);
  133. /* Make sure response belongs to us */
  134. if (MBOX_RESP_CLIENT_GET(mbox_hdr) != client_id)
  135. return 0;
  136. return mbox_hdr;
  137. }
  138. /* Send bit stream data to SDM via RECONFIG_DATA mailbox command */
  139. static int send_reconfig_data(const void *rbf_data, size_t rbf_size,
  140. u32 xfer_max, u32 buf_size_max)
  141. {
  142. u32 response_buffer[MBOX_RESP_BUFFER_SIZE];
  143. u32 xfer_pending[MBOX_RESP_BUFFER_SIZE];
  144. u32 resp_rindex = 0;
  145. u32 resp_windex = 0;
  146. u32 resp_count = 0;
  147. u32 xfer_count = 0;
  148. int resp_err = 0;
  149. u8 cmd_id = 1;
  150. u32 args[3];
  151. int ret;
  152. debug("SDM xfer_max = %d\n", xfer_max);
  153. debug("SDM buf_size_max = %x\n\n", buf_size_max);
  154. memset(xfer_pending, 0, sizeof(xfer_pending));
  155. while (rbf_size || xfer_count) {
  156. if (!resp_err && rbf_size && xfer_count < xfer_max) {
  157. args[0] = MBOX_ARG_DESC_COUNT(1);
  158. args[1] = (u64)rbf_data;
  159. if (rbf_size >= buf_size_max) {
  160. args[2] = buf_size_max;
  161. rbf_size -= buf_size_max;
  162. rbf_data += buf_size_max;
  163. } else {
  164. args[2] = (u64)rbf_size;
  165. rbf_size = 0;
  166. }
  167. resp_err = mbox_send_cmd_only(cmd_id, MBOX_RECONFIG_DATA,
  168. MBOX_CMD_INDIRECT, 3, args);
  169. if (!resp_err) {
  170. xfer_count++;
  171. cmd_id = add_transfer(xfer_pending,
  172. MBOX_RESP_BUFFER_SIZE,
  173. cmd_id);
  174. }
  175. puts(".");
  176. } else {
  177. u32 resp_hdr = get_resp_hdr(&resp_rindex, &resp_windex,
  178. &resp_count,
  179. response_buffer,
  180. MBOX_RESP_BUFFER_SIZE,
  181. MBOX_CLIENT_ID_UBOOT);
  182. /*
  183. * If no valid response header found or
  184. * non-zero length from RECONFIG_DATA
  185. */
  186. if (!resp_hdr || MBOX_RESP_LEN_GET(resp_hdr))
  187. continue;
  188. /* Check for response's status */
  189. if (!resp_err) {
  190. resp_err = MBOX_RESP_ERR_GET(resp_hdr);
  191. debug("Response error code: %08x\n", resp_err);
  192. }
  193. ret = get_and_clr_transfer(xfer_pending,
  194. MBOX_RESP_BUFFER_SIZE,
  195. MBOX_RESP_ID_GET(resp_hdr));
  196. if (ret) {
  197. /* Claim and reuse the ID */
  198. cmd_id = (u8)ret;
  199. xfer_count--;
  200. }
  201. if (resp_err && !xfer_count)
  202. return resp_err;
  203. }
  204. WATCHDOG_RESET();
  205. }
  206. return 0;
  207. }
  208. /*
  209. * This is the interface used by FPGA driver.
  210. * Return 0 for success, non-zero for error.
  211. */
  212. int intel_sdm_mb_load(Altera_desc *desc, const void *rbf_data, size_t rbf_size)
  213. {
  214. int ret;
  215. u32 resp_len = 2;
  216. u32 resp_buf[2];
  217. debug("Sending MBOX_RECONFIG...\n");
  218. ret = mbox_send_cmd(MBOX_ID_UBOOT, MBOX_RECONFIG, MBOX_CMD_DIRECT, 0,
  219. NULL, 0, &resp_len, resp_buf);
  220. if (ret) {
  221. puts("Failure in RECONFIG mailbox command!\n");
  222. return ret;
  223. }
  224. ret = send_reconfig_data(rbf_data, rbf_size, resp_buf[0], resp_buf[1]);
  225. if (ret) {
  226. printf("RECONFIG_DATA error: %08x, %s\n", ret,
  227. mbox_cfgstat_to_str(ret));
  228. return ret;
  229. }
  230. /* Make sure we don't send MBOX_RECONFIG_STATUS too fast */
  231. udelay(RECONFIG_STATUS_INTERVAL_DELAY_US);
  232. debug("Polling with MBOX_RECONFIG_STATUS...\n");
  233. ret = reconfig_status_polling_resp();
  234. if (ret) {
  235. printf("RECONFIG_STATUS Error: %08x, %s\n", ret,
  236. mbox_cfgstat_to_str(ret));
  237. return ret;
  238. }
  239. puts("FPGA reconfiguration OK!\n");
  240. return ret;
  241. }