ACEX1K.c 6.2 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * (C) Copyright 2003
  4. * Steven Scholz, imc Measurement & Control, steven.scholz@imc-berlin.de
  5. *
  6. * (C) Copyright 2002
  7. * Rich Ireland, Enterasys Networks, rireland@enterasys.com.
  8. */
  9. #include <common.h> /* core U-Boot definitions */
  10. #include <console.h>
  11. #include <ACEX1K.h> /* ACEX device family */
  12. #include <linux/delay.h>
  13. /* Define FPGA_DEBUG to get debug printf's */
  14. #ifdef FPGA_DEBUG
  15. #define PRINTF(fmt,args...) printf (fmt ,##args)
  16. #else
  17. #define PRINTF(fmt,args...)
  18. #endif
  19. /* Note: The assumption is that we cannot possibly run fast enough to
  20. * overrun the device (the Slave Parallel mode can free run at 50MHz).
  21. * If there is a need to operate slower, define CONFIG_FPGA_DELAY in
  22. * the board config file to slow things down.
  23. */
  24. #ifndef CONFIG_FPGA_DELAY
  25. #define CONFIG_FPGA_DELAY()
  26. #endif
  27. #ifndef CONFIG_SYS_FPGA_WAIT
  28. #define CONFIG_SYS_FPGA_WAIT CONFIG_SYS_HZ/10 /* 100 ms */
  29. #endif
  30. static int ACEX1K_ps_load(Altera_desc *desc, const void *buf, size_t bsize);
  31. static int ACEX1K_ps_dump(Altera_desc *desc, const void *buf, size_t bsize);
  32. /* static int ACEX1K_ps_info(Altera_desc *desc); */
  33. /* ------------------------------------------------------------------------- */
  34. /* ACEX1K Generic Implementation */
  35. int ACEX1K_load(Altera_desc *desc, const void *buf, size_t bsize)
  36. {
  37. int ret_val = FPGA_FAIL;
  38. switch (desc->iface) {
  39. case passive_serial:
  40. PRINTF ("%s: Launching Passive Serial Loader\n", __FUNCTION__);
  41. ret_val = ACEX1K_ps_load (desc, buf, bsize);
  42. break;
  43. /* Add new interface types here */
  44. default:
  45. printf ("%s: Unsupported interface type, %d\n",
  46. __FUNCTION__, desc->iface);
  47. }
  48. return ret_val;
  49. }
  50. int ACEX1K_dump(Altera_desc *desc, const void *buf, size_t bsize)
  51. {
  52. int ret_val = FPGA_FAIL;
  53. switch (desc->iface) {
  54. case passive_serial:
  55. PRINTF ("%s: Launching Passive Serial Dump\n", __FUNCTION__);
  56. ret_val = ACEX1K_ps_dump (desc, buf, bsize);
  57. break;
  58. /* Add new interface types here */
  59. default:
  60. printf ("%s: Unsupported interface type, %d\n",
  61. __FUNCTION__, desc->iface);
  62. }
  63. return ret_val;
  64. }
  65. int ACEX1K_info( Altera_desc *desc )
  66. {
  67. return FPGA_SUCCESS;
  68. }
  69. /* ------------------------------------------------------------------------- */
  70. /* ACEX1K Passive Serial Generic Implementation */
  71. static int ACEX1K_ps_load(Altera_desc *desc, const void *buf, size_t bsize)
  72. {
  73. int ret_val = FPGA_FAIL; /* assume the worst */
  74. Altera_ACEX1K_Passive_Serial_fns *fn = desc->iface_fns;
  75. int i;
  76. PRINTF ("%s: start with interface functions @ 0x%p\n",
  77. __FUNCTION__, fn);
  78. if (fn) {
  79. size_t bytecount = 0;
  80. unsigned char *data = (unsigned char *) buf;
  81. int cookie = desc->cookie; /* make a local copy */
  82. unsigned long ts; /* timestamp */
  83. PRINTF ("%s: Function Table:\n"
  84. "ptr:\t0x%p\n"
  85. "struct: 0x%p\n"
  86. "config:\t0x%p\n"
  87. "status:\t0x%p\n"
  88. "clk:\t0x%p\n"
  89. "data:\t0x%p\n"
  90. "done:\t0x%p\n\n",
  91. __FUNCTION__, &fn, fn, fn->config, fn->status,
  92. fn->clk, fn->data, fn->done);
  93. #ifdef CONFIG_SYS_FPGA_PROG_FEEDBACK
  94. printf ("Loading FPGA Device %d...", cookie);
  95. #endif
  96. /*
  97. * Run the pre configuration function if there is one.
  98. */
  99. if (*fn->pre) {
  100. (*fn->pre) (cookie);
  101. }
  102. /* Establish the initial state */
  103. (*fn->config) (true, true, cookie); /* Assert nCONFIG */
  104. udelay(2); /* T_cfg > 2us */
  105. /* nSTATUS should be asserted now */
  106. (*fn->done) (cookie);
  107. if ( !(*fn->status) (cookie) ) {
  108. puts ("** nSTATUS is not asserted.\n");
  109. (*fn->abort) (cookie);
  110. return FPGA_FAIL;
  111. }
  112. (*fn->config) (false, true, cookie); /* Deassert nCONFIG */
  113. udelay(2); /* T_cf2st1 < 4us */
  114. /* Wait for nSTATUS to be released (i.e. deasserted) */
  115. ts = get_timer (0); /* get current time */
  116. do {
  117. CONFIG_FPGA_DELAY ();
  118. if (get_timer (ts) > CONFIG_SYS_FPGA_WAIT) { /* check the time */
  119. puts ("** Timeout waiting for STATUS to go high.\n");
  120. (*fn->abort) (cookie);
  121. return FPGA_FAIL;
  122. }
  123. (*fn->done) (cookie);
  124. } while ((*fn->status) (cookie));
  125. /* Get ready for the burn */
  126. CONFIG_FPGA_DELAY ();
  127. /* Load the data */
  128. while (bytecount < bsize) {
  129. unsigned char val=0;
  130. #ifdef CONFIG_SYS_FPGA_CHECK_CTRLC
  131. if (ctrlc ()) {
  132. (*fn->abort) (cookie);
  133. return FPGA_FAIL;
  134. }
  135. #endif
  136. /* Altera detects an error if INIT goes low (active)
  137. while DONE is low (inactive) */
  138. #if 0 /* not yet implemented */
  139. if ((*fn->done) (cookie) == 0 && (*fn->init) (cookie)) {
  140. puts ("** CRC error during FPGA load.\n");
  141. (*fn->abort) (cookie);
  142. return (FPGA_FAIL);
  143. }
  144. #endif
  145. val = data [bytecount ++ ];
  146. i = 8;
  147. do {
  148. /* Deassert the clock */
  149. (*fn->clk) (false, true, cookie);
  150. CONFIG_FPGA_DELAY ();
  151. /* Write data */
  152. (*fn->data) ((val & 0x01), true, cookie);
  153. CONFIG_FPGA_DELAY ();
  154. /* Assert the clock */
  155. (*fn->clk) (true, true, cookie);
  156. CONFIG_FPGA_DELAY ();
  157. val >>= 1;
  158. i --;
  159. } while (i > 0);
  160. #ifdef CONFIG_SYS_FPGA_PROG_FEEDBACK
  161. if (bytecount % (bsize / 40) == 0)
  162. putc ('.'); /* let them know we are alive */
  163. #endif
  164. }
  165. CONFIG_FPGA_DELAY ();
  166. #ifdef CONFIG_SYS_FPGA_PROG_FEEDBACK
  167. putc (' '); /* terminate the dotted line */
  168. #endif
  169. /*
  170. * Checking FPGA's CONF_DONE signal - correctly booted ?
  171. */
  172. if ( ! (*fn->done) (cookie) ) {
  173. puts ("** Booting failed! CONF_DONE is still deasserted.\n");
  174. (*fn->abort) (cookie);
  175. return (FPGA_FAIL);
  176. }
  177. /*
  178. * "DCLK must be clocked an additional 10 times fpr ACEX 1K..."
  179. */
  180. for (i = 0; i < 12; i++) {
  181. CONFIG_FPGA_DELAY ();
  182. (*fn->clk) (true, true, cookie); /* Assert the clock pin */
  183. CONFIG_FPGA_DELAY ();
  184. (*fn->clk) (false, true, cookie); /* Deassert the clock pin */
  185. }
  186. ret_val = FPGA_SUCCESS;
  187. #ifdef CONFIG_SYS_FPGA_PROG_FEEDBACK
  188. if (ret_val == FPGA_SUCCESS) {
  189. puts ("Done.\n");
  190. }
  191. else {
  192. puts ("Fail.\n");
  193. }
  194. #endif
  195. (*fn->post) (cookie);
  196. } else {
  197. printf ("%s: NULL Interface function table!\n", __FUNCTION__);
  198. }
  199. return ret_val;
  200. }
  201. static int ACEX1K_ps_dump(Altera_desc *desc, const void *buf, size_t bsize)
  202. {
  203. /* Readback is only available through the Slave Parallel and */
  204. /* boundary-scan interfaces. */
  205. printf ("%s: Passive Serial Dumping is unavailable\n",
  206. __FUNCTION__);
  207. return FPGA_FAIL;
  208. }