k3-udma-hwdef.h 6.1 KB

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  1. /* SPDX-License-Identifier: GPL-2.0+ */
  2. /*
  3. * Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com
  4. *
  5. *
  6. * This program is free software; you can redistribute it and/or modify
  7. * it under the terms of the GNU General Public License version 2 as
  8. * published by the Free Software Foundation.
  9. *
  10. */
  11. #ifndef K3_NAVSS_UDMA_HWDEF_H_
  12. #define K3_NAVSS_UDMA_HWDEF_H_
  13. #include <linux/bitops.h>
  14. #define UDMA_PSIL_DST_THREAD_ID_OFFSET 0x8000
  15. /* Global registers */
  16. #define UDMA_REV_REG 0x0
  17. #define UDMA_PERF_CTL_REG 0x4
  18. #define UDMA_EMU_CTL_REG 0x8
  19. #define UDMA_PSIL_TO_REG 0x10
  20. #define UDMA_UTC_CTL_REG 0x1c
  21. #define UDMA_CAP_REG(i) (0x20 + (i * 4))
  22. #define UDMA_RX_FLOW_ID_FW_OES_REG 0x80
  23. #define UDMA_RX_FLOW_ID_FW_STATUS_REG 0x88
  24. /* RX Flow regs */
  25. #define UDMA_RFLOW_RFA_REG 0x0
  26. #define UDMA_RFLOW_RFB_REG 0x4
  27. #define UDMA_RFLOW_RFC_REG 0x8
  28. #define UDMA_RFLOW_RFD_REG 0xc
  29. #define UDMA_RFLOW_RFE_REG 0x10
  30. #define UDMA_RFLOW_RFF_REG 0x14
  31. #define UDMA_RFLOW_RFG_REG 0x18
  32. #define UDMA_RFLOW_RFH_REG 0x1c
  33. #define UDMA_RFLOW_REG(x) (UDMA_RFLOW_RF##x##_REG)
  34. /* TX chan regs */
  35. #define UDMA_TCHAN_TCFG_REG 0x0
  36. #define UDMA_TCHAN_TCREDIT_REG 0x4
  37. #define UDMA_TCHAN_TCQ_REG 0x14
  38. #define UDMA_TCHAN_TOES_REG(i) (0x20 + (i) * 4)
  39. #define UDMA_TCHAN_TEOES_REG 0x60
  40. #define UDMA_TCHAN_TPRI_CTRL_REG 0x64
  41. #define UDMA_TCHAN_THREAD_ID_REG 0x68
  42. #define UDMA_TCHAN_TFIFO_DEPTH_REG 0x70
  43. #define UDMA_TCHAN_TST_SCHED_REG 0x80
  44. /* RX chan regs */
  45. #define UDMA_RCHAN_RCFG_REG 0x0
  46. #define UDMA_RCHAN_RCQ_REG 0x14
  47. #define UDMA_RCHAN_ROES_REG(i) (0x20 + (i) * 4)
  48. #define UDMA_RCHAN_REOES_REG 0x60
  49. #define UDMA_RCHAN_RPRI_CTRL_REG 0x64
  50. #define UDMA_RCHAN_THREAD_ID_REG 0x68
  51. #define UDMA_RCHAN_RST_SCHED_REG 0x80
  52. #define UDMA_RCHAN_RFLOW_RNG_REG 0xf0
  53. /* TX chan RT regs */
  54. #define UDMA_TCHAN_RT_CTL_REG 0x0
  55. #define UDMA_TCHAN_RT_SWTRIG_REG 0x8
  56. #define UDMA_TCHAN_RT_STDATA_REG 0x80
  57. #define UDMA_TCHAN_RT_PEERn_REG(i) (0x200 + (i * 0x4))
  58. #define UDMA_TCHAN_RT_PEER_STATIC_TR_XY_REG \
  59. UDMA_TCHAN_RT_PEERn_REG(0) /* PSI-L: 0x400 */
  60. #define UDMA_TCHAN_RT_PEER_STATIC_TR_Z_REG \
  61. UDMA_TCHAN_RT_PEERn_REG(1) /* PSI-L: 0x401 */
  62. #define UDMA_TCHAN_RT_PEER_BCNT_REG \
  63. UDMA_TCHAN_RT_PEERn_REG(4) /* PSI-L: 0x404 */
  64. #define UDMA_TCHAN_RT_PEER_RT_EN_REG \
  65. UDMA_TCHAN_RT_PEERn_REG(8) /* PSI-L: 0x408 */
  66. #define UDMA_TCHAN_RT_PCNT_REG 0x400
  67. #define UDMA_TCHAN_RT_BCNT_REG 0x408
  68. #define UDMA_TCHAN_RT_SBCNT_REG 0x410
  69. /* RX chan RT regs */
  70. #define UDMA_RCHAN_RT_CTL_REG 0x0
  71. #define UDMA_RCHAN_RT_SWTRIG_REG 0x8
  72. #define UDMA_RCHAN_RT_STDATA_REG 0x80
  73. #define UDMA_RCHAN_RT_PEERn_REG(i) (0x200 + (i * 0x4))
  74. #define UDMA_RCHAN_RT_PEER_STATIC_TR_XY_REG \
  75. UDMA_RCHAN_RT_PEERn_REG(0) /* PSI-L: 0x400 */
  76. #define UDMA_RCHAN_RT_PEER_STATIC_TR_Z_REG \
  77. UDMA_RCHAN_RT_PEERn_REG(1) /* PSI-L: 0x401 */
  78. #define UDMA_RCHAN_RT_PEER_BCNT_REG \
  79. UDMA_RCHAN_RT_PEERn_REG(4) /* PSI-L: 0x404 */
  80. #define UDMA_RCHAN_RT_PEER_RT_EN_REG \
  81. UDMA_RCHAN_RT_PEERn_REG(8) /* PSI-L: 0x408 */
  82. #define UDMA_RCHAN_RT_PCNT_REG 0x400
  83. #define UDMA_RCHAN_RT_BCNT_REG 0x408
  84. #define UDMA_RCHAN_RT_SBCNT_REG 0x410
  85. /* UDMA_TCHAN_TCFG_REG/UDMA_RCHAN_RCFG_REG */
  86. #define UDMA_CHAN_CFG_PAUSE_ON_ERR BIT(31)
  87. #define UDMA_TCHAN_CFG_FILT_EINFO BIT(30)
  88. #define UDMA_TCHAN_CFG_FILT_PSWORDS BIT(29)
  89. #define UDMA_CHAN_CFG_ATYPE_MASK GENMASK(25, 24)
  90. #define UDMA_CHAN_CFG_ATYPE_SHIFT 24
  91. #define UDMA_CHAN_CFG_CHAN_TYPE_MASK GENMASK(19, 16)
  92. #define UDMA_CHAN_CFG_CHAN_TYPE_SHIFT 16
  93. /*
  94. * PBVR - using pass by value rings
  95. * PBRR - using pass by reference rings
  96. * 3RDP - Third Party DMA
  97. * BC - Block Copy
  98. * SB - single buffer packet mode enabled
  99. */
  100. #define UDMA_CHAN_CFG_CHAN_TYPE_PACKET_PBRR \
  101. (2 << UDMA_CHAN_CFG_CHAN_TYPE_SHIFT)
  102. #define UDMA_CHAN_CFG_CHAN_TYPE_PACKET_SB_PBRR \
  103. (3 << UDMA_CHAN_CFG_CHAN_TYPE_SHIFT)
  104. #define UDMA_CHAN_CFG_CHAN_TYPE_3RDP_PBRR \
  105. (10 << UDMA_CHAN_CFG_CHAN_TYPE_SHIFT)
  106. #define UDMA_CHAN_CFG_CHAN_TYPE_3RDP_PBVR \
  107. (11 << UDMA_CHAN_CFG_CHAN_TYPE_SHIFT)
  108. #define UDMA_CHAN_CFG_CHAN_TYPE_3RDP_BC_PBRR \
  109. (12 << UDMA_CHAN_CFG_CHAN_TYPE_SHIFT)
  110. #define UDMA_RCHAN_CFG_IGNORE_SHORT BIT(15)
  111. #define UDMA_RCHAN_CFG_IGNORE_LONG BIT(14)
  112. #define UDMA_TCHAN_CFG_SUPR_TDPKT BIT(8)
  113. #define UDMA_CHAN_CFG_FETCH_SIZE_MASK GENMASK(6, 0)
  114. #define UDMA_CHAN_CFG_FETCH_SIZE_SHIFT 0
  115. /* UDMA_TCHAN_RT_CTL_REG/UDMA_RCHAN_RT_CTL_REG */
  116. #define UDMA_CHAN_RT_CTL_EN BIT(31)
  117. #define UDMA_CHAN_RT_CTL_TDOWN BIT(30)
  118. #define UDMA_CHAN_RT_CTL_PAUSE BIT(29)
  119. #define UDMA_CHAN_RT_CTL_FTDOWN BIT(28)
  120. #define UDMA_CHAN_RT_CTL_ERROR BIT(0)
  121. /* UDMA_TCHAN_RT_PEER_RT_EN_REG/UDMA_RCHAN_RT_PEER_RT_EN_REG (PSI-L: 0x408) */
  122. #define UDMA_PEER_RT_EN_ENABLE BIT(31)
  123. #define UDMA_PEER_RT_EN_TEARDOWN BIT(30)
  124. #define UDMA_PEER_RT_EN_PAUSE BIT(29)
  125. #define UDMA_PEER_RT_EN_FLUSH BIT(28)
  126. #define UDMA_PEER_RT_EN_IDLE BIT(1)
  127. /* RX Flow reg RFA */
  128. #define UDMA_RFLOW_RFA_EINFO BIT(30)
  129. #define UDMA_RFLOW_RFA_PSINFO BIT(29)
  130. #define UDMA_RFLOW_RFA_ERR_HANDLING BIT(28)
  131. #define UDMA_RFLOW_RFA_DESC_TYPE_MASK GENMASK(27, 26)
  132. #define UDMA_RFLOW_RFA_DESC_TYPE_SHIFT 26
  133. #define UDMA_RFLOW_RFA_PS_LOC BIT(25)
  134. #define UDMA_RFLOW_RFA_SOP_OFF_MASK GENMASK(24, 16)
  135. #define UDMA_RFLOW_RFA_SOP_OFF_SHIFT 16
  136. #define UDMA_RFLOW_RFA_DEST_QNUM_MASK GENMASK(15, 0)
  137. #define UDMA_RFLOW_RFA_DEST_QNUM_SHIFT 0
  138. /* RX Flow reg RFC */
  139. #define UDMA_RFLOW_RFC_SRC_TAG_HI_SEL_SHIFT 28
  140. #define UDMA_RFLOW_RFC_SRC_TAG_LO_SEL_SHIFT 24
  141. #define UDMA_RFLOW_RFC_DST_TAG_HI_SEL_SHIFT 20
  142. #define UDMA_RFLOW_RFC_DST_TAG_LO_SE_SHIFT 16
  143. /*
  144. * UDMA_TCHAN_RT_PEER_STATIC_TR_XY_REG /
  145. * UDMA_RCHAN_RT_PEER_STATIC_TR_XY_REG
  146. */
  147. #define PDMA_STATIC_TR_X_MASK GENMASK(26, 24)
  148. #define PDMA_STATIC_TR_X_SHIFT (24)
  149. #define PDMA_STATIC_TR_Y_MASK GENMASK(11, 0)
  150. #define PDMA_STATIC_TR_Y_SHIFT (0)
  151. #define PDMA_STATIC_TR_Y(x) \
  152. (((x) << PDMA_STATIC_TR_Y_SHIFT) & PDMA_STATIC_TR_Y_MASK)
  153. #define PDMA_STATIC_TR_X(x) \
  154. (((x) << PDMA_STATIC_TR_X_SHIFT) & PDMA_STATIC_TR_X_MASK)
  155. /*
  156. * UDMA_TCHAN_RT_PEER_STATIC_TR_Z_REG /
  157. * UDMA_RCHAN_RT_PEER_STATIC_TR_Z_REG
  158. */
  159. #define PDMA_STATIC_TR_Z_MASK GENMASK(11, 0)
  160. #define PDMA_STATIC_TR_Z_SHIFT (0)
  161. #define PDMA_STATIC_TR_Z(x) \
  162. (((x) << PDMA_STATIC_TR_Z_SHIFT) & PDMA_STATIC_TR_Z_MASK)
  163. #endif /* K3_NAVSS_UDMA_HWDEF_H_ */