mpc85xx_ddr_gen2.c 2.7 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * Copyright 2008-2011 Freescale Semiconductor, Inc.
  4. */
  5. #include <common.h>
  6. #include <asm/io.h>
  7. #include <asm/processor.h>
  8. #include <fsl_ddr_sdram.h>
  9. #include <linux/delay.h>
  10. #if (CONFIG_CHIP_SELECTS_PER_CTRL > 4)
  11. #error Invalid setting for CONFIG_CHIP_SELECTS_PER_CTRL
  12. #endif
  13. void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs,
  14. unsigned int ctrl_num, int step)
  15. {
  16. unsigned int i;
  17. struct ccsr_ddr __iomem *ddr =
  18. (struct ccsr_ddr __iomem *)CONFIG_SYS_FSL_DDR_ADDR;
  19. #if defined(CONFIG_SYS_FSL_ERRATUM_NMG_DDR120) && defined(CONFIG_MPC85xx)
  20. ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
  21. uint svr;
  22. #endif
  23. if (ctrl_num) {
  24. printf("%s unexpected ctrl_num = %u\n", __FUNCTION__, ctrl_num);
  25. return;
  26. }
  27. #ifdef CONFIG_SYS_FSL_ERRATUM_NMG_DDR120
  28. /*
  29. * Set the DDR IO receiver to an acceptable bias point.
  30. * Fixed in Rev 2.1.
  31. */
  32. svr = get_svr();
  33. if ((SVR_MAJ(svr) == 1) || IS_SVR_REV(svr, 2, 0)) {
  34. if ((regs->ddr_sdram_cfg & SDRAM_CFG_SDRAM_TYPE_MASK) ==
  35. SDRAM_CFG_SDRAM_TYPE_DDR2)
  36. out_be32(&gur->ddrioovcr, 0x90000000);
  37. else
  38. out_be32(&gur->ddrioovcr, 0xA8000000);
  39. }
  40. #endif
  41. for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) {
  42. if (i == 0) {
  43. out_be32(&ddr->cs0_bnds, regs->cs[i].bnds);
  44. out_be32(&ddr->cs0_config, regs->cs[i].config);
  45. } else if (i == 1) {
  46. out_be32(&ddr->cs1_bnds, regs->cs[i].bnds);
  47. out_be32(&ddr->cs1_config, regs->cs[i].config);
  48. } else if (i == 2) {
  49. out_be32(&ddr->cs2_bnds, regs->cs[i].bnds);
  50. out_be32(&ddr->cs2_config, regs->cs[i].config);
  51. } else if (i == 3) {
  52. out_be32(&ddr->cs3_bnds, regs->cs[i].bnds);
  53. out_be32(&ddr->cs3_config, regs->cs[i].config);
  54. }
  55. }
  56. out_be32(&ddr->timing_cfg_3, regs->timing_cfg_3);
  57. out_be32(&ddr->timing_cfg_0, regs->timing_cfg_0);
  58. out_be32(&ddr->timing_cfg_1, regs->timing_cfg_1);
  59. out_be32(&ddr->timing_cfg_2, regs->timing_cfg_2);
  60. out_be32(&ddr->sdram_cfg_2, regs->ddr_sdram_cfg_2);
  61. out_be32(&ddr->sdram_mode, regs->ddr_sdram_mode);
  62. out_be32(&ddr->sdram_mode_2, regs->ddr_sdram_mode_2);
  63. out_be32(&ddr->sdram_md_cntl, regs->ddr_sdram_md_cntl);
  64. out_be32(&ddr->sdram_interval, regs->ddr_sdram_interval);
  65. out_be32(&ddr->sdram_data_init, regs->ddr_data_init);
  66. out_be32(&ddr->sdram_clk_cntl, regs->ddr_sdram_clk_cntl);
  67. out_be32(&ddr->init_addr, regs->ddr_init_addr);
  68. out_be32(&ddr->init_ext_addr, regs->ddr_init_ext_addr);
  69. /*
  70. * 200 painful micro-seconds must elapse between
  71. * the DDR clock setup and the DDR config enable.
  72. */
  73. udelay(200);
  74. asm volatile("sync;isync");
  75. out_be32(&ddr->sdram_cfg, regs->ddr_sdram_cfg);
  76. /* Poll DDR_SDRAM_CFG_2[D_INIT] bit until auto-data init is done. */
  77. while (in_be32(&ddr->sdram_cfg_2) & 0x10) {
  78. udelay(10000); /* throttle polling rate */
  79. }
  80. }