fsl_ddr_gen4.c 19 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright 2014-2020 Freescale Semiconductor, Inc.
  4. */
  5. #include <common.h>
  6. #include <env.h>
  7. #include <log.h>
  8. #include <asm/io.h>
  9. #include <fsl_ddr_sdram.h>
  10. #include <asm/processor.h>
  11. #include <fsl_immap.h>
  12. #include <fsl_ddr.h>
  13. #include <fsl_errata.h>
  14. #if defined(CONFIG_FSL_LSCH2) || defined(CONFIG_FSL_LSCH3) || \
  15. defined(CONFIG_ARM)
  16. #include <asm/arch/clock.h>
  17. #endif
  18. #include <linux/delay.h>
  19. #define CTLR_INTLV_MASK 0x20000000
  20. #if defined(CONFIG_SYS_FSL_ERRATUM_A008511) | \
  21. defined(CONFIG_SYS_FSL_ERRATUM_A009803)
  22. static void set_wait_for_bits_clear(void *ptr, u32 value, u32 bits)
  23. {
  24. int timeout = 1000;
  25. ddr_out32(ptr, value);
  26. while (ddr_in32(ptr) & bits) {
  27. udelay(100);
  28. timeout--;
  29. }
  30. if (timeout <= 0)
  31. puts("Error: wait for clear timeout.\n");
  32. }
  33. #endif
  34. #if (CONFIG_CHIP_SELECTS_PER_CTRL > 4)
  35. #error Invalid setting for CONFIG_CHIP_SELECTS_PER_CTRL
  36. #endif
  37. /*
  38. * regs has the to-be-set values for DDR controller registers
  39. * ctrl_num is the DDR controller number
  40. * step: 0 goes through the initialization in one pass
  41. * 1 sets registers and returns before enabling controller
  42. * 2 resumes from step 1 and continues to initialize
  43. * Dividing the initialization to two steps to deassert DDR reset signal
  44. * to comply with JEDEC specs for RDIMMs.
  45. */
  46. void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs,
  47. unsigned int ctrl_num, int step)
  48. {
  49. unsigned int i, bus_width;
  50. struct ccsr_ddr __iomem *ddr;
  51. u32 temp32;
  52. u32 total_gb_size_per_controller;
  53. int timeout;
  54. int mod_bnds = 0;
  55. #ifdef CONFIG_SYS_FSL_ERRATUM_A008511
  56. u32 mr6;
  57. u32 vref_seq1[3] = {0x80, 0x96, 0x16}; /* for range 1 */
  58. u32 vref_seq2[3] = {0xc0, 0xf0, 0x70}; /* for range 2 */
  59. u32 *vref_seq = vref_seq1;
  60. #endif
  61. #ifdef CONFIG_FSL_DDR_BIST
  62. u32 mtcr, err_detect, err_sbe;
  63. u32 cs0_bnds, cs1_bnds, cs2_bnds, cs3_bnds, cs0_config;
  64. #endif
  65. #ifdef CONFIG_FSL_DDR_BIST
  66. char buffer[CONFIG_SYS_CBSIZE];
  67. #endif
  68. #if defined(CONFIG_SYS_FSL_ERRATUM_A009942) || \
  69. (defined(CONFIG_SYS_FSL_ERRATUM_A008378) && \
  70. defined(CONFIG_SYS_FSL_DDRC_GEN4)) || \
  71. defined(CONFIG_SYS_FSL_ERRATUM_A008109)
  72. u32 val32;
  73. #endif
  74. #ifdef CONFIG_SYS_FSL_ERRATUM_A009942
  75. unsigned int ddr_freq;
  76. #endif
  77. switch (ctrl_num) {
  78. case 0:
  79. ddr = (void *)CONFIG_SYS_FSL_DDR_ADDR;
  80. break;
  81. #if defined(CONFIG_SYS_FSL_DDR2_ADDR) && (CONFIG_SYS_NUM_DDR_CTLRS > 1)
  82. case 1:
  83. ddr = (void *)CONFIG_SYS_FSL_DDR2_ADDR;
  84. break;
  85. #endif
  86. #if defined(CONFIG_SYS_FSL_DDR3_ADDR) && (CONFIG_SYS_NUM_DDR_CTLRS > 2)
  87. case 2:
  88. ddr = (void *)CONFIG_SYS_FSL_DDR3_ADDR;
  89. break;
  90. #endif
  91. #if defined(CONFIG_SYS_FSL_DDR4_ADDR) && (CONFIG_SYS_NUM_DDR_CTLRS > 3)
  92. case 3:
  93. ddr = (void *)CONFIG_SYS_FSL_DDR4_ADDR;
  94. break;
  95. #endif
  96. default:
  97. printf("%s unexpected ctrl_num = %u\n", __func__, ctrl_num);
  98. return;
  99. }
  100. mod_bnds = regs->cs[0].config & CTLR_INTLV_MASK;
  101. if (step == 2)
  102. goto step2;
  103. /* Set cdr1 first in case 0.9v VDD is enabled for some SoCs*/
  104. ddr_out32(&ddr->ddr_cdr1, regs->ddr_cdr1);
  105. if (regs->ddr_eor)
  106. ddr_out32(&ddr->eor, regs->ddr_eor);
  107. ddr_out32(&ddr->sdram_clk_cntl, regs->ddr_sdram_clk_cntl);
  108. for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) {
  109. if (i == 0) {
  110. if (mod_bnds) {
  111. debug("modified bnds\n");
  112. ddr_out32(&ddr->cs0_bnds,
  113. (regs->cs[i].bnds & 0xfffefffe) >> 1);
  114. ddr_out32(&ddr->cs0_config,
  115. (regs->cs[i].config &
  116. ~CTLR_INTLV_MASK));
  117. } else {
  118. ddr_out32(&ddr->cs0_bnds, regs->cs[i].bnds);
  119. ddr_out32(&ddr->cs0_config, regs->cs[i].config);
  120. }
  121. ddr_out32(&ddr->cs0_config_2, regs->cs[i].config_2);
  122. } else if (i == 1) {
  123. if (mod_bnds) {
  124. ddr_out32(&ddr->cs1_bnds,
  125. (regs->cs[i].bnds & 0xfffefffe) >> 1);
  126. } else {
  127. ddr_out32(&ddr->cs1_bnds, regs->cs[i].bnds);
  128. }
  129. ddr_out32(&ddr->cs1_config, regs->cs[i].config);
  130. ddr_out32(&ddr->cs1_config_2, regs->cs[i].config_2);
  131. } else if (i == 2) {
  132. if (mod_bnds) {
  133. ddr_out32(&ddr->cs2_bnds,
  134. (regs->cs[i].bnds & 0xfffefffe) >> 1);
  135. } else {
  136. ddr_out32(&ddr->cs2_bnds, regs->cs[i].bnds);
  137. }
  138. ddr_out32(&ddr->cs2_config, regs->cs[i].config);
  139. ddr_out32(&ddr->cs2_config_2, regs->cs[i].config_2);
  140. } else if (i == 3) {
  141. if (mod_bnds) {
  142. ddr_out32(&ddr->cs3_bnds,
  143. (regs->cs[i].bnds & 0xfffefffe) >> 1);
  144. } else {
  145. ddr_out32(&ddr->cs3_bnds, regs->cs[i].bnds);
  146. }
  147. ddr_out32(&ddr->cs3_config, regs->cs[i].config);
  148. ddr_out32(&ddr->cs3_config_2, regs->cs[i].config_2);
  149. }
  150. }
  151. ddr_out32(&ddr->timing_cfg_3, regs->timing_cfg_3);
  152. ddr_out32(&ddr->timing_cfg_0, regs->timing_cfg_0);
  153. ddr_out32(&ddr->timing_cfg_1, regs->timing_cfg_1);
  154. ddr_out32(&ddr->timing_cfg_2, regs->timing_cfg_2);
  155. ddr_out32(&ddr->timing_cfg_4, regs->timing_cfg_4);
  156. ddr_out32(&ddr->timing_cfg_5, regs->timing_cfg_5);
  157. ddr_out32(&ddr->timing_cfg_6, regs->timing_cfg_6);
  158. ddr_out32(&ddr->timing_cfg_7, regs->timing_cfg_7);
  159. ddr_out32(&ddr->timing_cfg_8, regs->timing_cfg_8);
  160. ddr_out32(&ddr->timing_cfg_9, regs->timing_cfg_9);
  161. ddr_out32(&ddr->ddr_zq_cntl, regs->ddr_zq_cntl);
  162. ddr_out32(&ddr->dq_map_0, regs->dq_map_0);
  163. ddr_out32(&ddr->dq_map_1, regs->dq_map_1);
  164. ddr_out32(&ddr->dq_map_2, regs->dq_map_2);
  165. ddr_out32(&ddr->dq_map_3, regs->dq_map_3);
  166. ddr_out32(&ddr->sdram_cfg_3, regs->ddr_sdram_cfg_3);
  167. ddr_out32(&ddr->sdram_mode, regs->ddr_sdram_mode);
  168. ddr_out32(&ddr->sdram_mode_2, regs->ddr_sdram_mode_2);
  169. ddr_out32(&ddr->sdram_mode_3, regs->ddr_sdram_mode_3);
  170. ddr_out32(&ddr->sdram_mode_4, regs->ddr_sdram_mode_4);
  171. ddr_out32(&ddr->sdram_mode_5, regs->ddr_sdram_mode_5);
  172. ddr_out32(&ddr->sdram_mode_6, regs->ddr_sdram_mode_6);
  173. ddr_out32(&ddr->sdram_mode_7, regs->ddr_sdram_mode_7);
  174. ddr_out32(&ddr->sdram_mode_8, regs->ddr_sdram_mode_8);
  175. ddr_out32(&ddr->sdram_mode_9, regs->ddr_sdram_mode_9);
  176. ddr_out32(&ddr->sdram_mode_10, regs->ddr_sdram_mode_10);
  177. ddr_out32(&ddr->sdram_mode_11, regs->ddr_sdram_mode_11);
  178. ddr_out32(&ddr->sdram_mode_12, regs->ddr_sdram_mode_12);
  179. ddr_out32(&ddr->sdram_mode_13, regs->ddr_sdram_mode_13);
  180. ddr_out32(&ddr->sdram_mode_14, regs->ddr_sdram_mode_14);
  181. ddr_out32(&ddr->sdram_mode_15, regs->ddr_sdram_mode_15);
  182. ddr_out32(&ddr->sdram_mode_16, regs->ddr_sdram_mode_16);
  183. ddr_out32(&ddr->sdram_md_cntl, regs->ddr_sdram_md_cntl);
  184. #ifdef CONFIG_SYS_FSL_ERRATUM_A009663
  185. ddr_out32(&ddr->sdram_interval,
  186. regs->ddr_sdram_interval & ~SDRAM_INTERVAL_BSTOPRE);
  187. #else
  188. ddr_out32(&ddr->sdram_interval, regs->ddr_sdram_interval);
  189. #endif
  190. ddr_out32(&ddr->sdram_data_init, regs->ddr_data_init);
  191. ddr_out32(&ddr->ddr_wrlvl_cntl, regs->ddr_wrlvl_cntl);
  192. #ifndef CONFIG_SYS_FSL_DDR_EMU
  193. /*
  194. * Skip these two registers if running on emulator
  195. * because emulator doesn't have skew between bytes.
  196. */
  197. if (regs->ddr_wrlvl_cntl_2)
  198. ddr_out32(&ddr->ddr_wrlvl_cntl_2, regs->ddr_wrlvl_cntl_2);
  199. if (regs->ddr_wrlvl_cntl_3)
  200. ddr_out32(&ddr->ddr_wrlvl_cntl_3, regs->ddr_wrlvl_cntl_3);
  201. #endif
  202. ddr_out32(&ddr->ddr_sr_cntr, regs->ddr_sr_cntr);
  203. ddr_out32(&ddr->ddr_sdram_rcw_1, regs->ddr_sdram_rcw_1);
  204. ddr_out32(&ddr->ddr_sdram_rcw_2, regs->ddr_sdram_rcw_2);
  205. ddr_out32(&ddr->ddr_sdram_rcw_3, regs->ddr_sdram_rcw_3);
  206. ddr_out32(&ddr->ddr_sdram_rcw_4, regs->ddr_sdram_rcw_4);
  207. ddr_out32(&ddr->ddr_sdram_rcw_5, regs->ddr_sdram_rcw_5);
  208. ddr_out32(&ddr->ddr_sdram_rcw_6, regs->ddr_sdram_rcw_6);
  209. #ifdef CONFIG_DEEP_SLEEP
  210. if (is_warm_boot()) {
  211. ddr_out32(&ddr->sdram_cfg_2,
  212. regs->ddr_sdram_cfg_2 & ~SDRAM_CFG2_D_INIT);
  213. ddr_out32(&ddr->init_addr, CONFIG_SYS_SDRAM_BASE);
  214. ddr_out32(&ddr->init_ext_addr, DDR_INIT_ADDR_EXT_UIA);
  215. /* DRAM VRef will not be trained */
  216. ddr_out32(&ddr->ddr_cdr2,
  217. regs->ddr_cdr2 & ~DDR_CDR2_VREF_TRAIN_EN);
  218. } else
  219. #endif
  220. {
  221. ddr_out32(&ddr->sdram_cfg_2, regs->ddr_sdram_cfg_2);
  222. ddr_out32(&ddr->init_addr, regs->ddr_init_addr);
  223. ddr_out32(&ddr->init_ext_addr, regs->ddr_init_ext_addr);
  224. ddr_out32(&ddr->ddr_cdr2, regs->ddr_cdr2);
  225. }
  226. #ifdef CONFIG_SYS_FSL_ERRATUM_A009803
  227. /* part 1 of 2 */
  228. if (regs->ddr_sdram_cfg_2 & SDRAM_CFG2_AP_EN) {
  229. if (regs->ddr_sdram_cfg & SDRAM_CFG_RD_EN) { /* for RDIMM */
  230. ddr_out32(&ddr->ddr_sdram_rcw_2,
  231. regs->ddr_sdram_rcw_2 & ~0xf0);
  232. }
  233. ddr_out32(&ddr->err_disable, regs->err_disable |
  234. DDR_ERR_DISABLE_APED);
  235. }
  236. #else
  237. ddr_out32(&ddr->err_disable, regs->err_disable);
  238. #endif
  239. ddr_out32(&ddr->err_int_en, regs->err_int_en);
  240. for (i = 0; i < 64; i++) {
  241. if (regs->debug[i]) {
  242. debug("Write to debug_%d as %08x\n",
  243. i+1, regs->debug[i]);
  244. ddr_out32(&ddr->debug[i], regs->debug[i]);
  245. }
  246. }
  247. #ifdef CONFIG_SYS_FSL_ERRATUM_A008511
  248. /* Part 1 of 2 */
  249. if (fsl_ddr_get_version(ctrl_num) == 0x50200) {
  250. /* Disable DRAM VRef training */
  251. ddr_out32(&ddr->ddr_cdr2,
  252. regs->ddr_cdr2 & ~DDR_CDR2_VREF_TRAIN_EN);
  253. /* disable transmit bit deskew */
  254. temp32 = ddr_in32(&ddr->debug[28]);
  255. temp32 |= DDR_TX_BD_DIS;
  256. ddr_out32(&ddr->debug[28], temp32);
  257. ddr_out32(&ddr->debug[25], 0x9000);
  258. } else if (fsl_ddr_get_version(ctrl_num) == 0x50201) {
  259. /* Output enable forced off */
  260. ddr_out32(&ddr->debug[37], 1 << 31);
  261. /* Enable Vref training */
  262. ddr_out32(&ddr->ddr_cdr2,
  263. regs->ddr_cdr2 | DDR_CDR2_VREF_TRAIN_EN);
  264. } else {
  265. debug("Erratum A008511 doesn't apply.\n");
  266. }
  267. #endif
  268. #if defined(CONFIG_SYS_FSL_ERRATUM_A009803) || \
  269. defined(CONFIG_SYS_FSL_ERRATUM_A008511)
  270. /* Disable D_INIT */
  271. ddr_out32(&ddr->sdram_cfg_2,
  272. regs->ddr_sdram_cfg_2 & ~SDRAM_CFG2_D_INIT);
  273. #endif
  274. #ifdef CONFIG_SYS_FSL_ERRATUM_A009801
  275. temp32 = ddr_in32(&ddr->debug[25]);
  276. temp32 &= ~DDR_CAS_TO_PRE_SUB_MASK;
  277. temp32 |= 9 << DDR_CAS_TO_PRE_SUB_SHIFT;
  278. ddr_out32(&ddr->debug[25], temp32);
  279. #endif
  280. #ifdef CONFIG_SYS_FSL_ERRATUM_A010165
  281. temp32 = get_ddr_freq(ctrl_num) / 1000000;
  282. if ((temp32 > 1900) && (temp32 < 2300)) {
  283. temp32 = ddr_in32(&ddr->debug[28]);
  284. ddr_out32(&ddr->debug[28], temp32 | 0x000a0000);
  285. }
  286. #endif
  287. /*
  288. * For RDIMMs, JEDEC spec requires clocks to be stable before reset is
  289. * deasserted. Clocks start when any chip select is enabled and clock
  290. * control register is set. Because all DDR components are connected to
  291. * one reset signal, this needs to be done in two steps. Step 1 is to
  292. * get the clocks started. Step 2 resumes after reset signal is
  293. * deasserted.
  294. */
  295. if (step == 1) {
  296. udelay(200);
  297. return;
  298. }
  299. step2:
  300. /* Set, but do not enable the memory */
  301. temp32 = regs->ddr_sdram_cfg;
  302. temp32 &= ~(SDRAM_CFG_MEM_EN);
  303. ddr_out32(&ddr->sdram_cfg, temp32);
  304. /*
  305. * 500 painful micro-seconds must elapse between
  306. * the DDR clock setup and the DDR config enable.
  307. * DDR2 need 200 us, and DDR3 need 500 us from spec,
  308. * we choose the max, that is 500 us for all of case.
  309. */
  310. udelay(500);
  311. mb();
  312. isb();
  313. #ifdef CONFIG_DEEP_SLEEP
  314. if (is_warm_boot()) {
  315. /* enter self-refresh */
  316. temp32 = ddr_in32(&ddr->sdram_cfg_2);
  317. temp32 |= SDRAM_CFG2_FRC_SR;
  318. ddr_out32(&ddr->sdram_cfg_2, temp32);
  319. /* do board specific memory setup */
  320. board_mem_sleep_setup();
  321. temp32 = (ddr_in32(&ddr->sdram_cfg) | SDRAM_CFG_BI);
  322. } else
  323. #endif
  324. temp32 = ddr_in32(&ddr->sdram_cfg) & ~SDRAM_CFG_BI;
  325. /* Let the controller go */
  326. ddr_out32(&ddr->sdram_cfg, temp32 | SDRAM_CFG_MEM_EN);
  327. mb();
  328. isb();
  329. #if defined(CONFIG_SYS_FSL_ERRATUM_A008511) || \
  330. defined(CONFIG_SYS_FSL_ERRATUM_A009803)
  331. /* Part 2 of 2 */
  332. timeout = 40;
  333. /* Wait for idle. D_INIT needs to be cleared earlier, or timeout */
  334. while (!(ddr_in32(&ddr->debug[1]) & 0x2) &&
  335. (timeout > 0)) {
  336. udelay(1000);
  337. timeout--;
  338. }
  339. if (timeout <= 0) {
  340. printf("Controler %d timeout, debug_2 = %x\n",
  341. ctrl_num, ddr_in32(&ddr->debug[1]));
  342. }
  343. #ifdef CONFIG_SYS_FSL_ERRATUM_A008511
  344. /* This erraum only applies to verion 5.2.0 */
  345. if (fsl_ddr_get_version(ctrl_num) == 0x50200) {
  346. /* The vref setting sequence is different for range 2 */
  347. if (regs->ddr_cdr2 & DDR_CDR2_VREF_RANGE_2)
  348. vref_seq = vref_seq2;
  349. /* Set VREF */
  350. for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) {
  351. if (!(regs->cs[i].config & SDRAM_CS_CONFIG_EN))
  352. continue;
  353. mr6 = (regs->ddr_sdram_mode_10 >> 16) |
  354. MD_CNTL_MD_EN |
  355. MD_CNTL_CS_SEL(i) |
  356. MD_CNTL_MD_SEL(6) |
  357. 0x00200000;
  358. temp32 = mr6 | vref_seq[0];
  359. set_wait_for_bits_clear(&ddr->sdram_md_cntl,
  360. temp32, MD_CNTL_MD_EN);
  361. udelay(1);
  362. debug("MR6 = 0x%08x\n", temp32);
  363. temp32 = mr6 | vref_seq[1];
  364. set_wait_for_bits_clear(&ddr->sdram_md_cntl,
  365. temp32, MD_CNTL_MD_EN);
  366. udelay(1);
  367. debug("MR6 = 0x%08x\n", temp32);
  368. temp32 = mr6 | vref_seq[2];
  369. set_wait_for_bits_clear(&ddr->sdram_md_cntl,
  370. temp32, MD_CNTL_MD_EN);
  371. udelay(1);
  372. debug("MR6 = 0x%08x\n", temp32);
  373. }
  374. ddr_out32(&ddr->sdram_md_cntl, 0);
  375. temp32 = ddr_in32(&ddr->debug[28]);
  376. temp32 &= ~DDR_TX_BD_DIS; /* Enable deskew */
  377. ddr_out32(&ddr->debug[28], temp32);
  378. ddr_out32(&ddr->debug[1], 0x400); /* restart deskew */
  379. /* wait for idle */
  380. timeout = 40;
  381. while (!(ddr_in32(&ddr->debug[1]) & 0x2) &&
  382. (timeout > 0)) {
  383. udelay(1000);
  384. timeout--;
  385. }
  386. if (timeout <= 0) {
  387. printf("Controler %d timeout, debug_2 = %x\n",
  388. ctrl_num, ddr_in32(&ddr->debug[1]));
  389. }
  390. }
  391. #endif /* CONFIG_SYS_FSL_ERRATUM_A008511 */
  392. #ifdef CONFIG_SYS_FSL_ERRATUM_A009803
  393. if (regs->ddr_sdram_cfg_2 & SDRAM_CFG2_AP_EN) {
  394. /* if it's RDIMM */
  395. if (regs->ddr_sdram_cfg & SDRAM_CFG_RD_EN) {
  396. for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) {
  397. if (!(regs->cs[i].config & SDRAM_CS_CONFIG_EN))
  398. continue;
  399. set_wait_for_bits_clear(&ddr->sdram_md_cntl,
  400. MD_CNTL_MD_EN |
  401. MD_CNTL_CS_SEL(i) |
  402. 0x070000ed,
  403. MD_CNTL_MD_EN);
  404. udelay(1);
  405. }
  406. }
  407. ddr_out32(&ddr->err_disable,
  408. regs->err_disable & ~DDR_ERR_DISABLE_APED);
  409. }
  410. #endif
  411. /* Restore D_INIT */
  412. ddr_out32(&ddr->sdram_cfg_2, regs->ddr_sdram_cfg_2);
  413. #endif
  414. #if defined(CONFIG_SYS_FSL_ERRATUM_A008378) && defined(CONFIG_SYS_FSL_DDRC_GEN4)
  415. /* Erratum applies when accumulated ECC is used, or DBI is enabled */
  416. #define IS_ACC_ECC_EN(v) ((v) & 0x4)
  417. #define IS_DBI(v) ((((v) >> 12) & 0x3) == 0x2)
  418. if (has_erratum_a008378()) {
  419. if (IS_ACC_ECC_EN(regs->ddr_sdram_cfg) ||
  420. IS_DBI(regs->ddr_sdram_cfg_3)) {
  421. val32 = ddr_in32(&ddr->debug[28]);
  422. val32 |= (0x9 << 20);
  423. ddr_out32(&ddr->debug[28], val32);
  424. }
  425. debug("Applied errata CONFIG_SYS_FSL_ERRATUM_A008378\n");
  426. }
  427. #endif
  428. #if defined(CONFIG_SYS_FSL_ERRATUM_A008109)
  429. val32 = ddr_in32(&ddr->sdram_cfg_2) | 0x800; /* DDR_SLOW */
  430. ddr_out32(&ddr->sdram_cfg_2, val32);
  431. val32 = ddr_in32(&ddr->debug[18]) | 0x2;
  432. ddr_out32(&ddr->debug[18], val32);
  433. ddr_out32(&ddr->debug[28], 0x30000000);
  434. debug("Applied errta CONFIG_SYS_FSL_ERRATUM_A008109\n");
  435. #endif
  436. #ifdef CONFIG_SYS_FSL_ERRATUM_A009942
  437. ddr_freq = get_ddr_freq(ctrl_num) / 1000000;
  438. val32 = ddr_in32(&ddr->debug[28]);
  439. val32 &= 0xff0fff00;
  440. if (ddr_freq <= 1333)
  441. val32 |= 0x0080006a;
  442. else if (ddr_freq <= 1600)
  443. val32 |= 0x0070006f;
  444. else if (ddr_freq <= 1867)
  445. val32 |= 0x00700076;
  446. else if (ddr_freq <= 2133)
  447. val32 |= 0x0060007b;
  448. ddr_out32(&ddr->debug[28], val32);
  449. debug("Applied errata CONFIG_SYS_FSL_ERRATUM_A009942\n");
  450. #endif
  451. total_gb_size_per_controller = 0;
  452. for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) {
  453. if (!(regs->cs[i].config & 0x80000000))
  454. continue;
  455. total_gb_size_per_controller += 1 << (
  456. ((regs->cs[i].config >> 14) & 0x3) + 2 +
  457. ((regs->cs[i].config >> 8) & 0x7) + 12 +
  458. ((regs->cs[i].config >> 4) & 0x3) + 0 +
  459. ((regs->cs[i].config >> 0) & 0x7) + 8 +
  460. ((regs->ddr_sdram_cfg_3 >> 4) & 0x3) +
  461. 3 - ((regs->ddr_sdram_cfg >> 19) & 0x3) -
  462. 26); /* minus 26 (count of 64M) */
  463. }
  464. /*
  465. * total memory / bus width = transactions needed
  466. * transactions needed / data rate = seconds
  467. * to add plenty of buffer, double the time
  468. * For example, 2GB on 666MT/s 64-bit bus takes about 402ms
  469. * Let's wait for 800ms
  470. */
  471. bus_width = 3 - ((ddr_in32(&ddr->sdram_cfg) & SDRAM_CFG_DBW_MASK)
  472. >> SDRAM_CFG_DBW_SHIFT);
  473. timeout = ((total_gb_size_per_controller << (6 - bus_width)) * 100 /
  474. (get_ddr_freq(ctrl_num) >> 20)) << 2;
  475. total_gb_size_per_controller >>= 4; /* shift down to gb size */
  476. debug("total %d GB\n", total_gb_size_per_controller);
  477. debug("Need to wait up to %d * 10ms\n", timeout);
  478. /* Poll DDR_SDRAM_CFG_2[D_INIT] bit until auto-data init is done. */
  479. while ((ddr_in32(&ddr->sdram_cfg_2) & SDRAM_CFG2_D_INIT) &&
  480. (timeout >= 0)) {
  481. udelay(10000); /* throttle polling rate */
  482. timeout--;
  483. }
  484. if (timeout <= 0)
  485. printf("Waiting for D_INIT timeout. Memory may not work.\n");
  486. if (mod_bnds) {
  487. debug("Reset to original bnds\n");
  488. ddr_out32(&ddr->cs0_bnds, regs->cs[0].bnds);
  489. #if (CONFIG_CHIP_SELECTS_PER_CTRL > 1)
  490. ddr_out32(&ddr->cs1_bnds, regs->cs[1].bnds);
  491. #if (CONFIG_CHIP_SELECTS_PER_CTRL > 2)
  492. ddr_out32(&ddr->cs2_bnds, regs->cs[2].bnds);
  493. #if (CONFIG_CHIP_SELECTS_PER_CTRL > 3)
  494. ddr_out32(&ddr->cs3_bnds, regs->cs[3].bnds);
  495. #endif
  496. #endif
  497. #endif
  498. ddr_out32(&ddr->cs0_config, regs->cs[0].config);
  499. }
  500. #ifdef CONFIG_SYS_FSL_ERRATUM_A009663
  501. ddr_out32(&ddr->sdram_interval, regs->ddr_sdram_interval);
  502. #endif
  503. #ifdef CONFIG_DEEP_SLEEP
  504. if (is_warm_boot()) {
  505. /* exit self-refresh */
  506. temp32 = ddr_in32(&ddr->sdram_cfg_2);
  507. temp32 &= ~SDRAM_CFG2_FRC_SR;
  508. ddr_out32(&ddr->sdram_cfg_2, temp32);
  509. }
  510. #endif
  511. #ifdef CONFIG_FSL_DDR_BIST
  512. #define BIST_PATTERN1 0xFFFFFFFF
  513. #define BIST_PATTERN2 0x0
  514. #define BIST_CR 0x80010000
  515. #define BIST_CR_EN 0x80000000
  516. #define BIST_CR_STAT 0x00000001
  517. /* Perform build-in test on memory. Three-way interleaving is not yet
  518. * supported by this code. */
  519. if (env_get_f("ddr_bist", buffer, CONFIG_SYS_CBSIZE) >= 0) {
  520. puts("Running BIST test. This will take a while...");
  521. cs0_config = ddr_in32(&ddr->cs0_config);
  522. cs0_bnds = ddr_in32(&ddr->cs0_bnds);
  523. cs1_bnds = ddr_in32(&ddr->cs1_bnds);
  524. cs2_bnds = ddr_in32(&ddr->cs2_bnds);
  525. cs3_bnds = ddr_in32(&ddr->cs3_bnds);
  526. if (cs0_config & CTLR_INTLV_MASK) {
  527. /* set bnds to non-interleaving */
  528. ddr_out32(&ddr->cs0_bnds, (cs0_bnds & 0xfffefffe) >> 1);
  529. ddr_out32(&ddr->cs1_bnds, (cs1_bnds & 0xfffefffe) >> 1);
  530. ddr_out32(&ddr->cs2_bnds, (cs2_bnds & 0xfffefffe) >> 1);
  531. ddr_out32(&ddr->cs3_bnds, (cs3_bnds & 0xfffefffe) >> 1);
  532. }
  533. ddr_out32(&ddr->mtp1, BIST_PATTERN1);
  534. ddr_out32(&ddr->mtp2, BIST_PATTERN1);
  535. ddr_out32(&ddr->mtp3, BIST_PATTERN2);
  536. ddr_out32(&ddr->mtp4, BIST_PATTERN2);
  537. ddr_out32(&ddr->mtp5, BIST_PATTERN1);
  538. ddr_out32(&ddr->mtp6, BIST_PATTERN1);
  539. ddr_out32(&ddr->mtp7, BIST_PATTERN2);
  540. ddr_out32(&ddr->mtp8, BIST_PATTERN2);
  541. ddr_out32(&ddr->mtp9, BIST_PATTERN1);
  542. ddr_out32(&ddr->mtp10, BIST_PATTERN2);
  543. mtcr = BIST_CR;
  544. ddr_out32(&ddr->mtcr, mtcr);
  545. timeout = 100;
  546. while (timeout > 0 && (mtcr & BIST_CR_EN)) {
  547. mdelay(1000);
  548. timeout--;
  549. mtcr = ddr_in32(&ddr->mtcr);
  550. }
  551. if (timeout <= 0)
  552. puts("Timeout\n");
  553. else
  554. puts("Done\n");
  555. err_detect = ddr_in32(&ddr->err_detect);
  556. err_sbe = ddr_in32(&ddr->err_sbe);
  557. if (mtcr & BIST_CR_STAT) {
  558. printf("BIST test failed on controller %d.\n",
  559. ctrl_num);
  560. }
  561. if (err_detect || (err_sbe & 0xffff)) {
  562. printf("ECC error detected on controller %d.\n",
  563. ctrl_num);
  564. }
  565. if (cs0_config & CTLR_INTLV_MASK) {
  566. /* restore bnds registers */
  567. ddr_out32(&ddr->cs0_bnds, cs0_bnds);
  568. ddr_out32(&ddr->cs1_bnds, cs1_bnds);
  569. ddr_out32(&ddr->cs2_bnds, cs2_bnds);
  570. ddr_out32(&ddr->cs3_bnds, cs3_bnds);
  571. }
  572. }
  573. #endif
  574. }