ddr4_dimm_params.c 10.0 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright 2014-2016 Freescale Semiconductor, Inc.
  4. * Copyright 2017-2018 NXP Semiconductor
  5. *
  6. * calculate the organization and timing parameter
  7. * from ddr3 spd, please refer to the spec
  8. * JEDEC standard No.21-C 4_01_02_12R23A.pdf
  9. *
  10. *
  11. */
  12. #include <common.h>
  13. #include <fsl_ddr_sdram.h>
  14. #include <log.h>
  15. #include <linux/bug.h>
  16. #include <fsl_ddr.h>
  17. /*
  18. * Calculate the Density of each Physical Rank.
  19. * Returned size is in bytes.
  20. *
  21. * Total DIMM size =
  22. * sdram capacity(bit) / 8 * primary bus width / sdram width
  23. * * Logical Ranks per DIMM
  24. *
  25. * where: sdram capacity = spd byte4[3:0]
  26. * primary bus width = spd byte13[2:0]
  27. * sdram width = spd byte12[2:0]
  28. * Logical Ranks per DIMM = spd byte12[5:3] for SDP, DDP, QDP
  29. * spd byte12{5:3] * spd byte6[6:4] for 3DS
  30. *
  31. * To simplify each rank size = total DIMM size / Number of Package Ranks
  32. * where Number of Package Ranks = spd byte12[5:3]
  33. *
  34. * SPD byte4 - sdram density and banks
  35. * bit[3:0] size(bit) size(byte)
  36. * 0000 256Mb 32MB
  37. * 0001 512Mb 64MB
  38. * 0010 1Gb 128MB
  39. * 0011 2Gb 256MB
  40. * 0100 4Gb 512MB
  41. * 0101 8Gb 1GB
  42. * 0110 16Gb 2GB
  43. * 0111 32Gb 4GB
  44. *
  45. * SPD byte13 - module memory bus width
  46. * bit[2:0] primary bus width
  47. * 000 8bits
  48. * 001 16bits
  49. * 010 32bits
  50. * 011 64bits
  51. *
  52. * SPD byte12 - module organization
  53. * bit[2:0] sdram device width
  54. * 000 4bits
  55. * 001 8bits
  56. * 010 16bits
  57. * 011 32bits
  58. *
  59. * SPD byte12 - module organization
  60. * bit[5:3] number of package ranks per DIMM
  61. * 000 1
  62. * 001 2
  63. * 010 3
  64. * 011 4
  65. *
  66. * SPD byte6 - SDRAM package type
  67. * bit[6:4] Die count
  68. * 000 1
  69. * 001 2
  70. * 010 3
  71. * 011 4
  72. * 100 5
  73. * 101 6
  74. * 110 7
  75. * 111 8
  76. *
  77. * SPD byte6 - SRAM package type
  78. * bit[1:0] Signal loading
  79. * 00 Not specified
  80. * 01 Multi load stack
  81. * 10 Sigle load stack (3DS)
  82. * 11 Reserved
  83. */
  84. static unsigned long long
  85. compute_ranksize(const struct ddr4_spd_eeprom_s *spd)
  86. {
  87. unsigned long long bsize;
  88. int nbit_sdram_cap_bsize = 0;
  89. int nbit_primary_bus_width = 0;
  90. int nbit_sdram_width = 0;
  91. int die_count = 0;
  92. bool package_3ds;
  93. if ((spd->density_banks & 0xf) <= 7)
  94. nbit_sdram_cap_bsize = (spd->density_banks & 0xf) + 28;
  95. if ((spd->bus_width & 0x7) < 4)
  96. nbit_primary_bus_width = (spd->bus_width & 0x7) + 3;
  97. if ((spd->organization & 0x7) < 4)
  98. nbit_sdram_width = (spd->organization & 0x7) + 2;
  99. package_3ds = (spd->package_type & 0x3) == 0x2;
  100. if ((spd->package_type & 0x80) && !package_3ds) { /* other than 3DS */
  101. printf("Warning: not supported SDRAM package type\n");
  102. return 0;
  103. }
  104. if (package_3ds)
  105. die_count = (spd->package_type >> 4) & 0x7;
  106. bsize = 1ULL << (nbit_sdram_cap_bsize - 3 +
  107. nbit_primary_bus_width - nbit_sdram_width +
  108. die_count);
  109. debug("DDR: DDR rank density = 0x%16llx\n", bsize);
  110. return bsize;
  111. }
  112. #define spd_to_ps(mtb, ftb) \
  113. (mtb * pdimm->mtb_ps + (ftb * pdimm->ftb_10th_ps) / 10)
  114. /*
  115. * ddr_compute_dimm_parameters for DDR4 SPD
  116. *
  117. * Compute DIMM parameters based upon the SPD information in spd.
  118. * Writes the results to the dimm_params_t structure pointed by pdimm.
  119. *
  120. */
  121. unsigned int ddr_compute_dimm_parameters(const unsigned int ctrl_num,
  122. const generic_spd_eeprom_t *spd,
  123. dimm_params_t *pdimm,
  124. unsigned int dimm_number)
  125. {
  126. unsigned int retval;
  127. int i;
  128. const u8 udimm_rc_e_dq[18] = {
  129. 0x0c, 0x2c, 0x15, 0x35, 0x15, 0x35, 0x0b, 0x2c, 0x15,
  130. 0x35, 0x0b, 0x35, 0x0b, 0x2c, 0x0b, 0x35, 0x15, 0x36
  131. };
  132. int spd_error = 0;
  133. u8 *ptr;
  134. u8 val;
  135. if (spd->mem_type) {
  136. if (spd->mem_type != SPD_MEMTYPE_DDR4) {
  137. printf("Ctrl %u DIMM %u: is not a DDR4 SPD.\n",
  138. ctrl_num, dimm_number);
  139. return 1;
  140. }
  141. } else {
  142. memset(pdimm, 0, sizeof(dimm_params_t));
  143. return 1;
  144. }
  145. retval = ddr4_spd_check(spd);
  146. if (retval) {
  147. printf("DIMM %u: failed checksum\n", dimm_number);
  148. return 2;
  149. }
  150. /*
  151. * The part name in ASCII in the SPD EEPROM is not null terminated.
  152. * Guarantee null termination here by presetting all bytes to 0
  153. * and copying the part name in ASCII from the SPD onto it
  154. */
  155. memset(pdimm->mpart, 0, sizeof(pdimm->mpart));
  156. if ((spd->info_size_crc & 0xF) > 2)
  157. memcpy(pdimm->mpart, spd->mpart, sizeof(pdimm->mpart) - 1);
  158. /* DIMM organization parameters */
  159. pdimm->n_ranks = ((spd->organization >> 3) & 0x7) + 1;
  160. pdimm->rank_density = compute_ranksize(spd);
  161. pdimm->capacity = pdimm->n_ranks * pdimm->rank_density;
  162. pdimm->die_density = spd->density_banks & 0xf;
  163. pdimm->primary_sdram_width = 1 << (3 + (spd->bus_width & 0x7));
  164. if ((spd->bus_width >> 3) & 0x3)
  165. pdimm->ec_sdram_width = 8;
  166. else
  167. pdimm->ec_sdram_width = 0;
  168. pdimm->data_width = pdimm->primary_sdram_width
  169. + pdimm->ec_sdram_width;
  170. pdimm->device_width = 1 << ((spd->organization & 0x7) + 2);
  171. pdimm->package_3ds = (spd->package_type & 0x3) == 0x2 ?
  172. (spd->package_type >> 4) & 0x7 : 0;
  173. /* These are the types defined by the JEDEC SPD spec */
  174. pdimm->mirrored_dimm = 0;
  175. pdimm->registered_dimm = 0;
  176. switch (spd->module_type & DDR4_SPD_MODULETYPE_MASK) {
  177. case DDR4_SPD_MODULETYPE_RDIMM:
  178. /* Registered/buffered DIMMs */
  179. pdimm->registered_dimm = 1;
  180. if (spd->mod_section.registered.reg_map & 0x1)
  181. pdimm->mirrored_dimm = 1;
  182. val = spd->mod_section.registered.ca_stren;
  183. pdimm->rcw[3] = val >> 4;
  184. pdimm->rcw[4] = ((val & 0x3) << 2) | ((val & 0xc) >> 2);
  185. val = spd->mod_section.registered.clk_stren;
  186. pdimm->rcw[5] = ((val & 0x3) << 2) | ((val & 0xc) >> 2);
  187. /* Not all in SPD. For convience only. Boards may overwrite. */
  188. pdimm->rcw[6] = 0xf;
  189. /*
  190. * A17 only used for 16Gb and above devices.
  191. * C[2:0] only used for 3DS.
  192. */
  193. pdimm->rcw[8] = pdimm->die_density >= 0x6 ? 0x0 : 0x8 |
  194. (pdimm->package_3ds > 0x3 ? 0x0 :
  195. (pdimm->package_3ds > 0x1 ? 0x1 :
  196. (pdimm->package_3ds > 0 ? 0x2 : 0x3)));
  197. if (pdimm->package_3ds || pdimm->n_ranks != 4)
  198. pdimm->rcw[13] = 0xc;
  199. else
  200. pdimm->rcw[13] = 0xd; /* Fix encoded by board */
  201. break;
  202. case DDR4_SPD_MODULETYPE_UDIMM:
  203. case DDR4_SPD_MODULETYPE_SO_DIMM:
  204. /* Unbuffered DIMMs */
  205. if (spd->mod_section.unbuffered.addr_mapping & 0x1)
  206. pdimm->mirrored_dimm = 1;
  207. if ((spd->mod_section.unbuffered.mod_height & 0xe0) == 0 &&
  208. (spd->mod_section.unbuffered.ref_raw_card == 0x04)) {
  209. /* Fix SPD error found on DIMMs with raw card E0 */
  210. for (i = 0; i < 18; i++) {
  211. if (spd->mapping[i] == udimm_rc_e_dq[i])
  212. continue;
  213. spd_error = 1;
  214. debug("SPD byte %d: 0x%x, should be 0x%x\n",
  215. 60 + i, spd->mapping[i],
  216. udimm_rc_e_dq[i]);
  217. ptr = (u8 *)&spd->mapping[i];
  218. *ptr = udimm_rc_e_dq[i];
  219. }
  220. if (spd_error)
  221. puts("SPD DQ mapping error fixed\n");
  222. }
  223. break;
  224. default:
  225. printf("unknown module_type 0x%02X\n", spd->module_type);
  226. return 1;
  227. }
  228. /* SDRAM device parameters */
  229. pdimm->n_row_addr = ((spd->addressing >> 3) & 0x7) + 12;
  230. pdimm->n_col_addr = (spd->addressing & 0x7) + 9;
  231. pdimm->bank_addr_bits = (spd->density_banks >> 4) & 0x3;
  232. pdimm->bank_group_bits = (spd->density_banks >> 6) & 0x3;
  233. /*
  234. * The SPD spec has not the ECC bit,
  235. * We consider the DIMM as ECC capability
  236. * when the extension bus exist
  237. */
  238. if (pdimm->ec_sdram_width)
  239. pdimm->edc_config = 0x02;
  240. else
  241. pdimm->edc_config = 0x00;
  242. /*
  243. * The SPD spec has not the burst length byte
  244. * but DDR4 spec has nature BL8 and BC4,
  245. * BL8 -bit3, BC4 -bit2
  246. */
  247. pdimm->burst_lengths_bitmask = 0x0c;
  248. /* MTB - medium timebase
  249. * The MTB in the SPD spec is 125ps,
  250. *
  251. * FTB - fine timebase
  252. * use 1/10th of ps as our unit to avoid floating point
  253. * eg, 10 for 1ps, 25 for 2.5ps, 50 for 5ps
  254. */
  255. if ((spd->timebases & 0xf) == 0x0) {
  256. pdimm->mtb_ps = 125;
  257. pdimm->ftb_10th_ps = 10;
  258. } else {
  259. printf("Unknown Timebases\n");
  260. }
  261. /* sdram minimum cycle time */
  262. pdimm->tckmin_x_ps = spd_to_ps(spd->tck_min, spd->fine_tck_min);
  263. /* sdram max cycle time */
  264. pdimm->tckmax_ps = spd_to_ps(spd->tck_max, spd->fine_tck_max);
  265. /*
  266. * CAS latency supported
  267. * bit0 - CL7
  268. * bit4 - CL11
  269. * bit8 - CL15
  270. * bit12- CL19
  271. * bit16- CL23
  272. */
  273. pdimm->caslat_x = (spd->caslat_b1 << 7) |
  274. (spd->caslat_b2 << 15) |
  275. (spd->caslat_b3 << 23);
  276. BUG_ON(spd->caslat_b4 != 0);
  277. /*
  278. * min CAS latency time
  279. */
  280. pdimm->taa_ps = spd_to_ps(spd->taa_min, spd->fine_taa_min);
  281. /*
  282. * min RAS to CAS delay time
  283. */
  284. pdimm->trcd_ps = spd_to_ps(spd->trcd_min, spd->fine_trcd_min);
  285. /*
  286. * Min Row Precharge Delay Time
  287. */
  288. pdimm->trp_ps = spd_to_ps(spd->trp_min, spd->fine_trp_min);
  289. /* min active to precharge delay time */
  290. pdimm->tras_ps = (((spd->tras_trc_ext & 0xf) << 8) +
  291. spd->tras_min_lsb) * pdimm->mtb_ps;
  292. /* min active to actice/refresh delay time */
  293. pdimm->trc_ps = spd_to_ps((((spd->tras_trc_ext & 0xf0) << 4) +
  294. spd->trc_min_lsb), spd->fine_trc_min);
  295. /* Min Refresh Recovery Delay Time */
  296. pdimm->trfc1_ps = ((spd->trfc1_min_msb << 8) | (spd->trfc1_min_lsb)) *
  297. pdimm->mtb_ps;
  298. pdimm->trfc2_ps = ((spd->trfc2_min_msb << 8) | (spd->trfc2_min_lsb)) *
  299. pdimm->mtb_ps;
  300. pdimm->trfc4_ps = ((spd->trfc4_min_msb << 8) | (spd->trfc4_min_lsb)) *
  301. pdimm->mtb_ps;
  302. /* min four active window delay time */
  303. pdimm->tfaw_ps = (((spd->tfaw_msb & 0xf) << 8) | spd->tfaw_min) *
  304. pdimm->mtb_ps;
  305. /* min row active to row active delay time, different bank group */
  306. pdimm->trrds_ps = spd_to_ps(spd->trrds_min, spd->fine_trrds_min);
  307. /* min row active to row active delay time, same bank group */
  308. pdimm->trrdl_ps = spd_to_ps(spd->trrdl_min, spd->fine_trrdl_min);
  309. /* min CAS to CAS Delay Time (tCCD_Lmin), same bank group */
  310. pdimm->tccdl_ps = spd_to_ps(spd->tccdl_min, spd->fine_tccdl_min);
  311. if (pdimm->package_3ds) {
  312. if (pdimm->die_density <= 0x4) {
  313. pdimm->trfc_slr_ps = 260000;
  314. } else if (pdimm->die_density <= 0x5) {
  315. pdimm->trfc_slr_ps = 350000;
  316. } else {
  317. printf("WARN: Unsupported logical rank density 0x%x\n",
  318. pdimm->die_density);
  319. }
  320. }
  321. /*
  322. * Average periodic refresh interval
  323. * tREFI = 7.8 us at normal temperature range
  324. */
  325. pdimm->refresh_rate_ps = 7800000;
  326. for (i = 0; i < 18; i++)
  327. pdimm->dq_mapping[i] = spd->mapping[i];
  328. pdimm->dq_mapping_ors = ((spd->mapping[0] >> 6) & 0x3) == 0 ? 1 : 0;
  329. return 0;
  330. }