sequencer.h 7.4 KB

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  1. /* SPDX-License-Identifier: BSD-3-Clause */
  2. /*
  3. * Copyright Altera Corporation (C) 2012-2015
  4. */
  5. #ifndef _SEQUENCER_H_
  6. #define _SEQUENCER_H_
  7. #define RW_MGR_NUM_DM_PER_WRITE_GROUP (seq->rwcfg->mem_data_mask_width \
  8. / seq->rwcfg->mem_if_write_dqs_width)
  9. #define RW_MGR_NUM_TRUE_DM_PER_WRITE_GROUP ( \
  10. seq->rwcfg->true_mem_data_mask_width \
  11. / seq->rwcfg->mem_if_write_dqs_width)
  12. #define RW_MGR_NUM_DQS_PER_WRITE_GROUP (seq->rwcfg->mem_if_read_dqs_width \
  13. / seq->rwcfg->mem_if_write_dqs_width)
  14. #define NUM_RANKS_PER_SHADOW_REG (seq->rwcfg->mem_number_of_ranks \
  15. / NUM_SHADOW_REGS)
  16. #define RW_MGR_RUN_SINGLE_GROUP_OFFSET 0x0
  17. #define RW_MGR_RUN_ALL_GROUPS_OFFSET 0x0400
  18. #define RW_MGR_RESET_READ_DATAPATH_OFFSET 0x1000
  19. #define RW_MGR_SET_CS_AND_ODT_MASK_OFFSET 0x1400
  20. #define RW_MGR_INST_ROM_WRITE_OFFSET 0x1800
  21. #define RW_MGR_AC_ROM_WRITE_OFFSET 0x1C00
  22. #define NUM_SHADOW_REGS 1
  23. #define RW_MGR_RANK_NONE 0xFF
  24. #define RW_MGR_RANK_ALL 0x00
  25. #define RW_MGR_ODT_MODE_OFF 0
  26. #define RW_MGR_ODT_MODE_READ_WRITE 1
  27. #define NUM_CALIB_REPEAT 1
  28. #define NUM_READ_TESTS 7
  29. #define NUM_READ_PB_TESTS 7
  30. #define NUM_WRITE_TESTS 15
  31. #define NUM_WRITE_PB_TESTS 31
  32. #define PASS_ALL_BITS 1
  33. #define PASS_ONE_BIT 0
  34. /* calibration stages */
  35. #define CAL_STAGE_NIL 0
  36. #define CAL_STAGE_VFIFO 1
  37. #define CAL_STAGE_WLEVEL 2
  38. #define CAL_STAGE_LFIFO 3
  39. #define CAL_STAGE_WRITES 4
  40. #define CAL_STAGE_FULLTEST 5
  41. #define CAL_STAGE_REFRESH 6
  42. #define CAL_STAGE_CAL_SKIPPED 7
  43. #define CAL_STAGE_CAL_ABORTED 8
  44. #define CAL_STAGE_VFIFO_AFTER_WRITES 9
  45. /* calibration substages */
  46. #define CAL_SUBSTAGE_NIL 0
  47. #define CAL_SUBSTAGE_GUARANTEED_READ 1
  48. #define CAL_SUBSTAGE_DQS_EN_PHASE 2
  49. #define CAL_SUBSTAGE_VFIFO_CENTER 3
  50. #define CAL_SUBSTAGE_WORKING_DELAY 1
  51. #define CAL_SUBSTAGE_LAST_WORKING_DELAY 2
  52. #define CAL_SUBSTAGE_WLEVEL_COPY 3
  53. #define CAL_SUBSTAGE_WRITES_CENTER 1
  54. #define CAL_SUBSTAGE_READ_LATENCY 1
  55. #define CAL_SUBSTAGE_REFRESH 1
  56. #define SCC_MGR_GROUP_COUNTER_OFFSET 0x0000
  57. #define SCC_MGR_DQS_IN_DELAY_OFFSET 0x0100
  58. #define SCC_MGR_DQS_EN_PHASE_OFFSET 0x0200
  59. #define SCC_MGR_DQS_EN_DELAY_OFFSET 0x0300
  60. #define SCC_MGR_DQDQS_OUT_PHASE_OFFSET 0x0400
  61. #define SCC_MGR_OCT_OUT1_DELAY_OFFSET 0x0500
  62. #define SCC_MGR_IO_OUT1_DELAY_OFFSET 0x0700
  63. #define SCC_MGR_IO_IN_DELAY_OFFSET 0x0900
  64. /* HHP-HPS-specific versions of some commands */
  65. #define SCC_MGR_DQS_EN_DELAY_GATE_OFFSET 0x0600
  66. #define SCC_MGR_IO_OE_DELAY_OFFSET 0x0800
  67. #define SCC_MGR_HHP_GLOBALS_OFFSET 0x0A00
  68. #define SCC_MGR_HHP_RFILE_OFFSET 0x0B00
  69. #define SCC_MGR_AFI_CAL_INIT_OFFSET 0x0D00
  70. #define SDR_PHYGRP_SCCGRP_ADDRESS (SOCFPGA_SDR_ADDRESS | 0x0)
  71. #define SDR_PHYGRP_PHYMGRGRP_ADDRESS (SOCFPGA_SDR_ADDRESS | 0x1000)
  72. #define SDR_PHYGRP_RWMGRGRP_ADDRESS (SOCFPGA_SDR_ADDRESS | 0x2000)
  73. #define SDR_PHYGRP_DATAMGRGRP_ADDRESS (SOCFPGA_SDR_ADDRESS | 0x4000)
  74. #define SDR_PHYGRP_REGFILEGRP_ADDRESS (SOCFPGA_SDR_ADDRESS | 0x4800)
  75. #define PHY_MGR_CAL_RESET (0)
  76. #define PHY_MGR_CAL_SUCCESS (1)
  77. #define PHY_MGR_CAL_FAIL (2)
  78. #define CALIB_SKIP_DELAY_LOOPS (1 << 0)
  79. #define CALIB_SKIP_ALL_BITS_CHK (1 << 1)
  80. #define CALIB_SKIP_DELAY_SWEEPS (1 << 2)
  81. #define CALIB_SKIP_VFIFO (1 << 3)
  82. #define CALIB_SKIP_LFIFO (1 << 4)
  83. #define CALIB_SKIP_WLEVEL (1 << 5)
  84. #define CALIB_SKIP_WRITES (1 << 6)
  85. #define CALIB_SKIP_FULL_TEST (1 << 7)
  86. #define CALIB_SKIP_ALL (CALIB_SKIP_VFIFO | \
  87. CALIB_SKIP_LFIFO | CALIB_SKIP_WLEVEL | \
  88. CALIB_SKIP_WRITES | CALIB_SKIP_FULL_TEST)
  89. #define CALIB_IN_RTL_SIM (1 << 8)
  90. /* Scan chain manager command addresses */
  91. #define READ_SCC_OCT_OUT2_DELAY 0
  92. #define READ_SCC_DQ_OUT2_DELAY 0
  93. #define READ_SCC_DQS_IO_OUT2_DELAY 0
  94. #define READ_SCC_DM_IO_OUT2_DELAY 0
  95. /* HHP-HPS-specific values */
  96. #define SCC_MGR_HHP_EXTRAS_OFFSET 0
  97. #define SCC_MGR_HHP_DQSE_MAP_OFFSET 1
  98. /* PHY Debug mode flag constants */
  99. #define PHY_DEBUG_IN_DEBUG_MODE 0x00000001
  100. #define PHY_DEBUG_ENABLE_CAL_RPT 0x00000002
  101. #define PHY_DEBUG_ENABLE_MARGIN_RPT 0x00000004
  102. #define PHY_DEBUG_SWEEP_ALL_GROUPS 0x00000008
  103. #define PHY_DEBUG_DISABLE_GUARANTEED_READ 0x00000010
  104. #define PHY_DEBUG_ENABLE_NON_DESTRUCTIVE_CALIBRATION 0x00000020
  105. struct socfpga_sdr_rw_load_manager {
  106. u32 load_cntr0;
  107. u32 load_cntr1;
  108. u32 load_cntr2;
  109. u32 load_cntr3;
  110. };
  111. struct socfpga_sdr_rw_load_jump_manager {
  112. u32 load_jump_add0;
  113. u32 load_jump_add1;
  114. u32 load_jump_add2;
  115. u32 load_jump_add3;
  116. };
  117. struct socfpga_sdr_reg_file {
  118. u32 signature;
  119. u32 debug_data_addr;
  120. u32 cur_stage;
  121. u32 fom;
  122. u32 failing_stage;
  123. u32 debug1;
  124. u32 debug2;
  125. u32 dtaps_per_ptap;
  126. u32 trk_sample_count;
  127. u32 trk_longidle;
  128. u32 delays;
  129. u32 trk_rw_mgr_addr;
  130. u32 trk_read_dqs_width;
  131. u32 trk_rfsh;
  132. };
  133. /* parameter variable holder */
  134. struct param_type {
  135. u32 read_correct_mask;
  136. u32 read_correct_mask_vg;
  137. u32 write_correct_mask;
  138. u32 write_correct_mask_vg;
  139. };
  140. /* global variable holder */
  141. struct gbl_type {
  142. uint32_t phy_debug_mode_flags;
  143. /* current read latency */
  144. uint32_t curr_read_lat;
  145. /* error code */
  146. uint32_t error_substage;
  147. uint32_t error_stage;
  148. uint32_t error_group;
  149. /* figure-of-merit in, figure-of-merit out */
  150. uint32_t fom_in;
  151. uint32_t fom_out;
  152. /*USER Number of RW Mgr NOP cycles between
  153. write command and write data */
  154. uint32_t rw_wl_nop_cycles;
  155. };
  156. struct socfpga_sdr_scc_mgr {
  157. u32 dqs_ena;
  158. u32 dqs_io_ena;
  159. u32 dq_ena;
  160. u32 dm_ena;
  161. u32 __padding1[4];
  162. u32 update;
  163. u32 __padding2[7];
  164. u32 active_rank;
  165. };
  166. /* PHY manager configuration registers. */
  167. struct socfpga_phy_mgr_cfg {
  168. u32 phy_rlat;
  169. u32 reset_mem_stbl;
  170. u32 mux_sel;
  171. u32 cal_status;
  172. u32 cal_debug_info;
  173. u32 vfifo_rd_en_ovrd;
  174. u32 afi_wlat;
  175. u32 afi_rlat;
  176. };
  177. /* PHY manager command addresses. */
  178. struct socfpga_phy_mgr_cmd {
  179. u32 inc_vfifo_fr;
  180. u32 inc_vfifo_hard_phy;
  181. u32 fifo_reset;
  182. u32 inc_vfifo_fr_hr;
  183. u32 inc_vfifo_qr;
  184. };
  185. struct socfpga_data_mgr {
  186. u32 __padding1;
  187. u32 t_wl_add;
  188. u32 mem_t_add;
  189. u32 t_rl_add;
  190. };
  191. /* This struct describes the controller @ SOCFPGA_SDR_ADDRESS */
  192. struct socfpga_sdr {
  193. /* SDR_PHYGRP_SCCGRP_ADDRESS */
  194. u8 _align1[0xe00];
  195. /* SDR_PHYGRP_SCCGRP_ADDRESS | 0xe00 */
  196. struct socfpga_sdr_scc_mgr sdr_scc_mgr;
  197. u8 _align2[0x1bc];
  198. /* SDR_PHYGRP_PHYMGRGRP_ADDRESS */
  199. struct socfpga_phy_mgr_cmd phy_mgr_cmd;
  200. u8 _align3[0x2c];
  201. /* SDR_PHYGRP_PHYMGRGRP_ADDRESS | 0x40 */
  202. struct socfpga_phy_mgr_cfg phy_mgr_cfg;
  203. u8 _align4[0xfa0];
  204. /* SDR_PHYGRP_RWMGRGRP_ADDRESS */
  205. u8 rwmgr_grp[0x800];
  206. /* SDR_PHYGRP_RWMGRGRP_ADDRESS | 0x800 */
  207. struct socfpga_sdr_rw_load_manager sdr_rw_load_mgr_regs;
  208. u8 _align5[0x3f0];
  209. /* SDR_PHYGRP_RWMGRGRP_ADDRESS | 0xC00 */
  210. struct socfpga_sdr_rw_load_jump_manager sdr_rw_load_jump_mgr_regs;
  211. u8 _align6[0x13f0];
  212. /* SDR_PHYGRP_DATAMGRGRP_ADDRESS */
  213. struct socfpga_data_mgr data_mgr;
  214. u8 _align7[0x7f0];
  215. /* SDR_PHYGRP_REGFILEGRP_ADDRESS */
  216. struct socfpga_sdr_reg_file sdr_reg_file;
  217. u8 _align8[0x7c8];
  218. /* SDR_CTRLGRP_ADDRESS */
  219. struct socfpga_sdr_ctrl sdr_ctrl;
  220. u8 _align9[0xea4];
  221. };
  222. struct socfpga_sdrseq {
  223. const struct socfpga_sdram_rw_mgr_config *rwcfg;
  224. const struct socfpga_sdram_io_config *iocfg;
  225. const struct socfpga_sdram_misc_config *misccfg;
  226. /* calibration steps requested by the rtl */
  227. u16 dyn_calib_steps;
  228. /*
  229. * To make CALIB_SKIP_DELAY_LOOPS a dynamic conditional option
  230. * instead of static, we use boolean logic to select between
  231. * non-skip and skip values
  232. *
  233. * The mask is set to include all bits when not-skipping, but is
  234. * zero when skipping
  235. */
  236. u16 skip_delay_mask; /* mask off bits when skipping/not-skipping */
  237. struct gbl_type gbl;
  238. struct param_type param;
  239. };
  240. int sdram_calibration_full(struct socfpga_sdr *sdr);
  241. bool dram_is_ddr(const u8 ddr);
  242. #endif /* _SEQUENCER_H_ */