riscv_cpu.c 3.8 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169
  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright (C) 2018, Bin Meng <bmeng.cn@gmail.com>
  4. * Copyright (C) 2020, Sean Anderson <seanga2@gmail.com>
  5. */
  6. #include <clk.h>
  7. #include <common.h>
  8. #include <cpu.h>
  9. #include <dm.h>
  10. #include <errno.h>
  11. #include <log.h>
  12. #include <dm/device-internal.h>
  13. #include <dm/lists.h>
  14. #include <linux/bitops.h>
  15. #include <linux/err.h>
  16. DECLARE_GLOBAL_DATA_PTR;
  17. static int riscv_cpu_get_desc(const struct udevice *dev, char *buf, int size)
  18. {
  19. const char *isa;
  20. isa = dev_read_string(dev, "riscv,isa");
  21. if (size < (strlen(isa) + 1))
  22. return -ENOSPC;
  23. strcpy(buf, isa);
  24. return 0;
  25. }
  26. static int riscv_cpu_get_info(const struct udevice *dev, struct cpu_info *info)
  27. {
  28. int ret;
  29. struct clk clk;
  30. const char *mmu;
  31. u32 i_cache_size;
  32. u32 d_cache_size;
  33. /* First try getting the frequency from the assigned clock */
  34. ret = clk_get_by_index((struct udevice *)dev, 0, &clk);
  35. if (!ret) {
  36. ret = clk_get_rate(&clk);
  37. if (!IS_ERR_VALUE(ret))
  38. info->cpu_freq = ret;
  39. clk_free(&clk);
  40. }
  41. if (!info->cpu_freq)
  42. dev_read_u32(dev, "clock-frequency", (u32 *)&info->cpu_freq);
  43. mmu = dev_read_string(dev, "mmu-type");
  44. if (mmu)
  45. info->features |= BIT(CPU_FEAT_MMU);
  46. /* check if I cache is present */
  47. ret = dev_read_u32(dev, "i-cache-size", &i_cache_size);
  48. if (ret)
  49. /* if not found check if d-cache is present */
  50. ret = dev_read_u32(dev, "d-cache-size", &d_cache_size);
  51. /* if either I or D cache is present set L1 cache feature */
  52. if (!ret)
  53. info->features |= BIT(CPU_FEAT_L1_CACHE);
  54. return 0;
  55. }
  56. static int riscv_cpu_get_count(const struct udevice *dev)
  57. {
  58. ofnode node;
  59. int num = 0;
  60. ofnode_for_each_subnode(node, dev_ofnode(dev->parent)) {
  61. const char *device_type;
  62. /* skip if hart is marked as not available in the device tree */
  63. if (!ofnode_is_available(node))
  64. continue;
  65. device_type = ofnode_read_string(node, "device_type");
  66. if (!device_type)
  67. continue;
  68. if (strcmp(device_type, "cpu") == 0)
  69. num++;
  70. }
  71. return num;
  72. }
  73. static int riscv_cpu_bind(struct udevice *dev)
  74. {
  75. struct cpu_platdata *plat = dev_get_parent_platdata(dev);
  76. struct driver *drv;
  77. int ret;
  78. /* save the hart id */
  79. plat->cpu_id = dev_read_addr(dev);
  80. /* first examine the property in current cpu node */
  81. ret = dev_read_u32(dev, "timebase-frequency", &plat->timebase_freq);
  82. /* if not found, then look at the parent /cpus node */
  83. if (ret)
  84. dev_read_u32(dev->parent, "timebase-frequency",
  85. &plat->timebase_freq);
  86. /*
  87. * Bind riscv-timer driver on boot hart.
  88. *
  89. * We only instantiate one timer device which is enough for U-Boot.
  90. * Pass the "timebase-frequency" value as the driver data for the
  91. * timer device.
  92. *
  93. * Return value is not checked since it's possible that the timer
  94. * driver is not included.
  95. */
  96. if (plat->cpu_id == gd->arch.boot_hart && plat->timebase_freq) {
  97. drv = lists_driver_lookup_name("riscv_timer");
  98. if (!drv) {
  99. debug("Cannot find the timer driver, not included?\n");
  100. return 0;
  101. }
  102. device_bind_with_driver_data(dev, drv, "riscv_timer",
  103. plat->timebase_freq, ofnode_null(),
  104. NULL);
  105. }
  106. return 0;
  107. }
  108. static int riscv_cpu_probe(struct udevice *dev)
  109. {
  110. int ret = 0;
  111. struct clk clk;
  112. /* Get a clock if it exists */
  113. ret = clk_get_by_index(dev, 0, &clk);
  114. if (ret)
  115. return 0;
  116. ret = clk_enable(&clk);
  117. clk_free(&clk);
  118. if (ret == -ENOSYS || ret == -ENOTSUPP)
  119. return 0;
  120. else
  121. return ret;
  122. }
  123. static const struct cpu_ops riscv_cpu_ops = {
  124. .get_desc = riscv_cpu_get_desc,
  125. .get_info = riscv_cpu_get_info,
  126. .get_count = riscv_cpu_get_count,
  127. };
  128. static const struct udevice_id riscv_cpu_ids[] = {
  129. { .compatible = "riscv" },
  130. { }
  131. };
  132. U_BOOT_DRIVER(riscv_cpu) = {
  133. .name = "riscv_cpu",
  134. .id = UCLASS_CPU,
  135. .of_match = riscv_cpu_ids,
  136. .bind = riscv_cpu_bind,
  137. .probe = riscv_cpu_probe,
  138. .ops = &riscv_cpu_ops,
  139. .flags = DM_FLAG_PRE_RELOC,
  140. };