bmips_cpu.c 13 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright (C) 2017 Álvaro Fernández Rojas <noltari@gmail.com>
  4. *
  5. * Derived from linux/arch/mips/bcm63xx/cpu.c:
  6. * Copyright (C) 2008 Maxime Bizon <mbizon@freebox.fr>
  7. * Copyright (C) 2009 Florian Fainelli <florian@openwrt.org>
  8. */
  9. #include <common.h>
  10. #include <cpu.h>
  11. #include <dm.h>
  12. #include <errno.h>
  13. #include <init.h>
  14. #include <asm/io.h>
  15. #include <linux/bitops.h>
  16. #define REV_CHIPID_SHIFT 16
  17. #define REV_CHIPID_MASK (0xffff << REV_CHIPID_SHIFT)
  18. #define REV_LONG_CHIPID_SHIFT 12
  19. #define REV_LONG_CHIPID_MASK (0xfffff << REV_LONG_CHIPID_SHIFT)
  20. #define REV_REVID_SHIFT 0
  21. #define REV_REVID_MASK (0xff << REV_REVID_SHIFT)
  22. #define REG_BCM6328_OTP 0x62c
  23. #define BCM6328_TP1_DISABLED BIT(9)
  24. #define REG_BCM6318_STRAP_OVRDBUS 0x900
  25. #define OVRDBUS_6318_FREQ_SHIFT 23
  26. #define OVRDBUS_6318_FREQ_MASK (0x3 << OVRDBUS_6318_FREQ_SHIFT)
  27. #define REG_BCM6328_MISC_STRAPBUS 0x1a40
  28. #define STRAPBUS_6328_FCVO_SHIFT 7
  29. #define STRAPBUS_6328_FCVO_MASK (0x1f << STRAPBUS_6328_FCVO_SHIFT)
  30. #define REG_BCM6348_PERF_MIPSPLLCFG 0x34
  31. #define MIPSPLLCFG_6348_M1CPU_SHIFT 6
  32. #define MIPSPLLCFG_6348_M1CPU_MASK (0x7 << MIPSPLLCFG_6348_M1CPU_SHIFT)
  33. #define MIPSPLLCFG_6348_N2_SHIFT 15
  34. #define MIPSPLLCFG_6348_N2_MASK (0x1F << MIPSPLLCFG_6348_N2_SHIFT)
  35. #define MIPSPLLCFG_6348_N1_SHIFT 20
  36. #define MIPSPLLCFG_6348_N1_MASK (0x7 << MIPSPLLCFG_6348_N1_SHIFT)
  37. #define REG_BCM6358_DDR_DMIPSPLLCFG 0x12b8
  38. #define DMIPSPLLCFG_6358_M1_SHIFT 0
  39. #define DMIPSPLLCFG_6358_M1_MASK (0xff << DMIPSPLLCFG_6358_M1_SHIFT)
  40. #define DMIPSPLLCFG_6358_N1_SHIFT 23
  41. #define DMIPSPLLCFG_6358_N1_MASK (0x3f << DMIPSPLLCFG_6358_N1_SHIFT)
  42. #define DMIPSPLLCFG_6358_N2_SHIFT 29
  43. #define DMIPSPLLCFG_6358_N2_MASK (0x7 << DMIPSPLLCFG_6358_N2_SHIFT)
  44. #define REG_BCM6362_MISC_STRAPBUS 0x1814
  45. #define STRAPBUS_6362_FCVO_SHIFT 1
  46. #define STRAPBUS_6362_FCVO_MASK (0x1f << STRAPBUS_6362_FCVO_SHIFT)
  47. #define REG_BCM6368_DDR_DMIPSPLLCFG 0x12a0
  48. #define DMIPSPLLCFG_6368_P1_SHIFT 0
  49. #define DMIPSPLLCFG_6368_P1_MASK (0xf << DMIPSPLLCFG_6368_P1_SHIFT)
  50. #define DMIPSPLLCFG_6368_P2_SHIFT 4
  51. #define DMIPSPLLCFG_6368_P2_MASK (0xf << DMIPSPLLCFG_6368_P2_SHIFT)
  52. #define DMIPSPLLCFG_6368_NDIV_SHIFT 16
  53. #define DMIPSPLLCFG_6368_NDIV_MASK (0x1ff << DMIPSPLLCFG_6368_NDIV_SHIFT)
  54. #define REG_BCM6368_DDR_DMIPSPLLDIV 0x12a4
  55. #define DMIPSPLLDIV_6368_MDIV_SHIFT 0
  56. #define DMIPSPLLDIV_6368_MDIV_MASK (0xff << DMIPSPLLDIV_6368_MDIV_SHIFT)
  57. #define REG_BCM63268_MISC_STRAPBUS 0x1814
  58. #define STRAPBUS_63268_FCVO_SHIFT 21
  59. #define STRAPBUS_63268_FCVO_MASK (0xf << STRAPBUS_63268_FCVO_SHIFT)
  60. #define REG_BCM6838_OTP_BRCMBITS0 0x440
  61. #define VIPER_6838_FREQ_SHIFT 18
  62. #define VIPER_6838_FREQ_MASK (0x7 << VIPER_6838_FREQ_SHIFT)
  63. struct bmips_cpu_priv;
  64. struct bmips_cpu_hw {
  65. int (*get_cpu_desc)(struct bmips_cpu_priv *priv, char *buf, int size);
  66. ulong (*get_cpu_freq)(struct bmips_cpu_priv *);
  67. int (*get_cpu_count)(struct bmips_cpu_priv *);
  68. };
  69. struct bmips_cpu_priv {
  70. void __iomem *regs;
  71. const struct bmips_cpu_hw *hw;
  72. };
  73. /* Specific CPU Ops */
  74. static int bmips_short_cpu_desc(struct bmips_cpu_priv *priv, char *buf,
  75. int size)
  76. {
  77. unsigned short cpu_id;
  78. unsigned char cpu_rev;
  79. u32 val;
  80. val = readl_be(priv->regs);
  81. cpu_id = (val & REV_CHIPID_MASK) >> REV_CHIPID_SHIFT;
  82. cpu_rev = (val & REV_REVID_MASK) >> REV_REVID_SHIFT;
  83. snprintf(buf, size, "BCM%04X%02X", cpu_id, cpu_rev);
  84. return 0;
  85. }
  86. static int bmips_long_cpu_desc(struct bmips_cpu_priv *priv, char *buf,
  87. int size)
  88. {
  89. unsigned int cpu_id;
  90. unsigned char cpu_rev;
  91. u32 val;
  92. val = readl_be(priv->regs);
  93. cpu_id = (val & REV_LONG_CHIPID_MASK) >> REV_LONG_CHIPID_SHIFT;
  94. cpu_rev = (val & REV_REVID_MASK) >> REV_REVID_SHIFT;
  95. snprintf(buf, size, "BCM%05X%02X", cpu_id, cpu_rev);
  96. return 0;
  97. }
  98. static ulong bcm3380_get_cpu_freq(struct bmips_cpu_priv *priv)
  99. {
  100. return 333000000;
  101. }
  102. static ulong bcm6318_get_cpu_freq(struct bmips_cpu_priv *priv)
  103. {
  104. unsigned int mips_pll_fcvo;
  105. mips_pll_fcvo = readl_be(priv->regs + REG_BCM6318_STRAP_OVRDBUS);
  106. mips_pll_fcvo = (mips_pll_fcvo & OVRDBUS_6318_FREQ_MASK)
  107. >> OVRDBUS_6318_FREQ_SHIFT;
  108. switch (mips_pll_fcvo) {
  109. case 0:
  110. return 166000000;
  111. case 1:
  112. return 400000000;
  113. case 2:
  114. return 250000000;
  115. case 3:
  116. return 333000000;
  117. default:
  118. return 0;
  119. }
  120. }
  121. static ulong bcm6328_get_cpu_freq(struct bmips_cpu_priv *priv)
  122. {
  123. unsigned int mips_pll_fcvo;
  124. mips_pll_fcvo = readl_be(priv->regs + REG_BCM6328_MISC_STRAPBUS);
  125. mips_pll_fcvo = (mips_pll_fcvo & STRAPBUS_6328_FCVO_MASK)
  126. >> STRAPBUS_6328_FCVO_SHIFT;
  127. switch (mips_pll_fcvo) {
  128. case 0x12:
  129. case 0x14:
  130. case 0x19:
  131. return 160000000;
  132. case 0x1c:
  133. return 192000000;
  134. case 0x13:
  135. case 0x15:
  136. return 200000000;
  137. case 0x1a:
  138. return 384000000;
  139. case 0x16:
  140. return 400000000;
  141. default:
  142. return 320000000;
  143. }
  144. }
  145. static ulong bcm6338_get_cpu_freq(struct bmips_cpu_priv *priv)
  146. {
  147. return 240000000;
  148. }
  149. static ulong bcm6348_get_cpu_freq(struct bmips_cpu_priv *priv)
  150. {
  151. unsigned int tmp, n1, n2, m1;
  152. tmp = readl_be(priv->regs + REG_BCM6348_PERF_MIPSPLLCFG);
  153. n1 = (tmp & MIPSPLLCFG_6348_N1_MASK) >> MIPSPLLCFG_6348_N1_SHIFT;
  154. n2 = (tmp & MIPSPLLCFG_6348_N2_MASK) >> MIPSPLLCFG_6348_N2_SHIFT;
  155. m1 = (tmp & MIPSPLLCFG_6348_M1CPU_MASK) >> MIPSPLLCFG_6348_M1CPU_SHIFT;
  156. return (16 * 1000000 * (n1 + 1) * (n2 + 2)) / (m1 + 1);
  157. }
  158. static ulong bcm6358_get_cpu_freq(struct bmips_cpu_priv *priv)
  159. {
  160. unsigned int tmp, n1, n2, m1;
  161. tmp = readl_be(priv->regs + REG_BCM6358_DDR_DMIPSPLLCFG);
  162. n1 = (tmp & DMIPSPLLCFG_6358_N1_MASK) >> DMIPSPLLCFG_6358_N1_SHIFT;
  163. n2 = (tmp & DMIPSPLLCFG_6358_N2_MASK) >> DMIPSPLLCFG_6358_N2_SHIFT;
  164. m1 = (tmp & DMIPSPLLCFG_6358_M1_MASK) >> DMIPSPLLCFG_6358_M1_SHIFT;
  165. return (16 * 1000000 * n1 * n2) / m1;
  166. }
  167. static ulong bcm6362_get_cpu_freq(struct bmips_cpu_priv *priv)
  168. {
  169. unsigned int mips_pll_fcvo;
  170. mips_pll_fcvo = readl_be(priv->regs + REG_BCM6362_MISC_STRAPBUS);
  171. mips_pll_fcvo = (mips_pll_fcvo & STRAPBUS_6362_FCVO_MASK)
  172. >> STRAPBUS_6362_FCVO_SHIFT;
  173. switch (mips_pll_fcvo) {
  174. case 0x03:
  175. case 0x0b:
  176. case 0x13:
  177. case 0x1b:
  178. return 240000000;
  179. case 0x04:
  180. case 0x0c:
  181. case 0x14:
  182. case 0x1c:
  183. return 160000000;
  184. case 0x05:
  185. case 0x0e:
  186. case 0x16:
  187. case 0x1e:
  188. case 0x1f:
  189. return 400000000;
  190. case 0x06:
  191. return 440000000;
  192. case 0x07:
  193. case 0x17:
  194. return 384000000;
  195. case 0x15:
  196. case 0x1d:
  197. return 200000000;
  198. default:
  199. return 320000000;
  200. }
  201. }
  202. static ulong bcm6368_get_cpu_freq(struct bmips_cpu_priv *priv)
  203. {
  204. unsigned int tmp, p1, p2, ndiv, m1;
  205. tmp = readl_be(priv->regs + REG_BCM6368_DDR_DMIPSPLLCFG);
  206. p1 = (tmp & DMIPSPLLCFG_6368_P1_MASK) >> DMIPSPLLCFG_6368_P1_SHIFT;
  207. p2 = (tmp & DMIPSPLLCFG_6368_P2_MASK) >> DMIPSPLLCFG_6368_P2_SHIFT;
  208. ndiv = (tmp & DMIPSPLLCFG_6368_NDIV_MASK) >>
  209. DMIPSPLLCFG_6368_NDIV_SHIFT;
  210. tmp = readl_be(priv->regs + REG_BCM6368_DDR_DMIPSPLLDIV);
  211. m1 = (tmp & DMIPSPLLDIV_6368_MDIV_MASK) >> DMIPSPLLDIV_6368_MDIV_SHIFT;
  212. return (((64 * 1000000) / p1) * p2 * ndiv) / m1;
  213. }
  214. static ulong bcm63268_get_cpu_freq(struct bmips_cpu_priv *priv)
  215. {
  216. unsigned int mips_pll_fcvo;
  217. mips_pll_fcvo = readl_be(priv->regs + REG_BCM63268_MISC_STRAPBUS);
  218. mips_pll_fcvo = (mips_pll_fcvo & STRAPBUS_63268_FCVO_MASK)
  219. >> STRAPBUS_63268_FCVO_SHIFT;
  220. switch (mips_pll_fcvo) {
  221. case 0x3:
  222. case 0xe:
  223. return 320000000;
  224. case 0xa:
  225. return 333000000;
  226. case 0x2:
  227. case 0xb:
  228. case 0xf:
  229. return 400000000;
  230. default:
  231. return 0;
  232. }
  233. }
  234. static ulong bcm6838_get_cpu_freq(struct bmips_cpu_priv *priv)
  235. {
  236. unsigned int mips_viper_freq;
  237. mips_viper_freq = readl_be(priv->regs + REG_BCM6838_OTP_BRCMBITS0);
  238. mips_viper_freq = (mips_viper_freq & VIPER_6838_FREQ_MASK)
  239. >> VIPER_6838_FREQ_SHIFT;
  240. switch (mips_viper_freq) {
  241. case 0x0:
  242. return 600000000;
  243. case 0x1:
  244. return 400000000;
  245. case 0x2:
  246. return 240000000;
  247. default:
  248. return 0;
  249. }
  250. }
  251. static int bcm6328_get_cpu_count(struct bmips_cpu_priv *priv)
  252. {
  253. u32 val = readl_be(priv->regs + REG_BCM6328_OTP);
  254. if (val & BCM6328_TP1_DISABLED)
  255. return 1;
  256. else
  257. return 2;
  258. }
  259. static int bcm6345_get_cpu_count(struct bmips_cpu_priv *priv)
  260. {
  261. return 1;
  262. }
  263. static int bcm6358_get_cpu_count(struct bmips_cpu_priv *priv)
  264. {
  265. return 2;
  266. }
  267. static const struct bmips_cpu_hw bmips_cpu_bcm3380 = {
  268. .get_cpu_desc = bmips_short_cpu_desc,
  269. .get_cpu_freq = bcm3380_get_cpu_freq,
  270. .get_cpu_count = bcm6358_get_cpu_count,
  271. };
  272. static const struct bmips_cpu_hw bmips_cpu_bcm6318 = {
  273. .get_cpu_desc = bmips_short_cpu_desc,
  274. .get_cpu_freq = bcm6318_get_cpu_freq,
  275. .get_cpu_count = bcm6345_get_cpu_count,
  276. };
  277. static const struct bmips_cpu_hw bmips_cpu_bcm6328 = {
  278. .get_cpu_desc = bmips_long_cpu_desc,
  279. .get_cpu_freq = bcm6328_get_cpu_freq,
  280. .get_cpu_count = bcm6328_get_cpu_count,
  281. };
  282. static const struct bmips_cpu_hw bmips_cpu_bcm6338 = {
  283. .get_cpu_desc = bmips_short_cpu_desc,
  284. .get_cpu_freq = bcm6338_get_cpu_freq,
  285. .get_cpu_count = bcm6345_get_cpu_count,
  286. };
  287. static const struct bmips_cpu_hw bmips_cpu_bcm6348 = {
  288. .get_cpu_desc = bmips_short_cpu_desc,
  289. .get_cpu_freq = bcm6348_get_cpu_freq,
  290. .get_cpu_count = bcm6345_get_cpu_count,
  291. };
  292. static const struct bmips_cpu_hw bmips_cpu_bcm6358 = {
  293. .get_cpu_desc = bmips_short_cpu_desc,
  294. .get_cpu_freq = bcm6358_get_cpu_freq,
  295. .get_cpu_count = bcm6358_get_cpu_count,
  296. };
  297. static const struct bmips_cpu_hw bmips_cpu_bcm6362 = {
  298. .get_cpu_desc = bmips_short_cpu_desc,
  299. .get_cpu_freq = bcm6362_get_cpu_freq,
  300. .get_cpu_count = bcm6358_get_cpu_count,
  301. };
  302. static const struct bmips_cpu_hw bmips_cpu_bcm6368 = {
  303. .get_cpu_desc = bmips_short_cpu_desc,
  304. .get_cpu_freq = bcm6368_get_cpu_freq,
  305. .get_cpu_count = bcm6358_get_cpu_count,
  306. };
  307. static const struct bmips_cpu_hw bmips_cpu_bcm63268 = {
  308. .get_cpu_desc = bmips_long_cpu_desc,
  309. .get_cpu_freq = bcm63268_get_cpu_freq,
  310. .get_cpu_count = bcm6358_get_cpu_count,
  311. };
  312. static const struct bmips_cpu_hw bmips_cpu_bcm6838 = {
  313. .get_cpu_desc = bmips_short_cpu_desc,
  314. .get_cpu_freq = bcm6838_get_cpu_freq,
  315. .get_cpu_count = bcm6358_get_cpu_count,
  316. };
  317. /* Generic CPU Ops */
  318. static int bmips_cpu_get_desc(const struct udevice *dev, char *buf, int size)
  319. {
  320. struct bmips_cpu_priv *priv = dev_get_priv(dev);
  321. const struct bmips_cpu_hw *hw = priv->hw;
  322. return hw->get_cpu_desc(priv, buf, size);
  323. }
  324. static int bmips_cpu_get_info(const struct udevice *dev, struct cpu_info *info)
  325. {
  326. struct bmips_cpu_priv *priv = dev_get_priv(dev);
  327. const struct bmips_cpu_hw *hw = priv->hw;
  328. info->cpu_freq = hw->get_cpu_freq(priv);
  329. info->features = BIT(CPU_FEAT_L1_CACHE);
  330. info->features |= BIT(CPU_FEAT_MMU);
  331. info->features |= BIT(CPU_FEAT_DEVICE_ID);
  332. return 0;
  333. }
  334. static int bmips_cpu_get_count(const struct udevice *dev)
  335. {
  336. struct bmips_cpu_priv *priv = dev_get_priv(dev);
  337. const struct bmips_cpu_hw *hw = priv->hw;
  338. return hw->get_cpu_count(priv);
  339. }
  340. static int bmips_cpu_get_vendor(const struct udevice *dev, char *buf, int size)
  341. {
  342. snprintf(buf, size, "Broadcom");
  343. return 0;
  344. }
  345. static const struct cpu_ops bmips_cpu_ops = {
  346. .get_desc = bmips_cpu_get_desc,
  347. .get_info = bmips_cpu_get_info,
  348. .get_count = bmips_cpu_get_count,
  349. .get_vendor = bmips_cpu_get_vendor,
  350. };
  351. /* BMIPS CPU driver */
  352. int bmips_cpu_bind(struct udevice *dev)
  353. {
  354. struct cpu_platdata *plat = dev_get_parent_platdata(dev);
  355. plat->cpu_id = dev_read_u32_default(dev, "reg", -1);
  356. plat->device_id = read_c0_prid();
  357. return 0;
  358. }
  359. int bmips_cpu_probe(struct udevice *dev)
  360. {
  361. struct bmips_cpu_priv *priv = dev_get_priv(dev);
  362. const struct bmips_cpu_hw *hw =
  363. (const struct bmips_cpu_hw *)dev_get_driver_data(dev);
  364. priv->regs = dev_remap_addr(dev_get_parent(dev));
  365. if (!priv->regs)
  366. return -EINVAL;
  367. priv->hw = hw;
  368. return 0;
  369. }
  370. static const struct udevice_id bmips_cpu_ids[] = {
  371. {
  372. .compatible = "brcm,bcm3380-cpu",
  373. .data = (ulong)&bmips_cpu_bcm3380,
  374. }, {
  375. .compatible = "brcm,bcm6318-cpu",
  376. .data = (ulong)&bmips_cpu_bcm6318,
  377. }, {
  378. .compatible = "brcm,bcm6328-cpu",
  379. .data = (ulong)&bmips_cpu_bcm6328,
  380. }, {
  381. .compatible = "brcm,bcm6338-cpu",
  382. .data = (ulong)&bmips_cpu_bcm6338,
  383. }, {
  384. .compatible = "brcm,bcm6348-cpu",
  385. .data = (ulong)&bmips_cpu_bcm6348,
  386. }, {
  387. .compatible = "brcm,bcm6358-cpu",
  388. .data = (ulong)&bmips_cpu_bcm6358,
  389. }, {
  390. .compatible = "brcm,bcm6362-cpu",
  391. .data = (ulong)&bmips_cpu_bcm6362,
  392. }, {
  393. .compatible = "brcm,bcm6368-cpu",
  394. .data = (ulong)&bmips_cpu_bcm6368,
  395. }, {
  396. .compatible = "brcm,bcm63268-cpu",
  397. .data = (ulong)&bmips_cpu_bcm63268,
  398. }, {
  399. .compatible = "brcm,bcm6838-cpu",
  400. .data = (ulong)&bmips_cpu_bcm6838,
  401. },
  402. { /* sentinel */ }
  403. };
  404. U_BOOT_DRIVER(bmips_cpu_drv) = {
  405. .name = "bmips_cpu",
  406. .id = UCLASS_CPU,
  407. .of_match = bmips_cpu_ids,
  408. .bind = bmips_cpu_bind,
  409. .probe = bmips_cpu_probe,
  410. .priv_auto_alloc_size = sizeof(struct bmips_cpu_priv),
  411. .ops = &bmips_cpu_ops,
  412. .flags = DM_FLAG_PRE_RELOC,
  413. };
  414. #ifdef CONFIG_DISPLAY_CPUINFO
  415. int print_cpuinfo(void)
  416. {
  417. struct cpu_info cpu;
  418. struct udevice *dev;
  419. int err;
  420. char desc[100];
  421. err = uclass_get_device(UCLASS_CPU, 0, &dev);
  422. if (err)
  423. return 0;
  424. err = cpu_get_info(dev, &cpu);
  425. if (err)
  426. return 0;
  427. err = cpu_get_desc(dev, desc, sizeof(desc));
  428. if (err)
  429. return 0;
  430. printf("Chip ID: %s, MIPS: ", desc);
  431. print_freq(cpu.cpu_freq, "\n");
  432. return 0;
  433. }
  434. #endif