clk_h3.c 3.3 KB

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  1. // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
  2. /*
  3. * Copyright (C) 2018 Amarula Solutions.
  4. * Author: Jagan Teki <jagan@amarulasolutions.com>
  5. */
  6. #include <common.h>
  7. #include <clk-uclass.h>
  8. #include <dm.h>
  9. #include <errno.h>
  10. #include <asm/arch/ccu.h>
  11. #include <dt-bindings/clock/sun8i-h3-ccu.h>
  12. #include <dt-bindings/reset/sun8i-h3-ccu.h>
  13. #include <linux/bitops.h>
  14. static struct ccu_clk_gate h3_gates[] = {
  15. [CLK_BUS_MMC0] = GATE(0x060, BIT(8)),
  16. [CLK_BUS_MMC1] = GATE(0x060, BIT(9)),
  17. [CLK_BUS_MMC2] = GATE(0x060, BIT(10)),
  18. [CLK_BUS_EMAC] = GATE(0x060, BIT(17)),
  19. [CLK_BUS_SPI0] = GATE(0x060, BIT(20)),
  20. [CLK_BUS_SPI1] = GATE(0x060, BIT(21)),
  21. [CLK_BUS_OTG] = GATE(0x060, BIT(23)),
  22. [CLK_BUS_EHCI0] = GATE(0x060, BIT(24)),
  23. [CLK_BUS_EHCI1] = GATE(0x060, BIT(25)),
  24. [CLK_BUS_EHCI2] = GATE(0x060, BIT(26)),
  25. [CLK_BUS_EHCI3] = GATE(0x060, BIT(27)),
  26. [CLK_BUS_OHCI0] = GATE(0x060, BIT(28)),
  27. [CLK_BUS_OHCI1] = GATE(0x060, BIT(29)),
  28. [CLK_BUS_OHCI2] = GATE(0x060, BIT(30)),
  29. [CLK_BUS_OHCI3] = GATE(0x060, BIT(31)),
  30. [CLK_BUS_UART0] = GATE(0x06c, BIT(16)),
  31. [CLK_BUS_UART1] = GATE(0x06c, BIT(17)),
  32. [CLK_BUS_UART2] = GATE(0x06c, BIT(18)),
  33. [CLK_BUS_UART3] = GATE(0x06c, BIT(19)),
  34. [CLK_BUS_EPHY] = GATE(0x070, BIT(0)),
  35. [CLK_SPI0] = GATE(0x0a0, BIT(31)),
  36. [CLK_SPI1] = GATE(0x0a4, BIT(31)),
  37. [CLK_USB_PHY0] = GATE(0x0cc, BIT(8)),
  38. [CLK_USB_PHY1] = GATE(0x0cc, BIT(9)),
  39. [CLK_USB_PHY2] = GATE(0x0cc, BIT(10)),
  40. [CLK_USB_PHY3] = GATE(0x0cc, BIT(11)),
  41. [CLK_USB_OHCI0] = GATE(0x0cc, BIT(16)),
  42. [CLK_USB_OHCI1] = GATE(0x0cc, BIT(17)),
  43. [CLK_USB_OHCI2] = GATE(0x0cc, BIT(18)),
  44. [CLK_USB_OHCI3] = GATE(0x0cc, BIT(19)),
  45. };
  46. static struct ccu_reset h3_resets[] = {
  47. [RST_USB_PHY0] = RESET(0x0cc, BIT(0)),
  48. [RST_USB_PHY1] = RESET(0x0cc, BIT(1)),
  49. [RST_USB_PHY2] = RESET(0x0cc, BIT(2)),
  50. [RST_USB_PHY3] = RESET(0x0cc, BIT(3)),
  51. [RST_BUS_MMC0] = RESET(0x2c0, BIT(8)),
  52. [RST_BUS_MMC1] = RESET(0x2c0, BIT(9)),
  53. [RST_BUS_MMC2] = RESET(0x2c0, BIT(10)),
  54. [RST_BUS_EMAC] = RESET(0x2c0, BIT(17)),
  55. [RST_BUS_SPI0] = RESET(0x2c0, BIT(20)),
  56. [RST_BUS_SPI1] = RESET(0x2c0, BIT(21)),
  57. [RST_BUS_OTG] = RESET(0x2c0, BIT(23)),
  58. [RST_BUS_EHCI0] = RESET(0x2c0, BIT(24)),
  59. [RST_BUS_EHCI1] = RESET(0x2c0, BIT(25)),
  60. [RST_BUS_EHCI2] = RESET(0x2c0, BIT(26)),
  61. [RST_BUS_EHCI3] = RESET(0x2c0, BIT(27)),
  62. [RST_BUS_OHCI0] = RESET(0x2c0, BIT(28)),
  63. [RST_BUS_OHCI1] = RESET(0x2c0, BIT(29)),
  64. [RST_BUS_OHCI2] = RESET(0x2c0, BIT(30)),
  65. [RST_BUS_OHCI3] = RESET(0x2c0, BIT(31)),
  66. [RST_BUS_EPHY] = RESET(0x2c8, BIT(2)),
  67. [RST_BUS_UART0] = RESET(0x2d8, BIT(16)),
  68. [RST_BUS_UART1] = RESET(0x2d8, BIT(17)),
  69. [RST_BUS_UART2] = RESET(0x2d8, BIT(18)),
  70. [RST_BUS_UART3] = RESET(0x2d8, BIT(19)),
  71. };
  72. static const struct ccu_desc h3_ccu_desc = {
  73. .gates = h3_gates,
  74. .resets = h3_resets,
  75. };
  76. static int h3_clk_bind(struct udevice *dev)
  77. {
  78. return sunxi_reset_bind(dev, ARRAY_SIZE(h3_resets));
  79. }
  80. static const struct udevice_id h3_ccu_ids[] = {
  81. { .compatible = "allwinner,sun8i-h3-ccu",
  82. .data = (ulong)&h3_ccu_desc },
  83. { .compatible = "allwinner,sun50i-h5-ccu",
  84. .data = (ulong)&h3_ccu_desc },
  85. { }
  86. };
  87. U_BOOT_DRIVER(clk_sun8i_h3) = {
  88. .name = "sun8i_h3_ccu",
  89. .id = UCLASS_CLK,
  90. .of_match = h3_ccu_ids,
  91. .priv_auto_alloc_size = sizeof(struct ccu_priv),
  92. .ops = &sunxi_clk_ops,
  93. .probe = sunxi_clk_probe,
  94. .bind = h3_clk_bind,
  95. };