clk_a80.c 2.7 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright (C) 2018 Amarula Solutions.
  4. * Author: Jagan Teki <jagan@amarulasolutions.com>
  5. */
  6. #include <common.h>
  7. #include <clk-uclass.h>
  8. #include <dm.h>
  9. #include <errno.h>
  10. #include <asm/arch/ccu.h>
  11. #include <dt-bindings/clock/sun9i-a80-ccu.h>
  12. #include <dt-bindings/reset/sun9i-a80-ccu.h>
  13. #include <linux/bitops.h>
  14. static const struct ccu_clk_gate a80_gates[] = {
  15. [CLK_SPI0] = GATE(0x430, BIT(31)),
  16. [CLK_SPI1] = GATE(0x434, BIT(31)),
  17. [CLK_SPI2] = GATE(0x438, BIT(31)),
  18. [CLK_SPI3] = GATE(0x43c, BIT(31)),
  19. [CLK_BUS_MMC] = GATE(0x580, BIT(8)),
  20. [CLK_BUS_SPI0] = GATE(0x580, BIT(20)),
  21. [CLK_BUS_SPI1] = GATE(0x580, BIT(21)),
  22. [CLK_BUS_SPI2] = GATE(0x580, BIT(22)),
  23. [CLK_BUS_SPI3] = GATE(0x580, BIT(23)),
  24. [CLK_BUS_UART0] = GATE(0x594, BIT(16)),
  25. [CLK_BUS_UART1] = GATE(0x594, BIT(17)),
  26. [CLK_BUS_UART2] = GATE(0x594, BIT(18)),
  27. [CLK_BUS_UART3] = GATE(0x594, BIT(19)),
  28. [CLK_BUS_UART4] = GATE(0x594, BIT(20)),
  29. [CLK_BUS_UART5] = GATE(0x594, BIT(21)),
  30. };
  31. static const struct ccu_reset a80_resets[] = {
  32. [RST_BUS_MMC] = RESET(0x5a0, BIT(8)),
  33. [RST_BUS_SPI0] = RESET(0x5a0, BIT(20)),
  34. [RST_BUS_SPI1] = RESET(0x5a0, BIT(21)),
  35. [RST_BUS_SPI2] = RESET(0x5a0, BIT(22)),
  36. [RST_BUS_SPI3] = RESET(0x5a0, BIT(23)),
  37. [RST_BUS_UART0] = RESET(0x5b4, BIT(16)),
  38. [RST_BUS_UART1] = RESET(0x5b4, BIT(17)),
  39. [RST_BUS_UART2] = RESET(0x5b4, BIT(18)),
  40. [RST_BUS_UART3] = RESET(0x5b4, BIT(19)),
  41. [RST_BUS_UART4] = RESET(0x5b4, BIT(20)),
  42. [RST_BUS_UART5] = RESET(0x5b4, BIT(21)),
  43. };
  44. static const struct ccu_clk_gate a80_mmc_gates[] = {
  45. [0] = GATE(0x0, BIT(16)),
  46. [1] = GATE(0x4, BIT(16)),
  47. [2] = GATE(0x8, BIT(16)),
  48. [3] = GATE(0xc, BIT(16)),
  49. };
  50. static const struct ccu_reset a80_mmc_resets[] = {
  51. [0] = GATE(0x0, BIT(18)),
  52. [1] = GATE(0x4, BIT(18)),
  53. [2] = GATE(0x8, BIT(18)),
  54. [3] = GATE(0xc, BIT(18)),
  55. };
  56. static const struct ccu_desc a80_ccu_desc = {
  57. .gates = a80_gates,
  58. .resets = a80_resets,
  59. };
  60. static const struct ccu_desc a80_mmc_clk_desc = {
  61. .gates = a80_mmc_gates,
  62. .resets = a80_mmc_resets,
  63. };
  64. static int a80_clk_bind(struct udevice *dev)
  65. {
  66. ulong count = ARRAY_SIZE(a80_resets);
  67. if (device_is_compatible(dev, "allwinner,sun9i-a80-mmc-config-clk"))
  68. count = ARRAY_SIZE(a80_mmc_resets);
  69. return sunxi_reset_bind(dev, count);
  70. }
  71. static const struct udevice_id a80_ccu_ids[] = {
  72. { .compatible = "allwinner,sun9i-a80-ccu",
  73. .data = (ulong)&a80_ccu_desc },
  74. { .compatible = "allwinner,sun9i-a80-mmc-config-clk",
  75. .data = (ulong)&a80_mmc_clk_desc },
  76. { }
  77. };
  78. U_BOOT_DRIVER(clk_sun9i_a80) = {
  79. .name = "sun9i_a80_ccu",
  80. .id = UCLASS_CLK,
  81. .of_match = a80_ccu_ids,
  82. .priv_auto_alloc_size = sizeof(struct ccu_priv),
  83. .ops = &sunxi_clk_ops,
  84. .probe = sunxi_clk_probe,
  85. .bind = a80_clk_bind,
  86. };