clk_a23.c 2.6 KB

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  1. // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
  2. /*
  3. * Copyright (C) 2018 Amarula Solutions B.V.
  4. * Author: Jagan Teki <jagan@amarulasolutions.com>
  5. */
  6. #include <common.h>
  7. #include <clk-uclass.h>
  8. #include <dm.h>
  9. #include <errno.h>
  10. #include <asm/arch/ccu.h>
  11. #include <dt-bindings/clock/sun8i-a23-a33-ccu.h>
  12. #include <dt-bindings/reset/sun8i-a23-a33-ccu.h>
  13. #include <linux/bitops.h>
  14. static struct ccu_clk_gate a23_gates[] = {
  15. [CLK_BUS_MMC0] = GATE(0x060, BIT(8)),
  16. [CLK_BUS_MMC1] = GATE(0x060, BIT(9)),
  17. [CLK_BUS_MMC2] = GATE(0x060, BIT(10)),
  18. [CLK_BUS_SPI0] = GATE(0x060, BIT(20)),
  19. [CLK_BUS_SPI1] = GATE(0x060, BIT(21)),
  20. [CLK_BUS_OTG] = GATE(0x060, BIT(24)),
  21. [CLK_BUS_EHCI] = GATE(0x060, BIT(26)),
  22. [CLK_BUS_OHCI] = GATE(0x060, BIT(29)),
  23. [CLK_BUS_UART0] = GATE(0x06c, BIT(16)),
  24. [CLK_BUS_UART1] = GATE(0x06c, BIT(17)),
  25. [CLK_BUS_UART2] = GATE(0x06c, BIT(18)),
  26. [CLK_BUS_UART3] = GATE(0x06c, BIT(19)),
  27. [CLK_BUS_UART4] = GATE(0x06c, BIT(20)),
  28. [CLK_SPI0] = GATE(0x0a0, BIT(31)),
  29. [CLK_SPI1] = GATE(0x0a4, BIT(31)),
  30. [CLK_USB_PHY0] = GATE(0x0cc, BIT(8)),
  31. [CLK_USB_PHY1] = GATE(0x0cc, BIT(9)),
  32. [CLK_USB_HSIC] = GATE(0x0cc, BIT(10)),
  33. [CLK_USB_HSIC_12M] = GATE(0x0cc, BIT(11)),
  34. [CLK_USB_OHCI] = GATE(0x0cc, BIT(16)),
  35. };
  36. static struct ccu_reset a23_resets[] = {
  37. [RST_USB_PHY0] = RESET(0x0cc, BIT(0)),
  38. [RST_USB_PHY1] = RESET(0x0cc, BIT(1)),
  39. [RST_USB_HSIC] = RESET(0x0cc, BIT(2)),
  40. [RST_BUS_MMC0] = RESET(0x2c0, BIT(8)),
  41. [RST_BUS_MMC1] = RESET(0x2c0, BIT(9)),
  42. [RST_BUS_MMC2] = RESET(0x2c0, BIT(10)),
  43. [RST_BUS_SPI0] = RESET(0x2c0, BIT(20)),
  44. [RST_BUS_SPI1] = RESET(0x2c0, BIT(21)),
  45. [RST_BUS_OTG] = RESET(0x2c0, BIT(24)),
  46. [RST_BUS_EHCI] = RESET(0x2c0, BIT(26)),
  47. [RST_BUS_OHCI] = RESET(0x2c0, BIT(29)),
  48. [RST_BUS_UART0] = RESET(0x2d8, BIT(16)),
  49. [RST_BUS_UART1] = RESET(0x2d8, BIT(17)),
  50. [RST_BUS_UART2] = RESET(0x2d8, BIT(18)),
  51. [RST_BUS_UART3] = RESET(0x2d8, BIT(19)),
  52. [RST_BUS_UART4] = RESET(0x2d8, BIT(20)),
  53. };
  54. static const struct ccu_desc a23_ccu_desc = {
  55. .gates = a23_gates,
  56. .resets = a23_resets,
  57. };
  58. static int a23_clk_bind(struct udevice *dev)
  59. {
  60. return sunxi_reset_bind(dev, ARRAY_SIZE(a23_resets));
  61. }
  62. static const struct udevice_id a23_clk_ids[] = {
  63. { .compatible = "allwinner,sun8i-a23-ccu",
  64. .data = (ulong)&a23_ccu_desc },
  65. { .compatible = "allwinner,sun8i-a33-ccu",
  66. .data = (ulong)&a23_ccu_desc },
  67. { }
  68. };
  69. U_BOOT_DRIVER(clk_sun8i_a23) = {
  70. .name = "sun8i_a23_ccu",
  71. .id = UCLASS_CLK,
  72. .of_match = a23_clk_ids,
  73. .priv_auto_alloc_size = sizeof(struct ccu_priv),
  74. .ops = &sunxi_clk_ops,
  75. .probe = sunxi_clk_probe,
  76. .bind = a23_clk_bind,
  77. };