clk-mtk.c 13 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * MediaTek common clock driver
  4. *
  5. * Copyright (C) 2018 MediaTek Inc.
  6. * Author: Ryder Lee <ryder.lee@mediatek.com>
  7. */
  8. #include <common.h>
  9. #include <clk-uclass.h>
  10. #include <div64.h>
  11. #include <dm.h>
  12. #include <asm/io.h>
  13. #include <linux/bitops.h>
  14. #include <linux/delay.h>
  15. #include "clk-mtk.h"
  16. #define REG_CON0 0
  17. #define REG_CON1 4
  18. #define CON0_BASE_EN BIT(0)
  19. #define CON0_PWR_ON BIT(0)
  20. #define CON0_ISO_EN BIT(1)
  21. #define CON1_PCW_CHG BIT(31)
  22. #define POSTDIV_MASK 0x7
  23. #define INTEGER_BITS 7
  24. /* scpsys clock off control */
  25. #define CLK_SCP_CFG0 0x200
  26. #define CLK_SCP_CFG1 0x204
  27. #define SCP_ARMCK_OFF_EN GENMASK(9, 0)
  28. #define SCP_AXICK_DCM_DIS_EN BIT(0)
  29. #define SCP_AXICK_26M_SEL_EN BIT(4)
  30. /* shared functions */
  31. /*
  32. * In case the rate change propagation to parent clocks is undesirable,
  33. * this function is recursively called to find the parent to calculate
  34. * the accurate frequency.
  35. */
  36. static ulong mtk_clk_find_parent_rate(struct clk *clk, int id,
  37. const struct driver *drv)
  38. {
  39. struct clk parent = { .id = id, };
  40. if (drv) {
  41. struct udevice *dev;
  42. if (uclass_get_device_by_driver(UCLASS_CLK, drv, &dev))
  43. return -ENODEV;
  44. parent.dev = dev;
  45. } else {
  46. parent.dev = clk->dev;
  47. }
  48. return clk_get_rate(&parent);
  49. }
  50. static int mtk_clk_mux_set_parent(void __iomem *base, u32 parent,
  51. const struct mtk_composite *mux)
  52. {
  53. u32 val, index = 0;
  54. while (mux->parent[index] != parent)
  55. if (++index == mux->num_parents)
  56. return -EINVAL;
  57. if (mux->flags & CLK_MUX_SETCLR_UPD) {
  58. val = (mux->mux_mask << mux->mux_shift);
  59. writel(val, base + mux->mux_clr_reg);
  60. val = (index << mux->mux_shift);
  61. writel(val, base + mux->mux_set_reg);
  62. if (mux->upd_shift >= 0)
  63. writel(BIT(mux->upd_shift), base + mux->upd_reg);
  64. } else {
  65. /* switch mux to a select parent */
  66. val = readl(base + mux->mux_reg);
  67. val &= ~(mux->mux_mask << mux->mux_shift);
  68. val |= index << mux->mux_shift;
  69. writel(val, base + mux->mux_reg);
  70. }
  71. return 0;
  72. }
  73. /* apmixedsys functions */
  74. static unsigned long __mtk_pll_recalc_rate(const struct mtk_pll_data *pll,
  75. u32 fin, u32 pcw, int postdiv)
  76. {
  77. int pcwbits = pll->pcwbits;
  78. int pcwfbits;
  79. int ibits;
  80. u64 vco;
  81. u8 c = 0;
  82. /* The fractional part of the PLL divider. */
  83. ibits = pll->pcwibits ? pll->pcwibits : INTEGER_BITS;
  84. pcwfbits = pcwbits > ibits ? pcwbits - ibits : 0;
  85. vco = (u64)fin * pcw;
  86. if (pcwfbits && (vco & GENMASK(pcwfbits - 1, 0)))
  87. c = 1;
  88. vco >>= pcwfbits;
  89. if (c)
  90. vco++;
  91. return ((unsigned long)vco + postdiv - 1) / postdiv;
  92. }
  93. /**
  94. * MediaTek PLLs are configured through their pcw value. The pcw value
  95. * describes a divider in the PLL feedback loop which consists of 7 bits
  96. * for the integer part and the remaining bits (if present) for the
  97. * fractional part. Also they have a 3 bit power-of-two post divider.
  98. */
  99. static void mtk_pll_set_rate_regs(struct clk *clk, u32 pcw, int postdiv)
  100. {
  101. struct mtk_clk_priv *priv = dev_get_priv(clk->dev);
  102. const struct mtk_pll_data *pll = &priv->tree->plls[clk->id];
  103. u32 val, chg;
  104. /* set postdiv */
  105. val = readl(priv->base + pll->pd_reg);
  106. val &= ~(POSTDIV_MASK << pll->pd_shift);
  107. val |= (ffs(postdiv) - 1) << pll->pd_shift;
  108. /* postdiv and pcw need to set at the same time if on same register */
  109. if (pll->pd_reg != pll->pcw_reg) {
  110. writel(val, priv->base + pll->pd_reg);
  111. val = readl(priv->base + pll->pcw_reg);
  112. }
  113. /* set pcw */
  114. val &= ~GENMASK(pll->pcw_shift + pll->pcwbits - 1, pll->pcw_shift);
  115. val |= pcw << pll->pcw_shift;
  116. if (pll->pcw_chg_reg) {
  117. chg = readl(priv->base + pll->pcw_chg_reg);
  118. chg |= CON1_PCW_CHG;
  119. writel(val, priv->base + pll->pcw_reg);
  120. writel(chg, priv->base + pll->pcw_chg_reg);
  121. } else {
  122. val |= CON1_PCW_CHG;
  123. writel(val, priv->base + pll->pcw_reg);
  124. }
  125. udelay(20);
  126. }
  127. /**
  128. * mtk_pll_calc_values - calculate good values for a given input frequency.
  129. * @clk: The clk
  130. * @pcw: The pcw value (output)
  131. * @postdiv: The post divider (output)
  132. * @freq: The desired target frequency
  133. */
  134. static void mtk_pll_calc_values(struct clk *clk, u32 *pcw, u32 *postdiv,
  135. u32 freq)
  136. {
  137. struct mtk_clk_priv *priv = dev_get_priv(clk->dev);
  138. const struct mtk_pll_data *pll = &priv->tree->plls[clk->id];
  139. unsigned long fmin = pll->fmin ? pll->fmin : 1000 * MHZ;
  140. u64 _pcw;
  141. int ibits;
  142. u32 val;
  143. if (freq > pll->fmax)
  144. freq = pll->fmax;
  145. for (val = 0; val < 5; val++) {
  146. *postdiv = 1 << val;
  147. if ((u64)freq * *postdiv >= fmin)
  148. break;
  149. }
  150. /* _pcw = freq * postdiv / xtal_rate * 2^pcwfbits */
  151. ibits = pll->pcwibits ? pll->pcwibits : INTEGER_BITS;
  152. _pcw = ((u64)freq << val) << (pll->pcwbits - ibits);
  153. do_div(_pcw, priv->tree->xtal2_rate);
  154. *pcw = (u32)_pcw;
  155. }
  156. static ulong mtk_apmixedsys_set_rate(struct clk *clk, ulong rate)
  157. {
  158. u32 pcw = 0;
  159. u32 postdiv;
  160. mtk_pll_calc_values(clk, &pcw, &postdiv, rate);
  161. mtk_pll_set_rate_regs(clk, pcw, postdiv);
  162. return 0;
  163. }
  164. static ulong mtk_apmixedsys_get_rate(struct clk *clk)
  165. {
  166. struct mtk_clk_priv *priv = dev_get_priv(clk->dev);
  167. const struct mtk_pll_data *pll = &priv->tree->plls[clk->id];
  168. u32 postdiv;
  169. u32 pcw;
  170. postdiv = (readl(priv->base + pll->pd_reg) >> pll->pd_shift) &
  171. POSTDIV_MASK;
  172. postdiv = 1 << postdiv;
  173. pcw = readl(priv->base + pll->pcw_reg) >> pll->pcw_shift;
  174. pcw &= GENMASK(pll->pcwbits - 1, 0);
  175. return __mtk_pll_recalc_rate(pll, priv->tree->xtal2_rate,
  176. pcw, postdiv);
  177. }
  178. static int mtk_apmixedsys_enable(struct clk *clk)
  179. {
  180. struct mtk_clk_priv *priv = dev_get_priv(clk->dev);
  181. const struct mtk_pll_data *pll = &priv->tree->plls[clk->id];
  182. u32 r;
  183. r = readl(priv->base + pll->pwr_reg) | CON0_PWR_ON;
  184. writel(r, priv->base + pll->pwr_reg);
  185. udelay(1);
  186. r = readl(priv->base + pll->pwr_reg) & ~CON0_ISO_EN;
  187. writel(r, priv->base + pll->pwr_reg);
  188. udelay(1);
  189. r = readl(priv->base + pll->reg + REG_CON0);
  190. r |= pll->en_mask;
  191. writel(r, priv->base + pll->reg + REG_CON0);
  192. udelay(20);
  193. if (pll->flags & HAVE_RST_BAR) {
  194. r = readl(priv->base + pll->reg + REG_CON0);
  195. r |= pll->rst_bar_mask;
  196. writel(r, priv->base + pll->reg + REG_CON0);
  197. }
  198. return 0;
  199. }
  200. static int mtk_apmixedsys_disable(struct clk *clk)
  201. {
  202. struct mtk_clk_priv *priv = dev_get_priv(clk->dev);
  203. const struct mtk_pll_data *pll = &priv->tree->plls[clk->id];
  204. u32 r;
  205. if (pll->flags & HAVE_RST_BAR) {
  206. r = readl(priv->base + pll->reg + REG_CON0);
  207. r &= ~pll->rst_bar_mask;
  208. writel(r, priv->base + pll->reg + REG_CON0);
  209. }
  210. r = readl(priv->base + pll->reg + REG_CON0);
  211. r &= ~CON0_BASE_EN;
  212. writel(r, priv->base + pll->reg + REG_CON0);
  213. r = readl(priv->base + pll->pwr_reg) | CON0_ISO_EN;
  214. writel(r, priv->base + pll->pwr_reg);
  215. r = readl(priv->base + pll->pwr_reg) & ~CON0_PWR_ON;
  216. writel(r, priv->base + pll->pwr_reg);
  217. return 0;
  218. }
  219. /* topckgen functions */
  220. static ulong mtk_factor_recalc_rate(const struct mtk_fixed_factor *fdiv,
  221. ulong parent_rate)
  222. {
  223. u64 rate = parent_rate * fdiv->mult;
  224. do_div(rate, fdiv->div);
  225. return rate;
  226. }
  227. static ulong mtk_topckgen_get_factor_rate(struct clk *clk, u32 off)
  228. {
  229. struct mtk_clk_priv *priv = dev_get_priv(clk->dev);
  230. const struct mtk_fixed_factor *fdiv = &priv->tree->fdivs[off];
  231. ulong rate;
  232. switch (fdiv->flags & CLK_PARENT_MASK) {
  233. case CLK_PARENT_APMIXED:
  234. rate = mtk_clk_find_parent_rate(clk, fdiv->parent,
  235. DM_GET_DRIVER(mtk_clk_apmixedsys));
  236. break;
  237. case CLK_PARENT_TOPCKGEN:
  238. rate = mtk_clk_find_parent_rate(clk, fdiv->parent, NULL);
  239. break;
  240. default:
  241. rate = priv->tree->xtal_rate;
  242. }
  243. return mtk_factor_recalc_rate(fdiv, rate);
  244. }
  245. static ulong mtk_topckgen_get_mux_rate(struct clk *clk, u32 off)
  246. {
  247. struct mtk_clk_priv *priv = dev_get_priv(clk->dev);
  248. const struct mtk_composite *mux = &priv->tree->muxes[off];
  249. u32 index;
  250. index = readl(priv->base + mux->mux_reg);
  251. index &= mux->mux_mask << mux->mux_shift;
  252. index = index >> mux->mux_shift;
  253. if (mux->parent[index])
  254. return mtk_clk_find_parent_rate(clk, mux->parent[index],
  255. NULL);
  256. return priv->tree->xtal_rate;
  257. }
  258. static ulong mtk_topckgen_get_rate(struct clk *clk)
  259. {
  260. struct mtk_clk_priv *priv = dev_get_priv(clk->dev);
  261. if (clk->id < priv->tree->fdivs_offs)
  262. return priv->tree->fclks[clk->id].rate;
  263. else if (clk->id < priv->tree->muxes_offs)
  264. return mtk_topckgen_get_factor_rate(clk, clk->id -
  265. priv->tree->fdivs_offs);
  266. else
  267. return mtk_topckgen_get_mux_rate(clk, clk->id -
  268. priv->tree->muxes_offs);
  269. }
  270. static int mtk_topckgen_enable(struct clk *clk)
  271. {
  272. struct mtk_clk_priv *priv = dev_get_priv(clk->dev);
  273. const struct mtk_composite *mux;
  274. u32 val;
  275. if (clk->id < priv->tree->muxes_offs)
  276. return 0;
  277. mux = &priv->tree->muxes[clk->id - priv->tree->muxes_offs];
  278. if (mux->gate_shift < 0)
  279. return 0;
  280. /* enable clock gate */
  281. if (mux->flags & CLK_MUX_SETCLR_UPD) {
  282. val = BIT(mux->gate_shift);
  283. writel(val, priv->base + mux->mux_clr_reg);
  284. } else {
  285. val = readl(priv->base + mux->gate_reg);
  286. val &= ~BIT(mux->gate_shift);
  287. writel(val, priv->base + mux->gate_reg);
  288. }
  289. if (mux->flags & CLK_DOMAIN_SCPSYS) {
  290. /* enable scpsys clock off control */
  291. writel(SCP_ARMCK_OFF_EN, priv->base + CLK_SCP_CFG0);
  292. writel(SCP_AXICK_DCM_DIS_EN | SCP_AXICK_26M_SEL_EN,
  293. priv->base + CLK_SCP_CFG1);
  294. }
  295. return 0;
  296. }
  297. static int mtk_topckgen_disable(struct clk *clk)
  298. {
  299. struct mtk_clk_priv *priv = dev_get_priv(clk->dev);
  300. const struct mtk_composite *mux;
  301. u32 val;
  302. if (clk->id < priv->tree->muxes_offs)
  303. return 0;
  304. mux = &priv->tree->muxes[clk->id - priv->tree->muxes_offs];
  305. if (mux->gate_shift < 0)
  306. return 0;
  307. /* disable clock gate */
  308. if (mux->flags & CLK_MUX_SETCLR_UPD) {
  309. val = BIT(mux->gate_shift);
  310. writel(val, priv->base + mux->mux_set_reg);
  311. } else {
  312. val = readl(priv->base + mux->gate_reg);
  313. val |= BIT(mux->gate_shift);
  314. writel(val, priv->base + mux->gate_reg);
  315. }
  316. return 0;
  317. }
  318. static int mtk_topckgen_set_parent(struct clk *clk, struct clk *parent)
  319. {
  320. struct mtk_clk_priv *priv = dev_get_priv(clk->dev);
  321. if (clk->id < priv->tree->muxes_offs)
  322. return 0;
  323. return mtk_clk_mux_set_parent(priv->base, parent->id,
  324. &priv->tree->muxes[clk->id - priv->tree->muxes_offs]);
  325. }
  326. /* CG functions */
  327. static int mtk_clk_gate_enable(struct clk *clk)
  328. {
  329. struct mtk_cg_priv *priv = dev_get_priv(clk->dev);
  330. const struct mtk_gate *gate = &priv->gates[clk->id];
  331. u32 bit = BIT(gate->shift);
  332. switch (gate->flags & CLK_GATE_MASK) {
  333. case CLK_GATE_SETCLR:
  334. writel(bit, priv->base + gate->regs->clr_ofs);
  335. break;
  336. case CLK_GATE_SETCLR_INV:
  337. writel(bit, priv->base + gate->regs->set_ofs);
  338. break;
  339. case CLK_GATE_NO_SETCLR:
  340. clrsetbits_le32(priv->base + gate->regs->sta_ofs, bit, 0);
  341. break;
  342. case CLK_GATE_NO_SETCLR_INV:
  343. clrsetbits_le32(priv->base + gate->regs->sta_ofs, bit, bit);
  344. break;
  345. default:
  346. return -EINVAL;
  347. }
  348. return 0;
  349. }
  350. static int mtk_clk_gate_disable(struct clk *clk)
  351. {
  352. struct mtk_cg_priv *priv = dev_get_priv(clk->dev);
  353. const struct mtk_gate *gate = &priv->gates[clk->id];
  354. u32 bit = BIT(gate->shift);
  355. switch (gate->flags & CLK_GATE_MASK) {
  356. case CLK_GATE_SETCLR:
  357. writel(bit, priv->base + gate->regs->set_ofs);
  358. break;
  359. case CLK_GATE_SETCLR_INV:
  360. writel(bit, priv->base + gate->regs->clr_ofs);
  361. break;
  362. case CLK_GATE_NO_SETCLR:
  363. clrsetbits_le32(priv->base + gate->regs->sta_ofs, bit, bit);
  364. break;
  365. case CLK_GATE_NO_SETCLR_INV:
  366. clrsetbits_le32(priv->base + gate->regs->sta_ofs, bit, 0);
  367. break;
  368. default:
  369. return -EINVAL;
  370. }
  371. return 0;
  372. }
  373. static ulong mtk_clk_gate_get_rate(struct clk *clk)
  374. {
  375. struct mtk_cg_priv *priv = dev_get_priv(clk->dev);
  376. const struct mtk_gate *gate = &priv->gates[clk->id];
  377. switch (gate->flags & CLK_PARENT_MASK) {
  378. case CLK_PARENT_APMIXED:
  379. return mtk_clk_find_parent_rate(clk, gate->parent,
  380. DM_GET_DRIVER(mtk_clk_apmixedsys));
  381. break;
  382. case CLK_PARENT_TOPCKGEN:
  383. return mtk_clk_find_parent_rate(clk, gate->parent,
  384. DM_GET_DRIVER(mtk_clk_topckgen));
  385. break;
  386. default:
  387. return priv->tree->xtal_rate;
  388. }
  389. }
  390. const struct clk_ops mtk_clk_apmixedsys_ops = {
  391. .enable = mtk_apmixedsys_enable,
  392. .disable = mtk_apmixedsys_disable,
  393. .set_rate = mtk_apmixedsys_set_rate,
  394. .get_rate = mtk_apmixedsys_get_rate,
  395. };
  396. const struct clk_ops mtk_clk_topckgen_ops = {
  397. .enable = mtk_topckgen_enable,
  398. .disable = mtk_topckgen_disable,
  399. .get_rate = mtk_topckgen_get_rate,
  400. .set_parent = mtk_topckgen_set_parent,
  401. };
  402. const struct clk_ops mtk_clk_gate_ops = {
  403. .enable = mtk_clk_gate_enable,
  404. .disable = mtk_clk_gate_disable,
  405. .get_rate = mtk_clk_gate_get_rate,
  406. };
  407. int mtk_common_clk_init(struct udevice *dev,
  408. const struct mtk_clk_tree *tree)
  409. {
  410. struct mtk_clk_priv *priv = dev_get_priv(dev);
  411. priv->base = dev_read_addr_ptr(dev);
  412. if (!priv->base)
  413. return -ENOENT;
  414. priv->tree = tree;
  415. return 0;
  416. }
  417. int mtk_common_clk_gate_init(struct udevice *dev,
  418. const struct mtk_clk_tree *tree,
  419. const struct mtk_gate *gates)
  420. {
  421. struct mtk_cg_priv *priv = dev_get_priv(dev);
  422. priv->base = dev_read_addr_ptr(dev);
  423. if (!priv->base)
  424. return -ENOENT;
  425. priv->tree = tree;
  426. priv->gates = gates;
  427. return 0;
  428. }