clk-mt7629.c 21 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * MediaTek clock driver for MT7629 SoC
  4. *
  5. * Copyright (C) 2018 MediaTek Inc.
  6. * Author: Ryder Lee <ryder.lee@mediatek.com>
  7. */
  8. #include <common.h>
  9. #include <dm.h>
  10. #include <log.h>
  11. #include <asm/arch-mediatek/reset.h>
  12. #include <asm/io.h>
  13. #include <dt-bindings/clock/mt7629-clk.h>
  14. #include <linux/bitops.h>
  15. #include "clk-mtk.h"
  16. #define MT7629_CLKSQ_STB_CON0 0x20
  17. #define MT7629_PLL_ISO_CON0 0x2c
  18. #define MT7629_PLL_FMAX (2500UL * MHZ)
  19. #define MT7629_CON0_RST_BAR BIT(24)
  20. #define MCU_AXI_DIV 0x640
  21. #define AXI_DIV_MSK GENMASK(4, 0)
  22. #define AXI_DIV_SEL(x) (x)
  23. #define MCU_BUS_MUX 0x7c0
  24. #define MCU_BUS_MSK GENMASK(10, 9)
  25. #define MCU_BUS_SEL(x) ((x) << 9)
  26. /* apmixedsys */
  27. #define PLL(_id, _reg, _pwr_reg, _en_mask, _flags, _pcwbits, _pd_reg, \
  28. _pd_shift, _pcw_reg, _pcw_shift) { \
  29. .id = _id, \
  30. .reg = _reg, \
  31. .pwr_reg = _pwr_reg, \
  32. .en_mask = _en_mask, \
  33. .rst_bar_mask = MT7629_CON0_RST_BAR, \
  34. .fmax = MT7629_PLL_FMAX, \
  35. .flags = _flags, \
  36. .pcwbits = _pcwbits, \
  37. .pd_reg = _pd_reg, \
  38. .pd_shift = _pd_shift, \
  39. .pcw_reg = _pcw_reg, \
  40. .pcw_shift = _pcw_shift, \
  41. }
  42. static const struct mtk_pll_data apmixed_plls[] = {
  43. PLL(CLK_APMIXED_ARMPLL, 0x200, 0x20c, 0x1, 0,
  44. 21, 0x204, 24, 0x204, 0),
  45. PLL(CLK_APMIXED_MAINPLL, 0x210, 0x21c, 0x1, HAVE_RST_BAR,
  46. 21, 0x214, 24, 0x214, 0),
  47. PLL(CLK_APMIXED_UNIV2PLL, 0x220, 0x22c, 0x1, HAVE_RST_BAR,
  48. 7, 0x224, 24, 0x224, 14),
  49. PLL(CLK_APMIXED_ETH1PLL, 0x300, 0x310, 0x1, 0,
  50. 21, 0x300, 1, 0x304, 0),
  51. PLL(CLK_APMIXED_ETH2PLL, 0x314, 0x320, 0x1, 0,
  52. 21, 0x314, 1, 0x318, 0),
  53. PLL(CLK_APMIXED_SGMIPLL, 0x358, 0x368, 0x1, 0,
  54. 21, 0x358, 1, 0x35c, 0),
  55. };
  56. /* topckgen */
  57. #define FACTOR0(_id, _parent, _mult, _div) \
  58. FACTOR(_id, _parent, _mult, _div, CLK_PARENT_APMIXED)
  59. #define FACTOR1(_id, _parent, _mult, _div) \
  60. FACTOR(_id, _parent, _mult, _div, CLK_PARENT_TOPCKGEN)
  61. #define FACTOR2(_id, _parent, _mult, _div) \
  62. FACTOR(_id, _parent, _mult, _div, 0)
  63. static const struct mtk_fixed_clk top_fixed_clks[] = {
  64. FIXED_CLK(CLK_TOP_TO_U2_PHY, CLK_XTAL, 31250000),
  65. FIXED_CLK(CLK_TOP_TO_U2_PHY_1P, CLK_XTAL, 31250000),
  66. FIXED_CLK(CLK_TOP_PCIE0_PIPE_EN, CLK_XTAL, 125000000),
  67. FIXED_CLK(CLK_TOP_PCIE1_PIPE_EN, CLK_XTAL, 125000000),
  68. FIXED_CLK(CLK_TOP_SSUSB_TX250M, CLK_XTAL, 250000000),
  69. FIXED_CLK(CLK_TOP_SSUSB_EQ_RX250M, CLK_XTAL, 250000000),
  70. FIXED_CLK(CLK_TOP_SSUSB_CDR_REF, CLK_XTAL, 33333333),
  71. FIXED_CLK(CLK_TOP_SSUSB_CDR_FB, CLK_XTAL, 50000000),
  72. FIXED_CLK(CLK_TOP_SATA_ASIC, CLK_XTAL, 50000000),
  73. FIXED_CLK(CLK_TOP_SATA_RBC, CLK_XTAL, 50000000),
  74. };
  75. static const struct mtk_fixed_factor top_fixed_divs[] = {
  76. FACTOR0(CLK_TOP_TO_USB3_SYS, CLK_APMIXED_ETH1PLL, 1, 4),
  77. FACTOR0(CLK_TOP_P1_1MHZ, CLK_APMIXED_ETH1PLL, 1, 500),
  78. FACTOR0(CLK_TOP_4MHZ, CLK_APMIXED_ETH1PLL, 1, 125),
  79. FACTOR0(CLK_TOP_P0_1MHZ, CLK_APMIXED_ETH1PLL, 1, 500),
  80. FACTOR0(CLK_TOP_ETH_500M, CLK_APMIXED_ETH1PLL, 1, 1),
  81. FACTOR1(CLK_TOP_TXCLK_SRC_PRE, CLK_TOP_SGMIIPLL_D2, 1, 1),
  82. FACTOR2(CLK_TOP_RTC, CLK_XTAL, 1, 1024),
  83. FACTOR2(CLK_TOP_PWM_QTR_26M, CLK_XTAL, 1, 1),
  84. FACTOR2(CLK_TOP_CPUM_TCK_IN, CLK_XTAL, 1, 1),
  85. FACTOR2(CLK_TOP_TO_USB3_DA_TOP, CLK_XTAL, 1, 1),
  86. FACTOR2(CLK_TOP_MEMPLL, CLK_XTAL, 32, 1),
  87. FACTOR1(CLK_TOP_DMPLL, CLK_TOP_MEMPLL, 1, 1),
  88. FACTOR1(CLK_TOP_DMPLL_D4, CLK_TOP_MEMPLL, 1, 4),
  89. FACTOR1(CLK_TOP_DMPLL_D8, CLK_TOP_MEMPLL, 1, 8),
  90. FACTOR0(CLK_TOP_SYSPLL_D2, CLK_APMIXED_MAINPLL, 1, 2),
  91. FACTOR0(CLK_TOP_SYSPLL1_D2, CLK_APMIXED_MAINPLL, 1, 4),
  92. FACTOR0(CLK_TOP_SYSPLL1_D4, CLK_APMIXED_MAINPLL, 1, 8),
  93. FACTOR0(CLK_TOP_SYSPLL1_D8, CLK_APMIXED_MAINPLL, 1, 16),
  94. FACTOR0(CLK_TOP_SYSPLL1_D16, CLK_APMIXED_MAINPLL, 1, 32),
  95. FACTOR0(CLK_TOP_SYSPLL2_D2, CLK_APMIXED_MAINPLL, 1, 6),
  96. FACTOR0(CLK_TOP_SYSPLL2_D4, CLK_APMIXED_MAINPLL, 1, 12),
  97. FACTOR0(CLK_TOP_SYSPLL2_D8, CLK_APMIXED_MAINPLL, 1, 24),
  98. FACTOR0(CLK_TOP_SYSPLL_D5, CLK_APMIXED_MAINPLL, 1, 5),
  99. FACTOR0(CLK_TOP_SYSPLL3_D2, CLK_APMIXED_MAINPLL, 1, 10),
  100. FACTOR0(CLK_TOP_SYSPLL3_D4, CLK_APMIXED_MAINPLL, 1, 20),
  101. FACTOR0(CLK_TOP_SYSPLL_D7, CLK_APMIXED_MAINPLL, 1, 7),
  102. FACTOR0(CLK_TOP_SYSPLL4_D2, CLK_APMIXED_MAINPLL, 1, 14),
  103. FACTOR0(CLK_TOP_SYSPLL4_D4, CLK_APMIXED_MAINPLL, 1, 28),
  104. FACTOR0(CLK_TOP_SYSPLL4_D16, CLK_APMIXED_MAINPLL, 1, 112),
  105. FACTOR0(CLK_TOP_UNIVPLL, CLK_APMIXED_UNIV2PLL, 1, 2),
  106. FACTOR1(CLK_TOP_UNIVPLL1_D2, CLK_TOP_UNIVPLL, 1, 4),
  107. FACTOR1(CLK_TOP_UNIVPLL1_D4, CLK_TOP_UNIVPLL, 1, 8),
  108. FACTOR1(CLK_TOP_UNIVPLL1_D8, CLK_TOP_UNIVPLL, 1, 16),
  109. FACTOR1(CLK_TOP_UNIVPLL_D3, CLK_TOP_UNIVPLL, 1, 3),
  110. FACTOR1(CLK_TOP_UNIVPLL2_D2, CLK_TOP_UNIVPLL, 1, 6),
  111. FACTOR1(CLK_TOP_UNIVPLL2_D4, CLK_TOP_UNIVPLL, 1, 12),
  112. FACTOR1(CLK_TOP_UNIVPLL2_D8, CLK_TOP_UNIVPLL, 1, 24),
  113. FACTOR1(CLK_TOP_UNIVPLL2_D16, CLK_TOP_UNIVPLL, 1, 48),
  114. FACTOR1(CLK_TOP_UNIVPLL_D5, CLK_TOP_UNIVPLL, 1, 5),
  115. FACTOR1(CLK_TOP_UNIVPLL3_D2, CLK_TOP_UNIVPLL, 1, 10),
  116. FACTOR1(CLK_TOP_UNIVPLL3_D4, CLK_TOP_UNIVPLL, 1, 20),
  117. FACTOR1(CLK_TOP_UNIVPLL3_D16, CLK_TOP_UNIVPLL, 1, 80),
  118. FACTOR1(CLK_TOP_UNIVPLL_D7, CLK_TOP_UNIVPLL, 1, 7),
  119. FACTOR1(CLK_TOP_UNIVPLL_D80_D4, CLK_TOP_UNIVPLL, 1, 320),
  120. FACTOR1(CLK_TOP_UNIV48M, CLK_TOP_UNIVPLL, 1, 25),
  121. FACTOR0(CLK_TOP_SGMIIPLL_D2, CLK_APMIXED_SGMIPLL, 1, 2),
  122. FACTOR2(CLK_TOP_CLKXTAL_D4, CLK_XTAL, 1, 4),
  123. FACTOR1(CLK_TOP_HD_FAXI, CLK_TOP_AXI_SEL, 1, 1),
  124. FACTOR1(CLK_TOP_FAXI, CLK_TOP_AXI_SEL, 1, 1),
  125. FACTOR1(CLK_TOP_F_FAUD_INTBUS, CLK_TOP_AUD_INTBUS_SEL, 1, 1),
  126. FACTOR1(CLK_TOP_AP2WBHIF_HCLK, CLK_TOP_SYSPLL1_D8, 1, 1),
  127. FACTOR1(CLK_TOP_10M_INFRAO, CLK_TOP_10M_SEL, 1, 1),
  128. FACTOR1(CLK_TOP_MSDC30_1, CLK_TOP_MSDC30_1, 1, 1),
  129. FACTOR1(CLK_TOP_SPI, CLK_TOP_SPI0_SEL, 1, 1),
  130. FACTOR1(CLK_TOP_SF, CLK_TOP_NFI_INFRA_SEL, 1, 1),
  131. FACTOR1(CLK_TOP_FLASH, CLK_TOP_FLASH_SEL, 1, 1),
  132. FACTOR1(CLK_TOP_TO_USB3_REF, CLK_TOP_SATA_SEL, 1, 4),
  133. FACTOR1(CLK_TOP_TO_USB3_MCU, CLK_TOP_AXI_SEL, 1, 1),
  134. FACTOR1(CLK_TOP_TO_USB3_DMA, CLK_TOP_HIF_SEL, 1, 1),
  135. FACTOR1(CLK_TOP_FROM_TOP_AHB, CLK_TOP_AXI_SEL, 1, 1),
  136. FACTOR1(CLK_TOP_FROM_TOP_AXI, CLK_TOP_HIF_SEL, 1, 1),
  137. FACTOR1(CLK_TOP_PCIE1_MAC_EN, CLK_TOP_UNIVPLL1_D4, 1, 1),
  138. FACTOR1(CLK_TOP_PCIE0_MAC_EN, CLK_TOP_UNIVPLL1_D4, 1, 1),
  139. };
  140. static const int axi_parents[] = {
  141. CLK_XTAL,
  142. CLK_TOP_SYSPLL1_D2,
  143. CLK_TOP_SYSPLL_D5,
  144. CLK_TOP_SYSPLL1_D4,
  145. CLK_TOP_UNIVPLL_D5,
  146. CLK_TOP_UNIVPLL2_D2,
  147. CLK_TOP_UNIVPLL_D7,
  148. CLK_TOP_DMPLL
  149. };
  150. static const int mem_parents[] = {
  151. CLK_XTAL,
  152. CLK_TOP_DMPLL
  153. };
  154. static const int ddrphycfg_parents[] = {
  155. CLK_XTAL,
  156. CLK_TOP_SYSPLL1_D8
  157. };
  158. static const int eth_parents[] = {
  159. CLK_XTAL,
  160. CLK_TOP_SYSPLL1_D2,
  161. CLK_TOP_UNIVPLL1_D2,
  162. CLK_TOP_SYSPLL1_D4,
  163. CLK_TOP_UNIVPLL_D5,
  164. CLK_TOP_SGMIIPLL_D2,
  165. CLK_TOP_UNIVPLL_D7,
  166. CLK_TOP_DMPLL
  167. };
  168. static const int pwm_parents[] = {
  169. CLK_XTAL,
  170. CLK_TOP_UNIVPLL2_D4
  171. };
  172. static const int f10m_ref_parents[] = {
  173. CLK_XTAL,
  174. CLK_TOP_SGMIIPLL_D2
  175. };
  176. static const int nfi_infra_parents[] = {
  177. CLK_XTAL,
  178. CLK_XTAL,
  179. CLK_XTAL,
  180. CLK_XTAL,
  181. CLK_XTAL,
  182. CLK_XTAL,
  183. CLK_TOP_UNIVPLL2_D8,
  184. CLK_TOP_UNIVPLL3_D4,
  185. CLK_TOP_SYSPLL1_D8,
  186. CLK_TOP_UNIVPLL1_D8,
  187. CLK_TOP_SYSPLL4_D2,
  188. CLK_TOP_SYSPLL2_D4,
  189. CLK_TOP_UNIVPLL2_D4,
  190. CLK_TOP_UNIVPLL3_D2,
  191. CLK_TOP_SYSPLL1_D4,
  192. CLK_TOP_SYSPLL_D7
  193. };
  194. static const int flash_parents[] = {
  195. CLK_XTAL,
  196. CLK_TOP_UNIVPLL_D80_D4,
  197. CLK_TOP_SYSPLL2_D8,
  198. CLK_TOP_SYSPLL3_D4,
  199. CLK_TOP_UNIVPLL3_D4,
  200. CLK_TOP_UNIVPLL1_D8,
  201. CLK_TOP_SYSPLL2_D4,
  202. CLK_TOP_UNIVPLL2_D4
  203. };
  204. static const int uart_parents[] = {
  205. CLK_XTAL,
  206. CLK_TOP_UNIVPLL2_D8
  207. };
  208. static const int spi0_parents[] = {
  209. CLK_XTAL,
  210. CLK_TOP_SYSPLL3_D2,
  211. CLK_XTAL,
  212. CLK_TOP_SYSPLL2_D4,
  213. CLK_TOP_SYSPLL4_D2,
  214. CLK_TOP_UNIVPLL2_D4,
  215. CLK_TOP_UNIVPLL1_D8,
  216. CLK_XTAL
  217. };
  218. static const int spi1_parents[] = {
  219. CLK_XTAL,
  220. CLK_TOP_SYSPLL3_D2,
  221. CLK_XTAL,
  222. CLK_TOP_SYSPLL4_D4,
  223. CLK_TOP_SYSPLL4_D2,
  224. CLK_TOP_UNIVPLL2_D4,
  225. CLK_TOP_UNIVPLL1_D8,
  226. CLK_XTAL
  227. };
  228. static const int msdc30_0_parents[] = {
  229. CLK_XTAL,
  230. CLK_TOP_UNIVPLL2_D16,
  231. CLK_TOP_UNIV48M
  232. };
  233. static const int msdc30_1_parents[] = {
  234. CLK_XTAL,
  235. CLK_TOP_UNIVPLL2_D16,
  236. CLK_TOP_UNIV48M,
  237. CLK_TOP_SYSPLL2_D4,
  238. CLK_TOP_UNIVPLL2_D4,
  239. CLK_TOP_SYSPLL_D7,
  240. CLK_TOP_SYSPLL2_D2,
  241. CLK_TOP_UNIVPLL2_D2
  242. };
  243. static const int ap2wbmcu_parents[] = {
  244. CLK_XTAL,
  245. CLK_TOP_SYSPLL1_D2,
  246. CLK_TOP_UNIV48M,
  247. CLK_TOP_SYSPLL1_D8,
  248. CLK_TOP_UNIVPLL2_D4,
  249. CLK_TOP_SYSPLL_D7,
  250. CLK_TOP_SYSPLL2_D2,
  251. CLK_TOP_UNIVPLL2_D2
  252. };
  253. static const int audio_parents[] = {
  254. CLK_XTAL,
  255. CLK_TOP_SYSPLL3_D4,
  256. CLK_TOP_SYSPLL4_D4,
  257. CLK_TOP_SYSPLL1_D16
  258. };
  259. static const int aud_intbus_parents[] = {
  260. CLK_XTAL,
  261. CLK_TOP_SYSPLL1_D4,
  262. CLK_TOP_SYSPLL4_D2,
  263. CLK_TOP_DMPLL_D4
  264. };
  265. static const int pmicspi_parents[] = {
  266. CLK_XTAL,
  267. CLK_TOP_SYSPLL1_D8,
  268. CLK_TOP_SYSPLL3_D4,
  269. CLK_TOP_SYSPLL1_D16,
  270. CLK_TOP_UNIVPLL3_D4,
  271. CLK_XTAL,
  272. CLK_TOP_UNIVPLL2_D4,
  273. CLK_TOP_DMPLL_D8
  274. };
  275. static const int scp_parents[] = {
  276. CLK_XTAL,
  277. CLK_TOP_SYSPLL1_D8,
  278. CLK_TOP_UNIVPLL2_D2,
  279. CLK_TOP_UNIVPLL2_D4
  280. };
  281. static const int atb_parents[] = {
  282. CLK_XTAL,
  283. CLK_TOP_SYSPLL1_D2,
  284. CLK_TOP_SYSPLL_D5
  285. };
  286. static const int hif_parents[] = {
  287. CLK_XTAL,
  288. CLK_TOP_SYSPLL1_D2,
  289. CLK_TOP_UNIVPLL1_D2,
  290. CLK_TOP_SYSPLL1_D4,
  291. CLK_TOP_UNIVPLL_D5,
  292. -1,
  293. CLK_TOP_UNIVPLL_D7
  294. };
  295. static const int sata_parents[] = {
  296. CLK_XTAL,
  297. CLK_TOP_UNIVPLL2_D4
  298. };
  299. static const int usb20_parents[] = {
  300. CLK_XTAL,
  301. CLK_TOP_UNIVPLL3_D4,
  302. CLK_TOP_SYSPLL1_D8
  303. };
  304. static const int aud1_parents[] = {
  305. CLK_XTAL
  306. };
  307. static const int irrx_parents[] = {
  308. CLK_XTAL,
  309. CLK_TOP_SYSPLL4_D16
  310. };
  311. static const int crypto_parents[] = {
  312. CLK_XTAL,
  313. CLK_TOP_UNIVPLL_D3,
  314. CLK_TOP_UNIVPLL1_D2,
  315. CLK_TOP_SYSPLL1_D2,
  316. CLK_TOP_UNIVPLL_D5,
  317. CLK_TOP_SYSPLL_D5,
  318. CLK_TOP_UNIVPLL2_D2,
  319. CLK_TOP_SYSPLL_D2
  320. };
  321. static const int gpt10m_parents[] = {
  322. CLK_XTAL,
  323. CLK_TOP_CLKXTAL_D4
  324. };
  325. static const struct mtk_composite top_muxes[] = {
  326. /* CLK_CFG_0 */
  327. MUX_GATE(CLK_TOP_AXI_SEL, axi_parents, 0x40, 0, 3, 7),
  328. MUX_GATE(CLK_TOP_MEM_SEL, mem_parents, 0x40, 8, 1, 15),
  329. MUX_GATE(CLK_TOP_DDRPHYCFG_SEL, ddrphycfg_parents, 0x40, 16, 1, 23),
  330. MUX_GATE(CLK_TOP_ETH_SEL, eth_parents, 0x40, 24, 3, 31),
  331. /* CLK_CFG_1 */
  332. MUX_GATE(CLK_TOP_PWM_SEL, pwm_parents, 0x50, 0, 2, 7),
  333. MUX_GATE(CLK_TOP_F10M_REF_SEL, f10m_ref_parents, 0x50, 8, 1, 15),
  334. MUX_GATE(CLK_TOP_NFI_INFRA_SEL, nfi_infra_parents, 0x50, 16, 4, 23),
  335. MUX_GATE(CLK_TOP_FLASH_SEL, flash_parents, 0x50, 24, 3, 31),
  336. /* CLK_CFG_2 */
  337. MUX_GATE(CLK_TOP_UART_SEL, uart_parents, 0x60, 0, 1, 7),
  338. MUX_GATE(CLK_TOP_SPI0_SEL, spi0_parents, 0x60, 8, 3, 15),
  339. MUX_GATE(CLK_TOP_SPI1_SEL, spi1_parents, 0x60, 16, 3, 23),
  340. MUX_GATE(CLK_TOP_MSDC50_0_SEL, uart_parents, 0x60, 24, 3, 31),
  341. /* CLK_CFG_3 */
  342. MUX_GATE(CLK_TOP_MSDC30_0_SEL, msdc30_0_parents, 0x70, 0, 3, 7),
  343. MUX_GATE(CLK_TOP_MSDC30_1_SEL, msdc30_1_parents, 0x70, 8, 3, 15),
  344. MUX_GATE(CLK_TOP_AP2WBMCU_SEL, ap2wbmcu_parents, 0x70, 16, 3, 23),
  345. MUX_GATE(CLK_TOP_AP2WBHIF_SEL, ap2wbmcu_parents, 0x70, 24, 3, 31),
  346. /* CLK_CFG_4 */
  347. MUX_GATE(CLK_TOP_AUDIO_SEL, audio_parents, 0x80, 0, 2, 7),
  348. MUX_GATE(CLK_TOP_AUD_INTBUS_SEL, aud_intbus_parents, 0x80, 8, 2, 15),
  349. MUX_GATE(CLK_TOP_PMICSPI_SEL, pmicspi_parents, 0x80, 16, 3, 23),
  350. MUX_GATE(CLK_TOP_SCP_SEL, scp_parents, 0x80, 24, 2, 31),
  351. /* CLK_CFG_5 */
  352. MUX_GATE(CLK_TOP_ATB_SEL, atb_parents, 0x90, 0, 2, 7),
  353. MUX_GATE_FLAGS(CLK_TOP_HIF_SEL, hif_parents, 0x90, 8, 3, 15,
  354. CLK_DOMAIN_SCPSYS),
  355. MUX_GATE(CLK_TOP_SATA_SEL, sata_parents, 0x90, 16, 1, 23),
  356. MUX_GATE(CLK_TOP_U2_SEL, usb20_parents, 0x90, 24, 2, 31),
  357. /* CLK_CFG_6 */
  358. MUX_GATE(CLK_TOP_AUD1_SEL, aud1_parents, 0xA0, 0, 1, 7),
  359. MUX_GATE(CLK_TOP_AUD2_SEL, aud1_parents, 0xA0, 8, 1, 15),
  360. MUX_GATE(CLK_TOP_IRRX_SEL, irrx_parents, 0xA0, 16, 1, 23),
  361. MUX_GATE(CLK_TOP_IRTX_SEL, irrx_parents, 0xA0, 24, 1, 31),
  362. /* CLK_CFG_7 */
  363. MUX_GATE(CLK_TOP_SATA_MCU_SEL, scp_parents, 0xB0, 0, 2, 7),
  364. MUX_GATE(CLK_TOP_PCIE0_MCU_SEL, scp_parents, 0xB0, 8, 2, 15),
  365. MUX_GATE(CLK_TOP_PCIE1_MCU_SEL, scp_parents, 0xB0, 16, 2, 23),
  366. MUX_GATE(CLK_TOP_SSUSB_MCU_SEL, scp_parents, 0xB0, 24, 2, 31),
  367. /* CLK_CFG_8 */
  368. MUX_GATE(CLK_TOP_CRYPTO_SEL, crypto_parents, 0xC0, 0, 3, 7),
  369. MUX_GATE(CLK_TOP_SGMII_REF_1_SEL, f10m_ref_parents, 0xC0, 8, 1, 15),
  370. MUX_GATE(CLK_TOP_10M_SEL, gpt10m_parents, 0xC0, 16, 1, 23),
  371. };
  372. /* infracfg */
  373. static const struct mtk_gate_regs infra_cg_regs = {
  374. .set_ofs = 0x40,
  375. .clr_ofs = 0x44,
  376. .sta_ofs = 0x48,
  377. };
  378. #define GATE_INFRA(_id, _parent, _shift) { \
  379. .id = _id, \
  380. .parent = _parent, \
  381. .regs = &infra_cg_regs, \
  382. .shift = _shift, \
  383. .flags = CLK_GATE_SETCLR | CLK_PARENT_TOPCKGEN, \
  384. }
  385. static const struct mtk_gate infra_cgs[] = {
  386. GATE_INFRA(CLK_INFRA_DBGCLK_PD, CLK_TOP_HD_FAXI, 0),
  387. GATE_INFRA(CLK_INFRA_TRNG_PD, CLK_TOP_HD_FAXI, 2),
  388. GATE_INFRA(CLK_INFRA_DEVAPC_PD, CLK_TOP_HD_FAXI, 4),
  389. GATE_INFRA(CLK_INFRA_APXGPT_PD, CLK_TOP_10M_INFRAO, 18),
  390. GATE_INFRA(CLK_INFRA_SEJ_PD, CLK_TOP_10M_INFRAO, 19),
  391. };
  392. /* pericfg */
  393. static const struct mtk_gate_regs peri0_cg_regs = {
  394. .set_ofs = 0x8,
  395. .clr_ofs = 0x10,
  396. .sta_ofs = 0x18,
  397. };
  398. static const struct mtk_gate_regs peri1_cg_regs = {
  399. .set_ofs = 0xC,
  400. .clr_ofs = 0x14,
  401. .sta_ofs = 0x1C,
  402. };
  403. #define GATE_PERI0(_id, _parent, _shift) { \
  404. .id = _id, \
  405. .parent = _parent, \
  406. .regs = &peri0_cg_regs, \
  407. .shift = _shift, \
  408. .flags = CLK_GATE_SETCLR | CLK_PARENT_TOPCKGEN, \
  409. }
  410. #define GATE_PERI1(_id, _parent, _shift) { \
  411. .id = _id, \
  412. .parent = _parent, \
  413. .regs = &peri1_cg_regs, \
  414. .shift = _shift, \
  415. .flags = CLK_GATE_SETCLR | CLK_PARENT_TOPCKGEN, \
  416. }
  417. static const struct mtk_gate peri_cgs[] = {
  418. GATE_PERI0(CLK_PERI_PWM1_PD, CLK_TOP_PWM_QTR_26M, 2),
  419. GATE_PERI0(CLK_PERI_PWM2_PD, CLK_TOP_PWM_QTR_26M, 3),
  420. GATE_PERI0(CLK_PERI_PWM3_PD, CLK_TOP_PWM_QTR_26M, 4),
  421. GATE_PERI0(CLK_PERI_PWM4_PD, CLK_TOP_PWM_QTR_26M, 5),
  422. GATE_PERI0(CLK_PERI_PWM5_PD, CLK_TOP_PWM_QTR_26M, 6),
  423. GATE_PERI0(CLK_PERI_PWM6_PD, CLK_TOP_PWM_QTR_26M, 7),
  424. GATE_PERI0(CLK_PERI_PWM7_PD, CLK_TOP_PWM_QTR_26M, 8),
  425. GATE_PERI0(CLK_PERI_PWM_PD, CLK_TOP_PWM_QTR_26M, 9),
  426. GATE_PERI0(CLK_PERI_AP_DMA_PD, CLK_TOP_FAXI, 12),
  427. GATE_PERI0(CLK_PERI_MSDC30_1_PD, CLK_TOP_MSDC30_1, 14),
  428. GATE_PERI0(CLK_PERI_UART0_PD, CLK_TOP_FAXI, 17),
  429. GATE_PERI0(CLK_PERI_UART1_PD, CLK_TOP_FAXI, 18),
  430. GATE_PERI0(CLK_PERI_UART2_PD, CLK_TOP_FAXI, 19),
  431. GATE_PERI0(CLK_PERI_UART3_PD, CLK_TOP_FAXI, 20),
  432. GATE_PERI0(CLK_PERI_BTIF_PD, CLK_TOP_FAXI, 22),
  433. GATE_PERI0(CLK_PERI_I2C0_PD, CLK_TOP_FAXI, 23),
  434. GATE_PERI0(CLK_PERI_SPI0_PD, CLK_TOP_SPI, 28),
  435. GATE_PERI0(CLK_PERI_SNFI_PD, CLK_TOP_SF, 29),
  436. GATE_PERI0(CLK_PERI_NFI_PD, CLK_TOP_FAXI, 30),
  437. GATE_PERI0(CLK_PERI_NFIECC_PD, CLK_TOP_FAXI, 31),
  438. GATE_PERI1(CLK_PERI_FLASH_PD, CLK_TOP_FLASH, 1),
  439. };
  440. /* ethsys */
  441. static const struct mtk_gate_regs eth_cg_regs = {
  442. .sta_ofs = 0x30,
  443. };
  444. #define GATE_ETH(_id, _parent, _shift, _flag) { \
  445. .id = _id, \
  446. .parent = _parent, \
  447. .regs = &eth_cg_regs, \
  448. .shift = _shift, \
  449. .flags = CLK_GATE_NO_SETCLR_INV | (_flag), \
  450. }
  451. #define GATE_ETH0(_id, _parent, _shift) \
  452. GATE_ETH(_id, _parent, _shift, CLK_PARENT_APMIXED)
  453. #define GATE_ETH1(_id, _parent, _shift) \
  454. GATE_ETH(_id, _parent, _shift, CLK_PARENT_TOPCKGEN)
  455. static const struct mtk_gate eth_cgs[] = {
  456. GATE_ETH0(CLK_ETH_FE_EN, CLK_APMIXED_ETH2PLL, 6),
  457. GATE_ETH1(CLK_ETH_GP2_EN, CLK_TOP_TXCLK_SRC_PRE, 7),
  458. GATE_ETH1(CLK_ETH_GP1_EN, CLK_TOP_TXCLK_SRC_PRE, 8),
  459. GATE_ETH1(CLK_ETH_GP0_EN, CLK_TOP_TXCLK_SRC_PRE, 9),
  460. GATE_ETH1(CLK_ETH_ESW_EN, CLK_TOP_ETH_500M, 16),
  461. };
  462. static const struct mtk_gate_regs sgmii_cg_regs = {
  463. .set_ofs = 0xE4,
  464. .clr_ofs = 0xE4,
  465. .sta_ofs = 0xE4,
  466. };
  467. #define GATE_SGMII(_id, _parent, _shift) { \
  468. .id = _id, \
  469. .parent = _parent, \
  470. .regs = &sgmii_cg_regs, \
  471. .shift = _shift, \
  472. .flags = CLK_GATE_NO_SETCLR_INV | CLK_PARENT_TOPCKGEN, \
  473. }
  474. static const struct mtk_gate sgmii_cgs[] = {
  475. GATE_SGMII(CLK_SGMII_TX_EN, CLK_TOP_SSUSB_TX250M, 2),
  476. GATE_SGMII(CLK_SGMII_RX_EN, CLK_TOP_SSUSB_EQ_RX250M, 3),
  477. GATE_SGMII(CLK_SGMII_CDR_REF, CLK_TOP_SSUSB_CDR_REF, 4),
  478. GATE_SGMII(CLK_SGMII_CDR_FB, CLK_TOP_SSUSB_CDR_FB, 5),
  479. };
  480. static const struct mtk_gate_regs ssusb_cg_regs = {
  481. .set_ofs = 0x30,
  482. .clr_ofs = 0x30,
  483. .sta_ofs = 0x30,
  484. };
  485. #define GATE_SSUSB(_id, _parent, _shift) { \
  486. .id = _id, \
  487. .parent = _parent, \
  488. .regs = &ssusb_cg_regs, \
  489. .shift = _shift, \
  490. .flags = CLK_GATE_NO_SETCLR_INV | CLK_PARENT_TOPCKGEN, \
  491. }
  492. static const struct mtk_gate ssusb_cgs[] = {
  493. GATE_SSUSB(CLK_SSUSB_U2_PHY_1P_EN, CLK_TOP_TO_U2_PHY_1P, 0),
  494. GATE_SSUSB(CLK_SSUSB_U2_PHY_EN, CLK_TOP_TO_U2_PHY, 1),
  495. GATE_SSUSB(CLK_SSUSB_REF_EN, CLK_TOP_TO_USB3_REF, 5),
  496. GATE_SSUSB(CLK_SSUSB_SYS_EN, CLK_TOP_TO_USB3_SYS, 6),
  497. GATE_SSUSB(CLK_SSUSB_MCU_EN, CLK_TOP_TO_USB3_MCU, 7),
  498. GATE_SSUSB(CLK_SSUSB_DMA_EN, CLK_TOP_TO_USB3_DMA, 8),
  499. };
  500. static const struct mtk_clk_tree mt7629_clk_tree = {
  501. .xtal_rate = 40 * MHZ,
  502. .xtal2_rate = 20 * MHZ,
  503. .fdivs_offs = CLK_TOP_TO_USB3_SYS,
  504. .muxes_offs = CLK_TOP_AXI_SEL,
  505. .plls = apmixed_plls,
  506. .fclks = top_fixed_clks,
  507. .fdivs = top_fixed_divs,
  508. .muxes = top_muxes,
  509. };
  510. static int mt7629_mcucfg_probe(struct udevice *dev)
  511. {
  512. void __iomem *base;
  513. base = dev_read_addr_ptr(dev);
  514. if (!base)
  515. return -ENOENT;
  516. clrsetbits_le32(base + MCU_AXI_DIV, AXI_DIV_MSK,
  517. AXI_DIV_SEL(0x12));
  518. clrsetbits_le32(base + MCU_BUS_MUX, MCU_BUS_MSK,
  519. MCU_BUS_SEL(0x1));
  520. return 0;
  521. }
  522. static int mt7629_apmixedsys_probe(struct udevice *dev)
  523. {
  524. struct mtk_clk_priv *priv = dev_get_priv(dev);
  525. int ret;
  526. ret = mtk_common_clk_init(dev, &mt7629_clk_tree);
  527. if (ret)
  528. return ret;
  529. /* reduce clock square disable time */
  530. writel(0x501, priv->base + MT7629_CLKSQ_STB_CON0);
  531. /* extend pwr/iso control timing to 1us */
  532. writel(0x80008, priv->base + MT7629_PLL_ISO_CON0);
  533. return 0;
  534. }
  535. static int mt7629_topckgen_probe(struct udevice *dev)
  536. {
  537. return mtk_common_clk_init(dev, &mt7629_clk_tree);
  538. }
  539. static int mt7629_infracfg_probe(struct udevice *dev)
  540. {
  541. return mtk_common_clk_gate_init(dev, &mt7629_clk_tree, infra_cgs);
  542. }
  543. static int mt7629_pericfg_probe(struct udevice *dev)
  544. {
  545. return mtk_common_clk_gate_init(dev, &mt7629_clk_tree, peri_cgs);
  546. }
  547. static int mt7629_ethsys_probe(struct udevice *dev)
  548. {
  549. return mtk_common_clk_gate_init(dev, &mt7629_clk_tree, eth_cgs);
  550. }
  551. static int mt7629_ethsys_bind(struct udevice *dev)
  552. {
  553. int ret = 0;
  554. #if CONFIG_IS_ENABLED(RESET_MEDIATEK)
  555. ret = mediatek_reset_bind(dev, ETHSYS_HIFSYS_RST_CTRL_OFS, 1);
  556. if (ret)
  557. debug("Warning: failed to bind reset controller\n");
  558. #endif
  559. return ret;
  560. }
  561. static int mt7629_sgmiisys_probe(struct udevice *dev)
  562. {
  563. return mtk_common_clk_gate_init(dev, &mt7629_clk_tree, sgmii_cgs);
  564. }
  565. static int mt7629_ssusbsys_probe(struct udevice *dev)
  566. {
  567. return mtk_common_clk_gate_init(dev, &mt7629_clk_tree, ssusb_cgs);
  568. }
  569. static const struct udevice_id mt7629_apmixed_compat[] = {
  570. { .compatible = "mediatek,mt7629-apmixedsys" },
  571. { }
  572. };
  573. static const struct udevice_id mt7629_topckgen_compat[] = {
  574. { .compatible = "mediatek,mt7629-topckgen" },
  575. { }
  576. };
  577. static const struct udevice_id mt7629_infracfg_compat[] = {
  578. { .compatible = "mediatek,mt7629-infracfg", },
  579. { }
  580. };
  581. static const struct udevice_id mt7629_pericfg_compat[] = {
  582. { .compatible = "mediatek,mt7629-pericfg", },
  583. { }
  584. };
  585. static const struct udevice_id mt7629_ethsys_compat[] = {
  586. { .compatible = "mediatek,mt7629-ethsys", },
  587. { }
  588. };
  589. static const struct udevice_id mt7629_sgmiisys_compat[] = {
  590. { .compatible = "mediatek,mt7629-sgmiisys", },
  591. { }
  592. };
  593. static const struct udevice_id mt7629_ssusbsys_compat[] = {
  594. { .compatible = "mediatek,mt7629-ssusbsys" },
  595. { }
  596. };
  597. static const struct udevice_id mt7629_mcucfg_compat[] = {
  598. { .compatible = "mediatek,mt7629-mcucfg" },
  599. { }
  600. };
  601. U_BOOT_DRIVER(mtk_mcucfg) = {
  602. .name = "mt7629-mcucfg",
  603. .id = UCLASS_SYSCON,
  604. .of_match = mt7629_mcucfg_compat,
  605. .probe = mt7629_mcucfg_probe,
  606. .flags = DM_FLAG_PRE_RELOC,
  607. };
  608. U_BOOT_DRIVER(mtk_clk_apmixedsys) = {
  609. .name = "mt7629-clock-apmixedsys",
  610. .id = UCLASS_CLK,
  611. .of_match = mt7629_apmixed_compat,
  612. .probe = mt7629_apmixedsys_probe,
  613. .priv_auto_alloc_size = sizeof(struct mtk_clk_priv),
  614. .ops = &mtk_clk_apmixedsys_ops,
  615. .flags = DM_FLAG_PRE_RELOC,
  616. };
  617. U_BOOT_DRIVER(mtk_clk_topckgen) = {
  618. .name = "mt7629-clock-topckgen",
  619. .id = UCLASS_CLK,
  620. .of_match = mt7629_topckgen_compat,
  621. .probe = mt7629_topckgen_probe,
  622. .priv_auto_alloc_size = sizeof(struct mtk_clk_priv),
  623. .ops = &mtk_clk_topckgen_ops,
  624. .flags = DM_FLAG_PRE_RELOC,
  625. };
  626. U_BOOT_DRIVER(mtk_clk_infracfg) = {
  627. .name = "mt7629-clock-infracfg",
  628. .id = UCLASS_CLK,
  629. .of_match = mt7629_infracfg_compat,
  630. .probe = mt7629_infracfg_probe,
  631. .priv_auto_alloc_size = sizeof(struct mtk_cg_priv),
  632. .ops = &mtk_clk_gate_ops,
  633. .flags = DM_FLAG_PRE_RELOC,
  634. };
  635. U_BOOT_DRIVER(mtk_clk_pericfg) = {
  636. .name = "mt7629-clock-pericfg",
  637. .id = UCLASS_CLK,
  638. .of_match = mt7629_pericfg_compat,
  639. .probe = mt7629_pericfg_probe,
  640. .priv_auto_alloc_size = sizeof(struct mtk_cg_priv),
  641. .ops = &mtk_clk_gate_ops,
  642. .flags = DM_FLAG_PRE_RELOC,
  643. };
  644. U_BOOT_DRIVER(mtk_clk_ethsys) = {
  645. .name = "mt7629-clock-ethsys",
  646. .id = UCLASS_CLK,
  647. .of_match = mt7629_ethsys_compat,
  648. .probe = mt7629_ethsys_probe,
  649. .bind = mt7629_ethsys_bind,
  650. .priv_auto_alloc_size = sizeof(struct mtk_cg_priv),
  651. .ops = &mtk_clk_gate_ops,
  652. };
  653. U_BOOT_DRIVER(mtk_clk_sgmiisys) = {
  654. .name = "mt7629-clock-sgmiisys",
  655. .id = UCLASS_CLK,
  656. .of_match = mt7629_sgmiisys_compat,
  657. .probe = mt7629_sgmiisys_probe,
  658. .priv_auto_alloc_size = sizeof(struct mtk_cg_priv),
  659. .ops = &mtk_clk_gate_ops,
  660. };
  661. U_BOOT_DRIVER(mtk_clk_ssusbsys) = {
  662. .name = "mt7629-clock-ssusbsys",
  663. .id = UCLASS_CLK,
  664. .of_match = mt7629_ssusbsys_compat,
  665. .probe = mt7629_ssusbsys_probe,
  666. .priv_auto_alloc_size = sizeof(struct mtk_cg_priv),
  667. .ops = &mtk_clk_gate_ops,
  668. };