clk-mt7622.c 22 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * MediaTek clock driver for MT7622 SoC
  4. *
  5. * Copyright (C) 2019 MediaTek Inc.
  6. * Author: Ryder Lee <ryder.lee@mediatek.com>
  7. */
  8. #include <common.h>
  9. #include <dm.h>
  10. #include <log.h>
  11. #include <asm/arch-mediatek/reset.h>
  12. #include <asm/io.h>
  13. #include <dt-bindings/clock/mt7622-clk.h>
  14. #include <linux/bitops.h>
  15. #include "clk-mtk.h"
  16. #define MT7622_CLKSQ_STB_CON0 0x20
  17. #define MT7622_PLL_ISO_CON0 0x2c
  18. #define MT7622_PLL_FMAX (2500UL * MHZ)
  19. #define MT7622_CON0_RST_BAR BIT(24)
  20. #define MCU_AXI_DIV 0x640
  21. #define AXI_DIV_MSK GENMASK(4, 0)
  22. #define AXI_DIV_SEL(x) (x)
  23. #define MCU_BUS_MUX 0x7c0
  24. #define MCU_BUS_MSK GENMASK(10, 9)
  25. #define MCU_BUS_SEL(x) ((x) << 9)
  26. /* apmixedsys */
  27. #define PLL(_id, _reg, _pwr_reg, _en_mask, _flags, _pcwbits, _pd_reg, \
  28. _pd_shift, _pcw_reg, _pcw_shift) { \
  29. .id = _id, \
  30. .reg = _reg, \
  31. .pwr_reg = _pwr_reg, \
  32. .en_mask = _en_mask, \
  33. .rst_bar_mask = MT7622_CON0_RST_BAR, \
  34. .fmax = MT7622_PLL_FMAX, \
  35. .flags = _flags, \
  36. .pcwbits = _pcwbits, \
  37. .pd_reg = _pd_reg, \
  38. .pd_shift = _pd_shift, \
  39. .pcw_reg = _pcw_reg, \
  40. .pcw_shift = _pcw_shift, \
  41. }
  42. static const struct mtk_pll_data apmixed_plls[] = {
  43. PLL(CLK_APMIXED_ARMPLL, 0x200, 0x20c, 0x1, 0,
  44. 21, 0x204, 24, 0x204, 0),
  45. PLL(CLK_APMIXED_MAINPLL, 0x210, 0x21c, 0x1, HAVE_RST_BAR,
  46. 21, 0x214, 24, 0x214, 0),
  47. PLL(CLK_APMIXED_UNIV2PLL, 0x220, 0x22c, 0x1, HAVE_RST_BAR,
  48. 7, 0x224, 24, 0x224, 14),
  49. PLL(CLK_APMIXED_ETH1PLL, 0x300, 0x310, 0x1, 0,
  50. 21, 0x300, 1, 0x304, 0),
  51. PLL(CLK_APMIXED_ETH2PLL, 0x314, 0x320, 0x1, 0,
  52. 21, 0x314, 1, 0x318, 0),
  53. PLL(CLK_APMIXED_AUD1PLL, 0x324, 0x330, 0x1, 0,
  54. 31, 0x324, 1, 0x328, 0),
  55. PLL(CLK_APMIXED_AUD2PLL, 0x334, 0x340, 0x1, 0,
  56. 31, 0x334, 1, 0x338, 0),
  57. PLL(CLK_APMIXED_TRGPLL, 0x344, 0x354, 0x1, 0,
  58. 21, 0x344, 1, 0x348, 0),
  59. PLL(CLK_APMIXED_SGMIPLL, 0x358, 0x368, 0x1, 0,
  60. 21, 0x358, 1, 0x35c, 0),
  61. };
  62. /* topckgen */
  63. #define FACTOR0(_id, _parent, _mult, _div) \
  64. FACTOR(_id, _parent, _mult, _div, CLK_PARENT_APMIXED)
  65. #define FACTOR1(_id, _parent, _mult, _div) \
  66. FACTOR(_id, _parent, _mult, _div, CLK_PARENT_TOPCKGEN)
  67. #define FACTOR2(_id, _parent, _mult, _div) \
  68. FACTOR(_id, _parent, _mult, _div, 0)
  69. static const struct mtk_fixed_clk top_fixed_clks[] = {
  70. FIXED_CLK(CLK_TOP_TO_U2_PHY, CLK_XTAL, 31250000),
  71. FIXED_CLK(CLK_TOP_TO_U2_PHY_1P, CLK_XTAL, 31250000),
  72. FIXED_CLK(CLK_TOP_PCIE0_PIPE_EN, CLK_XTAL, 125000000),
  73. FIXED_CLK(CLK_TOP_PCIE1_PIPE_EN, CLK_XTAL, 125000000),
  74. FIXED_CLK(CLK_TOP_SSUSB_TX250M, CLK_XTAL, 250000000),
  75. FIXED_CLK(CLK_TOP_SSUSB_EQ_RX250M, CLK_XTAL, 250000000),
  76. FIXED_CLK(CLK_TOP_SSUSB_CDR_REF, CLK_XTAL, 33333333),
  77. FIXED_CLK(CLK_TOP_SSUSB_CDR_FB, CLK_XTAL, 50000000),
  78. FIXED_CLK(CLK_TOP_SATA_ASIC, CLK_XTAL, 50000000),
  79. FIXED_CLK(CLK_TOP_SATA_RBC, CLK_XTAL, 50000000),
  80. };
  81. static const struct mtk_fixed_factor top_fixed_divs[] = {
  82. FACTOR0(CLK_TOP_TO_USB3_SYS, CLK_APMIXED_ETH1PLL, 1, 4),
  83. FACTOR0(CLK_TOP_P1_1MHZ, CLK_APMIXED_ETH1PLL, 1, 500),
  84. FACTOR0(CLK_TOP_4MHZ, CLK_APMIXED_ETH1PLL, 1, 125),
  85. FACTOR0(CLK_TOP_P0_1MHZ, CLK_APMIXED_ETH1PLL, 1, 500),
  86. FACTOR1(CLK_TOP_TXCLK_SRC_PRE, CLK_TOP_SGMIIPLL_D2, 1, 1),
  87. FACTOR2(CLK_TOP_RTC, CLK_XTAL, 1, 1024),
  88. FACTOR2(CLK_TOP_MEMPLL, CLK_XTAL, 32, 1),
  89. FACTOR1(CLK_TOP_DMPLL, CLK_TOP_MEMPLL, 1, 1),
  90. FACTOR0(CLK_TOP_SYSPLL_D2, CLK_APMIXED_MAINPLL, 1, 2),
  91. FACTOR0(CLK_TOP_SYSPLL1_D2, CLK_APMIXED_MAINPLL, 1, 4),
  92. FACTOR0(CLK_TOP_SYSPLL1_D4, CLK_APMIXED_MAINPLL, 1, 8),
  93. FACTOR0(CLK_TOP_SYSPLL1_D8, CLK_APMIXED_MAINPLL, 1, 16),
  94. FACTOR0(CLK_TOP_SYSPLL2_D4, CLK_APMIXED_MAINPLL, 1, 12),
  95. FACTOR0(CLK_TOP_SYSPLL2_D8, CLK_APMIXED_MAINPLL, 1, 24),
  96. FACTOR0(CLK_TOP_SYSPLL_D5, CLK_APMIXED_MAINPLL, 1, 5),
  97. FACTOR0(CLK_TOP_SYSPLL3_D2, CLK_APMIXED_MAINPLL, 1, 10),
  98. FACTOR0(CLK_TOP_SYSPLL3_D4, CLK_APMIXED_MAINPLL, 1, 20),
  99. FACTOR0(CLK_TOP_SYSPLL4_D2, CLK_APMIXED_MAINPLL, 1, 14),
  100. FACTOR0(CLK_TOP_SYSPLL4_D4, CLK_APMIXED_MAINPLL, 1, 28),
  101. FACTOR0(CLK_TOP_SYSPLL4_D16, CLK_APMIXED_MAINPLL, 1, 112),
  102. FACTOR0(CLK_TOP_UNIVPLL, CLK_APMIXED_UNIV2PLL, 1, 2),
  103. FACTOR0(CLK_TOP_UNIVPLL_D2, CLK_TOP_UNIVPLL, 1, 2),
  104. FACTOR1(CLK_TOP_UNIVPLL1_D2, CLK_TOP_UNIVPLL, 1, 4),
  105. FACTOR1(CLK_TOP_UNIVPLL1_D4, CLK_TOP_UNIVPLL, 1, 8),
  106. FACTOR1(CLK_TOP_UNIVPLL1_D8, CLK_TOP_UNIVPLL, 1, 16),
  107. FACTOR1(CLK_TOP_UNIVPLL1_D16, CLK_TOP_UNIVPLL, 1, 32),
  108. FACTOR1(CLK_TOP_UNIVPLL2_D2, CLK_TOP_UNIVPLL, 1, 6),
  109. FACTOR1(CLK_TOP_UNIVPLL2_D4, CLK_TOP_UNIVPLL, 1, 12),
  110. FACTOR1(CLK_TOP_UNIVPLL2_D8, CLK_TOP_UNIVPLL, 1, 24),
  111. FACTOR1(CLK_TOP_UNIVPLL2_D16, CLK_TOP_UNIVPLL, 1, 48),
  112. FACTOR1(CLK_TOP_UNIVPLL_D5, CLK_TOP_UNIVPLL, 1, 5),
  113. FACTOR1(CLK_TOP_UNIVPLL3_D2, CLK_TOP_UNIVPLL, 1, 10),
  114. FACTOR1(CLK_TOP_UNIVPLL3_D4, CLK_TOP_UNIVPLL, 1, 20),
  115. FACTOR1(CLK_TOP_UNIVPLL3_D16, CLK_TOP_UNIVPLL, 1, 80),
  116. FACTOR1(CLK_TOP_UNIVPLL_D7, CLK_TOP_UNIVPLL, 1, 7),
  117. FACTOR1(CLK_TOP_UNIVPLL_D80_D4, CLK_TOP_UNIVPLL, 1, 320),
  118. FACTOR1(CLK_TOP_UNIV48M, CLK_TOP_UNIVPLL, 1, 25),
  119. FACTOR0(CLK_TOP_SGMIIPLL, CLK_APMIXED_SGMIPLL, 1, 1),
  120. FACTOR0(CLK_TOP_SGMIIPLL_D2, CLK_APMIXED_SGMIPLL, 1, 2),
  121. FACTOR0(CLK_TOP_AUD1PLL, CLK_APMIXED_AUD1PLL, 1, 1),
  122. FACTOR0(CLK_TOP_AUD2PLL, CLK_APMIXED_AUD2PLL, 1, 1),
  123. FACTOR1(CLK_TOP_AUD_I2S2_MCK, CLK_TOP_I2S2_MCK_SEL, 1, 2),
  124. FACTOR1(CLK_TOP_TO_USB3_REF, CLK_TOP_UNIVPLL2_D4, 1, 4),
  125. FACTOR1(CLK_TOP_PCIE1_MAC_EN, CLK_TOP_UNIVPLL1_D4, 1, 1),
  126. FACTOR1(CLK_TOP_PCIE0_MAC_EN, CLK_TOP_UNIVPLL1_D4, 1, 1),
  127. FACTOR0(CLK_TOP_ETH_500M, CLK_APMIXED_ETH1PLL, 1, 1),
  128. };
  129. static const int axi_parents[] = {
  130. CLK_XTAL,
  131. CLK_TOP_SYSPLL1_D2,
  132. CLK_TOP_SYSPLL_D5,
  133. CLK_TOP_SYSPLL1_D4,
  134. CLK_TOP_UNIVPLL_D5,
  135. CLK_TOP_UNIVPLL2_D2,
  136. CLK_TOP_UNIVPLL_D7
  137. };
  138. static const int mem_parents[] = {
  139. CLK_XTAL,
  140. CLK_TOP_DMPLL
  141. };
  142. static const int ddrphycfg_parents[] = {
  143. CLK_XTAL,
  144. CLK_TOP_SYSPLL1_D8
  145. };
  146. static const int eth_parents[] = {
  147. CLK_XTAL,
  148. CLK_TOP_SYSPLL1_D2,
  149. CLK_TOP_UNIVPLL1_D2,
  150. CLK_TOP_SYSPLL1_D4,
  151. CLK_TOP_UNIVPLL_D5,
  152. -1,
  153. CLK_TOP_UNIVPLL_D7
  154. };
  155. static const int pwm_parents[] = {
  156. CLK_XTAL,
  157. CLK_TOP_UNIVPLL2_D4
  158. };
  159. static const int f10m_ref_parents[] = {
  160. CLK_XTAL,
  161. CLK_TOP_SYSPLL4_D16
  162. };
  163. static const int nfi_infra_parents[] = {
  164. CLK_XTAL,
  165. CLK_XTAL,
  166. CLK_XTAL,
  167. CLK_XTAL,
  168. CLK_XTAL,
  169. CLK_XTAL,
  170. CLK_XTAL,
  171. CLK_XTAL,
  172. CLK_TOP_UNIVPLL2_D8,
  173. CLK_TOP_SYSPLL1_D8,
  174. CLK_TOP_UNIVPLL1_D8,
  175. CLK_TOP_SYSPLL4_D2,
  176. CLK_TOP_UNIVPLL2_D4,
  177. CLK_TOP_UNIVPLL3_D2,
  178. CLK_TOP_SYSPLL1_D4
  179. };
  180. static const int flash_parents[] = {
  181. CLK_XTAL,
  182. CLK_TOP_UNIVPLL_D80_D4,
  183. CLK_TOP_SYSPLL2_D8,
  184. CLK_TOP_SYSPLL3_D4,
  185. CLK_TOP_UNIVPLL3_D4,
  186. CLK_TOP_UNIVPLL1_D8,
  187. CLK_TOP_SYSPLL2_D4,
  188. CLK_TOP_UNIVPLL2_D4
  189. };
  190. static const int uart_parents[] = {
  191. CLK_XTAL,
  192. CLK_TOP_UNIVPLL2_D8
  193. };
  194. static const int spi0_parents[] = {
  195. CLK_XTAL,
  196. CLK_TOP_SYSPLL3_D2,
  197. CLK_XTAL,
  198. CLK_TOP_SYSPLL2_D4,
  199. CLK_TOP_SYSPLL4_D2,
  200. CLK_TOP_UNIVPLL2_D4,
  201. CLK_TOP_UNIVPLL1_D8,
  202. CLK_XTAL
  203. };
  204. static const int spi1_parents[] = {
  205. CLK_XTAL,
  206. CLK_TOP_SYSPLL3_D2,
  207. CLK_XTAL,
  208. CLK_TOP_SYSPLL4_D4,
  209. CLK_TOP_SYSPLL4_D2,
  210. CLK_TOP_UNIVPLL2_D4,
  211. CLK_TOP_UNIVPLL1_D8,
  212. CLK_XTAL
  213. };
  214. static const int msdc30_0_parents[] = {
  215. CLK_XTAL,
  216. CLK_TOP_UNIVPLL2_D16,
  217. CLK_TOP_UNIV48M
  218. };
  219. static const int a1sys_hp_parents[] = {
  220. CLK_XTAL,
  221. CLK_TOP_AUD1PLL,
  222. CLK_TOP_AUD2PLL,
  223. CLK_XTAL
  224. };
  225. static const int intdir_parents[] = {
  226. CLK_XTAL,
  227. CLK_TOP_SYSPLL1_D2,
  228. CLK_TOP_UNIVPLL_D2,
  229. CLK_TOP_SGMIIPLL
  230. };
  231. static const int aud_intbus_parents[] = {
  232. CLK_XTAL,
  233. CLK_TOP_SYSPLL1_D4,
  234. CLK_TOP_SYSPLL4_D2,
  235. CLK_TOP_SYSPLL3_D2
  236. };
  237. static const int pmicspi_parents[] = {
  238. CLK_XTAL,
  239. -1,
  240. -1,
  241. -1,
  242. -1,
  243. CLK_TOP_UNIVPLL2_D16
  244. };
  245. static const int atb_parents[] = {
  246. CLK_XTAL,
  247. CLK_TOP_SYSPLL1_D2,
  248. CLK_TOP_SYSPLL_D5
  249. };
  250. static const int audio_parents[] = {
  251. CLK_XTAL,
  252. CLK_TOP_SYSPLL3_D4,
  253. CLK_TOP_SYSPLL4_D4,
  254. CLK_TOP_UNIVPLL1_D16
  255. };
  256. static const int usb20_parents[] = {
  257. CLK_XTAL,
  258. CLK_TOP_UNIVPLL3_D4,
  259. CLK_TOP_SYSPLL1_D8,
  260. CLK_XTAL
  261. };
  262. static const int aud1_parents[] = {
  263. CLK_XTAL,
  264. CLK_TOP_AUD1PLL
  265. };
  266. static const int asm_l_parents[] = {
  267. CLK_XTAL,
  268. CLK_TOP_SYSPLL_D5,
  269. CLK_TOP_UNIVPLL2_D2,
  270. CLK_TOP_UNIVPLL2_D4
  271. };
  272. static const int apll1_ck_parents[] = {
  273. CLK_TOP_AUD1_SEL,
  274. CLK_TOP_AUD2_SEL
  275. };
  276. static const struct mtk_composite top_muxes[] = {
  277. /* CLK_CFG_0 */
  278. MUX_GATE(CLK_TOP_AXI_SEL, axi_parents, 0x40, 0, 3, 7),
  279. MUX_GATE(CLK_TOP_MEM_SEL, mem_parents, 0x40, 8, 1, 15),
  280. MUX_GATE(CLK_TOP_DDRPHYCFG_SEL, ddrphycfg_parents, 0x40, 16, 1, 23),
  281. MUX_GATE(CLK_TOP_ETH_SEL, eth_parents, 0x40, 24, 3, 31),
  282. /* CLK_CFG_1 */
  283. MUX_GATE(CLK_TOP_PWM_SEL, pwm_parents, 0x50, 0, 2, 7),
  284. MUX_GATE(CLK_TOP_F10M_REF_SEL, f10m_ref_parents, 0x50, 8, 1, 15),
  285. MUX_GATE(CLK_TOP_NFI_INFRA_SEL, nfi_infra_parents, 0x50, 16, 4, 23),
  286. MUX_GATE(CLK_TOP_FLASH_SEL, flash_parents, 0x50, 24, 3, 31),
  287. /* CLK_CFG_2 */
  288. MUX_GATE(CLK_TOP_UART_SEL, uart_parents, 0x60, 0, 1, 7),
  289. MUX_GATE(CLK_TOP_SPI0_SEL, spi0_parents, 0x60, 8, 3, 15),
  290. MUX_GATE(CLK_TOP_SPI1_SEL, spi1_parents, 0x60, 16, 3, 23),
  291. MUX_GATE(CLK_TOP_MSDC50_0_SEL, uart_parents, 0x60, 24, 3, 31),
  292. /* CLK_CFG_3 */
  293. MUX_GATE(CLK_TOP_MSDC30_0_SEL, msdc30_0_parents, 0x70, 0, 3, 7),
  294. MUX_GATE(CLK_TOP_MSDC30_1_SEL, msdc30_0_parents, 0x70, 8, 3, 15),
  295. MUX_GATE(CLK_TOP_A1SYS_HP_SEL, a1sys_hp_parents, 0x70, 16, 3, 23),
  296. MUX_GATE(CLK_TOP_A2SYS_HP_SEL, a1sys_hp_parents, 0x70, 24, 3, 31),
  297. /* CLK_CFG_4 */
  298. MUX_GATE(CLK_TOP_INTDIR_SEL, intdir_parents, 0x80, 0, 2, 7),
  299. MUX_GATE(CLK_TOP_AUD_INTBUS_SEL, aud_intbus_parents, 0x80, 8, 2, 15),
  300. MUX_GATE(CLK_TOP_PMICSPI_SEL, pmicspi_parents, 0x80, 16, 3, 23),
  301. MUX_GATE(CLK_TOP_SCP_SEL, ddrphycfg_parents, 0x80, 24, 2, 31),
  302. /* CLK_CFG_5 */
  303. MUX_GATE(CLK_TOP_ATB_SEL, atb_parents, 0x90, 0, 2, 7),
  304. MUX_GATE_FLAGS(CLK_TOP_HIF_SEL, eth_parents, 0x90, 8, 3, 15,
  305. CLK_DOMAIN_SCPSYS),
  306. MUX_GATE(CLK_TOP_AUDIO_SEL, audio_parents, 0x90, 16, 2, 23),
  307. MUX_GATE(CLK_TOP_U2_SEL, usb20_parents, 0x90, 24, 2, 31),
  308. /* CLK_CFG_6 */
  309. MUX_GATE(CLK_TOP_AUD1_SEL, aud1_parents, 0xA0, 0, 1, 7),
  310. MUX_GATE(CLK_TOP_AUD2_SEL, aud1_parents, 0xA0, 8, 1, 15),
  311. MUX_GATE(CLK_TOP_IRRX_SEL, f10m_ref_parents, 0xA0, 16, 1, 23),
  312. MUX_GATE(CLK_TOP_IRTX_SEL, f10m_ref_parents, 0xA0, 24, 1, 31),
  313. /* CLK_CFG_7 */
  314. MUX_GATE(CLK_TOP_ASM_L_SEL, asm_l_parents, 0xB0, 0, 2, 7),
  315. MUX_GATE(CLK_TOP_ASM_M_SEL, asm_l_parents, 0xB0, 8, 2, 15),
  316. MUX_GATE(CLK_TOP_ASM_H_SEL, asm_l_parents, 0xB0, 16, 2, 23),
  317. /* CLK_AUDDIV_0 */
  318. MUX(CLK_TOP_APLL1_SEL, apll1_ck_parents, 0x120, 6, 1),
  319. MUX(CLK_TOP_APLL2_SEL, apll1_ck_parents, 0x120, 7, 1),
  320. MUX(CLK_TOP_I2S0_MCK_SEL, apll1_ck_parents, 0x120, 8, 1),
  321. MUX(CLK_TOP_I2S1_MCK_SEL, apll1_ck_parents, 0x120, 9, 1),
  322. MUX(CLK_TOP_I2S2_MCK_SEL, apll1_ck_parents, 0x120, 10, 1),
  323. MUX(CLK_TOP_I2S3_MCK_SEL, apll1_ck_parents, 0x120, 161, 1),
  324. };
  325. /* infracfg */
  326. static const struct mtk_gate_regs infra_cg_regs = {
  327. .set_ofs = 0x40,
  328. .clr_ofs = 0x44,
  329. .sta_ofs = 0x48,
  330. };
  331. #define GATE_INFRA(_id, _parent, _shift) { \
  332. .id = _id, \
  333. .parent = _parent, \
  334. .regs = &infra_cg_regs, \
  335. .shift = _shift, \
  336. .flags = CLK_GATE_SETCLR | CLK_PARENT_TOPCKGEN, \
  337. }
  338. static const struct mtk_gate infra_cgs[] = {
  339. GATE_INFRA(CLK_INFRA_DBGCLK_PD, CLK_TOP_AXI_SEL, 0),
  340. GATE_INFRA(CLK_INFRA_TRNG, CLK_TOP_AXI_SEL, 2),
  341. GATE_INFRA(CLK_INFRA_AUDIO_PD, CLK_TOP_AUD_INTBUS_SEL, 5),
  342. GATE_INFRA(CLK_INFRA_IRRX_PD, CLK_TOP_IRRX_SEL, 16),
  343. GATE_INFRA(CLK_INFRA_APXGPT_PD, CLK_TOP_F10M_REF_SEL, 18),
  344. GATE_INFRA(CLK_INFRA_PMIC_PD, CLK_TOP_PMICSPI_SEL, 22),
  345. };
  346. /* pericfg */
  347. static const struct mtk_gate_regs peri0_cg_regs = {
  348. .set_ofs = 0x8,
  349. .clr_ofs = 0x10,
  350. .sta_ofs = 0x18,
  351. };
  352. static const struct mtk_gate_regs peri1_cg_regs = {
  353. .set_ofs = 0xC,
  354. .clr_ofs = 0x14,
  355. .sta_ofs = 0x1C,
  356. };
  357. #define GATE_PERI0(_id, _parent, _shift) { \
  358. .id = _id, \
  359. .parent = _parent, \
  360. .regs = &peri0_cg_regs, \
  361. .shift = _shift, \
  362. .flags = CLK_GATE_SETCLR | CLK_PARENT_TOPCKGEN, \
  363. }
  364. #define GATE_PERI1(_id, _parent, _shift) { \
  365. .id = _id, \
  366. .parent = _parent, \
  367. .regs = &peri1_cg_regs, \
  368. .shift = _shift, \
  369. .flags = CLK_GATE_SETCLR | CLK_PARENT_TOPCKGEN, \
  370. }
  371. static const struct mtk_gate peri_cgs[] = {
  372. /* PERI0 */
  373. GATE_PERI0(CLK_PERI_THERM_PD, CLK_TOP_AXI_SEL, 1),
  374. GATE_PERI0(CLK_PERI_PWM1_PD, CLK_XTAL, 2),
  375. GATE_PERI0(CLK_PERI_PWM2_PD, CLK_XTAL, 3),
  376. GATE_PERI0(CLK_PERI_PWM3_PD, CLK_XTAL, 4),
  377. GATE_PERI0(CLK_PERI_PWM4_PD, CLK_XTAL, 5),
  378. GATE_PERI0(CLK_PERI_PWM5_PD, CLK_XTAL, 6),
  379. GATE_PERI0(CLK_PERI_PWM6_PD, CLK_XTAL, 7),
  380. GATE_PERI0(CLK_PERI_PWM7_PD, CLK_XTAL, 8),
  381. GATE_PERI0(CLK_PERI_PWM_PD, CLK_XTAL, 9),
  382. GATE_PERI0(CLK_PERI_AP_DMA_PD, CLK_TOP_AXI_SEL, 12),
  383. GATE_PERI0(CLK_PERI_MSDC30_0_PD, CLK_TOP_MSDC30_0_SEL, 13),
  384. GATE_PERI0(CLK_PERI_MSDC30_1_PD, CLK_TOP_MSDC30_1_SEL, 14),
  385. GATE_PERI0(CLK_PERI_UART0_PD, CLK_TOP_AXI_SEL, 17),
  386. GATE_PERI0(CLK_PERI_UART1_PD, CLK_TOP_AXI_SEL, 18),
  387. GATE_PERI0(CLK_PERI_UART2_PD, CLK_TOP_AXI_SEL, 19),
  388. GATE_PERI0(CLK_PERI_UART3_PD, CLK_TOP_AXI_SEL, 20),
  389. GATE_PERI0(CLK_PERI_BTIF_PD, CLK_TOP_AXI_SEL, 22),
  390. GATE_PERI0(CLK_PERI_I2C0_PD, CLK_TOP_AXI_SEL, 23),
  391. GATE_PERI0(CLK_PERI_I2C1_PD, CLK_TOP_AXI_SEL, 24),
  392. GATE_PERI0(CLK_PERI_I2C2_PD, CLK_TOP_AXI_SEL, 25),
  393. GATE_PERI0(CLK_PERI_SPI1_PD, CLK_TOP_SPI1_SEL, 26),
  394. GATE_PERI0(CLK_PERI_AUXADC_PD, CLK_XTAL, 27),
  395. GATE_PERI0(CLK_PERI_SPI0_PD, CLK_TOP_SPI0_SEL, 28),
  396. GATE_PERI0(CLK_PERI_SNFI_PD, CLK_TOP_NFI_INFRA_SEL, 29),
  397. GATE_PERI0(CLK_PERI_NFI_PD, CLK_TOP_AXI_SEL, 30),
  398. GATE_PERI1(CLK_PERI_NFIECC_PD, CLK_TOP_AXI_SEL, 31),
  399. /* PERI1 */
  400. GATE_PERI1(CLK_PERI_FLASH_PD, CLK_TOP_FLASH_SEL, 1),
  401. GATE_PERI1(CLK_PERI_IRTX_PD, CLK_TOP_IRTX_SEL, 2),
  402. };
  403. /* pciesys */
  404. static const struct mtk_gate_regs pcie_cg_regs = {
  405. .set_ofs = 0x30,
  406. .clr_ofs = 0x30,
  407. .sta_ofs = 0x30,
  408. };
  409. #define GATE_PCIE(_id, _parent, _shift) { \
  410. .id = _id, \
  411. .parent = _parent, \
  412. .regs = &pcie_cg_regs, \
  413. .shift = _shift, \
  414. .flags = CLK_GATE_NO_SETCLR_INV | CLK_PARENT_TOPCKGEN, \
  415. }
  416. static const struct mtk_gate pcie_cgs[] = {
  417. GATE_PCIE(CLK_PCIE_P1_AUX_EN, CLK_TOP_P1_1MHZ, 12),
  418. GATE_PCIE(CLK_PCIE_P1_OBFF_EN, CLK_TOP_4MHZ, 13),
  419. GATE_PCIE(CLK_PCIE_P1_AHB_EN, CLK_TOP_AXI_SEL, 14),
  420. GATE_PCIE(CLK_PCIE_P1_AXI_EN, CLK_TOP_HIF_SEL, 15),
  421. GATE_PCIE(CLK_PCIE_P1_MAC_EN, CLK_TOP_PCIE1_MAC_EN, 16),
  422. GATE_PCIE(CLK_PCIE_P1_PIPE_EN, CLK_TOP_PCIE1_PIPE_EN, 17),
  423. GATE_PCIE(CLK_PCIE_P0_AUX_EN, CLK_TOP_P0_1MHZ, 18),
  424. GATE_PCIE(CLK_PCIE_P0_OBFF_EN, CLK_TOP_4MHZ, 19),
  425. GATE_PCIE(CLK_PCIE_P0_AHB_EN, CLK_TOP_AXI_SEL, 20),
  426. GATE_PCIE(CLK_PCIE_P0_AXI_EN, CLK_TOP_HIF_SEL, 21),
  427. GATE_PCIE(CLK_PCIE_P0_MAC_EN, CLK_TOP_PCIE0_MAC_EN, 22),
  428. GATE_PCIE(CLK_PCIE_P0_PIPE_EN, CLK_TOP_PCIE0_PIPE_EN, 23),
  429. GATE_PCIE(CLK_SATA_AHB_EN, CLK_TOP_AXI_SEL, 26),
  430. GATE_PCIE(CLK_SATA_AXI_EN, CLK_TOP_HIF_SEL, 27),
  431. GATE_PCIE(CLK_SATA_ASIC_EN, CLK_TOP_SATA_ASIC, 28),
  432. GATE_PCIE(CLK_SATA_RBC_EN, CLK_TOP_SATA_RBC, 29),
  433. GATE_PCIE(CLK_SATA_PM_EN, CLK_TOP_UNIVPLL2_D4, 30),
  434. };
  435. /* ethsys */
  436. static const struct mtk_gate_regs eth_cg_regs = {
  437. .sta_ofs = 0x30,
  438. };
  439. #define GATE_ETH(_id, _parent, _shift) { \
  440. .id = _id, \
  441. .parent = _parent, \
  442. .regs = &eth_cg_regs, \
  443. .shift = _shift, \
  444. .flags = CLK_GATE_NO_SETCLR_INV | CLK_PARENT_TOPCKGEN, \
  445. }
  446. static const struct mtk_gate eth_cgs[] = {
  447. GATE_ETH(CLK_ETH_HSDMA_EN, CLK_TOP_ETH_SEL, 5),
  448. GATE_ETH(CLK_ETH_ESW_EN, CLK_TOP_ETH_500M, 6),
  449. GATE_ETH(CLK_ETH_GP2_EN, CLK_TOP_TXCLK_SRC_PRE, 7),
  450. GATE_ETH(CLK_ETH_GP1_EN, CLK_TOP_TXCLK_SRC_PRE, 8),
  451. GATE_ETH(CLK_ETH_GP0_EN, CLK_TOP_TXCLK_SRC_PRE, 9),
  452. };
  453. static const struct mtk_gate_regs sgmii_cg_regs = {
  454. .sta_ofs = 0xE4,
  455. };
  456. #define GATE_SGMII(_id, _parent, _shift) { \
  457. .id = _id, \
  458. .parent = _parent, \
  459. .regs = &sgmii_cg_regs, \
  460. .shift = _shift, \
  461. .flags = CLK_GATE_NO_SETCLR_INV | CLK_PARENT_TOPCKGEN, \
  462. }
  463. static const struct mtk_gate_regs ssusb_cg_regs = {
  464. .set_ofs = 0x30,
  465. .clr_ofs = 0x30,
  466. .sta_ofs = 0x30,
  467. };
  468. #define GATE_SSUSB(_id, _parent, _shift) { \
  469. .id = _id, \
  470. .parent = _parent, \
  471. .regs = &ssusb_cg_regs, \
  472. .shift = _shift, \
  473. .flags = CLK_GATE_NO_SETCLR_INV | CLK_PARENT_TOPCKGEN, \
  474. }
  475. static const struct mtk_gate sgmii_cgs[] = {
  476. GATE_SGMII(CLK_SGMII_TX250M_EN, CLK_TOP_SSUSB_TX250M, 2),
  477. GATE_SGMII(CLK_SGMII_RX250M_EN, CLK_TOP_SSUSB_EQ_RX250M, 3),
  478. GATE_SGMII(CLK_SGMII_CDR_REF, CLK_TOP_SSUSB_CDR_REF, 4),
  479. GATE_SGMII(CLK_SGMII_CDR_FB, CLK_TOP_SSUSB_CDR_FB, 5),
  480. };
  481. static const struct mtk_gate ssusb_cgs[] = {
  482. GATE_SSUSB(CLK_SSUSB_U2_PHY_1P_EN, CLK_TOP_TO_U2_PHY_1P, 0),
  483. GATE_SSUSB(CLK_SSUSB_U2_PHY_EN, CLK_TOP_TO_U2_PHY, 1),
  484. GATE_SSUSB(CLK_SSUSB_REF_EN, CLK_TOP_TO_USB3_REF, 5),
  485. GATE_SSUSB(CLK_SSUSB_SYS_EN, CLK_TOP_TO_USB3_SYS, 6),
  486. GATE_SSUSB(CLK_SSUSB_MCU_EN, CLK_TOP_AXI_SEL, 7),
  487. GATE_SSUSB(CLK_SSUSB_DMA_EN, CLK_TOP_HIF_SEL, 8),
  488. };
  489. static const struct mtk_clk_tree mt7622_clk_tree = {
  490. .xtal_rate = 25 * MHZ,
  491. .xtal2_rate = 25 * MHZ,
  492. .fdivs_offs = CLK_TOP_TO_USB3_SYS,
  493. .muxes_offs = CLK_TOP_AXI_SEL,
  494. .plls = apmixed_plls,
  495. .fclks = top_fixed_clks,
  496. .fdivs = top_fixed_divs,
  497. .muxes = top_muxes,
  498. };
  499. static int mt7622_mcucfg_probe(struct udevice *dev)
  500. {
  501. void __iomem *base;
  502. base = dev_read_addr_ptr(dev);
  503. if (!base)
  504. return -ENOENT;
  505. clrsetbits_le32(base + MCU_AXI_DIV, AXI_DIV_MSK,
  506. AXI_DIV_SEL(0x12));
  507. clrsetbits_le32(base + MCU_BUS_MUX, MCU_BUS_MSK,
  508. MCU_BUS_SEL(0x1));
  509. return 0;
  510. }
  511. static int mt7622_apmixedsys_probe(struct udevice *dev)
  512. {
  513. struct mtk_clk_priv *priv = dev_get_priv(dev);
  514. int ret;
  515. ret = mtk_common_clk_init(dev, &mt7622_clk_tree);
  516. if (ret)
  517. return ret;
  518. /* reduce clock square disable time */
  519. // writel(0x501, priv->base + MT7622_CLKSQ_STB_CON0);
  520. writel(0x98940501, priv->base + MT7622_CLKSQ_STB_CON0);
  521. /* extend pwr/iso control timing to 1us */
  522. writel(0x80008, priv->base + MT7622_PLL_ISO_CON0);
  523. return 0;
  524. }
  525. static int mt7622_topckgen_probe(struct udevice *dev)
  526. {
  527. return mtk_common_clk_init(dev, &mt7622_clk_tree);
  528. }
  529. static int mt7622_infracfg_probe(struct udevice *dev)
  530. {
  531. return mtk_common_clk_gate_init(dev, &mt7622_clk_tree, infra_cgs);
  532. }
  533. static int mt7622_pericfg_probe(struct udevice *dev)
  534. {
  535. return mtk_common_clk_gate_init(dev, &mt7622_clk_tree, peri_cgs);
  536. }
  537. static int mt7622_pciesys_probe(struct udevice *dev)
  538. {
  539. return mtk_common_clk_gate_init(dev, &mt7622_clk_tree, pcie_cgs);
  540. }
  541. static int mt7622_pciesys_bind(struct udevice *dev)
  542. {
  543. int ret = 0;
  544. if (IS_ENABLED(CONFIG_RESET_MEDIATEK)) {
  545. ret = mediatek_reset_bind(dev, ETHSYS_HIFSYS_RST_CTRL_OFS, 1);
  546. if (ret)
  547. debug("Warning: failed to bind reset controller\n");
  548. }
  549. return ret;
  550. }
  551. static int mt7622_ethsys_probe(struct udevice *dev)
  552. {
  553. return mtk_common_clk_gate_init(dev, &mt7622_clk_tree, eth_cgs);
  554. }
  555. static int mt7622_ethsys_bind(struct udevice *dev)
  556. {
  557. int ret = 0;
  558. #if CONFIG_IS_ENABLED(RESET_MEDIATEK)
  559. ret = mediatek_reset_bind(dev, ETHSYS_HIFSYS_RST_CTRL_OFS, 1);
  560. if (ret)
  561. debug("Warning: failed to bind reset controller\n");
  562. #endif
  563. return ret;
  564. }
  565. static int mt7622_sgmiisys_probe(struct udevice *dev)
  566. {
  567. return mtk_common_clk_gate_init(dev, &mt7622_clk_tree, sgmii_cgs);
  568. }
  569. static int mt7622_ssusbsys_probe(struct udevice *dev)
  570. {
  571. return mtk_common_clk_gate_init(dev, &mt7622_clk_tree, ssusb_cgs);
  572. }
  573. static const struct udevice_id mt7622_apmixed_compat[] = {
  574. { .compatible = "mediatek,mt7622-apmixedsys" },
  575. { }
  576. };
  577. static const struct udevice_id mt7622_topckgen_compat[] = {
  578. { .compatible = "mediatek,mt7622-topckgen" },
  579. { }
  580. };
  581. static const struct udevice_id mt7622_infracfg_compat[] = {
  582. { .compatible = "mediatek,mt7622-infracfg", },
  583. { }
  584. };
  585. static const struct udevice_id mt7622_pericfg_compat[] = {
  586. { .compatible = "mediatek,mt7622-pericfg", },
  587. { }
  588. };
  589. static const struct udevice_id mt7622_pciesys_compat[] = {
  590. { .compatible = "mediatek,mt7622-pciesys", },
  591. { }
  592. };
  593. static const struct udevice_id mt7622_ethsys_compat[] = {
  594. { .compatible = "mediatek,mt7622-ethsys", },
  595. { }
  596. };
  597. static const struct udevice_id mt7622_sgmiisys_compat[] = {
  598. { .compatible = "mediatek,mt7622-sgmiisys", },
  599. { }
  600. };
  601. static const struct udevice_id mt7622_mcucfg_compat[] = {
  602. { .compatible = "mediatek,mt7622-mcucfg" },
  603. { }
  604. };
  605. static const struct udevice_id mt7622_ssusbsys_compat[] = {
  606. { .compatible = "mediatek,mt7622-ssusbsys" },
  607. { }
  608. };
  609. U_BOOT_DRIVER(mtk_mcucfg) = {
  610. .name = "mt7622-mcucfg",
  611. .id = UCLASS_SYSCON,
  612. .of_match = mt7622_mcucfg_compat,
  613. .probe = mt7622_mcucfg_probe,
  614. .flags = DM_FLAG_PRE_RELOC,
  615. };
  616. U_BOOT_DRIVER(mtk_clk_apmixedsys) = {
  617. .name = "mt7622-clock-apmixedsys",
  618. .id = UCLASS_CLK,
  619. .of_match = mt7622_apmixed_compat,
  620. .probe = mt7622_apmixedsys_probe,
  621. .priv_auto_alloc_size = sizeof(struct mtk_clk_priv),
  622. .ops = &mtk_clk_apmixedsys_ops,
  623. .flags = DM_FLAG_PRE_RELOC,
  624. };
  625. U_BOOT_DRIVER(mtk_clk_topckgen) = {
  626. .name = "mt7622-clock-topckgen",
  627. .id = UCLASS_CLK,
  628. .of_match = mt7622_topckgen_compat,
  629. .probe = mt7622_topckgen_probe,
  630. .priv_auto_alloc_size = sizeof(struct mtk_clk_priv),
  631. .ops = &mtk_clk_topckgen_ops,
  632. .flags = DM_FLAG_PRE_RELOC,
  633. };
  634. U_BOOT_DRIVER(mtk_clk_infracfg) = {
  635. .name = "mt7622-clock-infracfg",
  636. .id = UCLASS_CLK,
  637. .of_match = mt7622_infracfg_compat,
  638. .probe = mt7622_infracfg_probe,
  639. .priv_auto_alloc_size = sizeof(struct mtk_cg_priv),
  640. .ops = &mtk_clk_gate_ops,
  641. .flags = DM_FLAG_PRE_RELOC,
  642. };
  643. U_BOOT_DRIVER(mtk_clk_pericfg) = {
  644. .name = "mt7622-clock-pericfg",
  645. .id = UCLASS_CLK,
  646. .of_match = mt7622_pericfg_compat,
  647. .probe = mt7622_pericfg_probe,
  648. .priv_auto_alloc_size = sizeof(struct mtk_cg_priv),
  649. .ops = &mtk_clk_gate_ops,
  650. .flags = DM_FLAG_PRE_RELOC,
  651. };
  652. U_BOOT_DRIVER(mtk_clk_pciesys) = {
  653. .name = "mt7622-clock-pciesys",
  654. .id = UCLASS_CLK,
  655. .of_match = mt7622_pciesys_compat,
  656. .probe = mt7622_pciesys_probe,
  657. .bind = mt7622_pciesys_bind,
  658. .priv_auto_alloc_size = sizeof(struct mtk_cg_priv),
  659. .ops = &mtk_clk_gate_ops,
  660. };
  661. U_BOOT_DRIVER(mtk_clk_ethsys) = {
  662. .name = "mt7622-clock-ethsys",
  663. .id = UCLASS_CLK,
  664. .of_match = mt7622_ethsys_compat,
  665. .probe = mt7622_ethsys_probe,
  666. .bind = mt7622_ethsys_bind,
  667. .priv_auto_alloc_size = sizeof(struct mtk_cg_priv),
  668. .ops = &mtk_clk_gate_ops,
  669. };
  670. U_BOOT_DRIVER(mtk_clk_sgmiisys) = {
  671. .name = "mt7622-clock-sgmiisys",
  672. .id = UCLASS_CLK,
  673. .of_match = mt7622_sgmiisys_compat,
  674. .probe = mt7622_sgmiisys_probe,
  675. .priv_auto_alloc_size = sizeof(struct mtk_cg_priv),
  676. .ops = &mtk_clk_gate_ops,
  677. };
  678. U_BOOT_DRIVER(mtk_clk_ssusbsys) = {
  679. .name = "mt7622-clock-ssusbsys",
  680. .id = UCLASS_CLK,
  681. .of_match = mt7622_ssusbsys_compat,
  682. .probe = mt7622_ssusbsys_probe,
  683. .priv_auto_alloc_size = sizeof(struct mtk_cg_priv),
  684. .ops = &mtk_clk_gate_ops,
  685. };