clk.h 5.9 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203
  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright (C) 2019 DENX Software Engineering
  4. * Lukasz Majewski, DENX Software Engineering, lukma@denx.de
  5. */
  6. #ifndef __MACH_IMX_CLK_H
  7. #define __MACH_IMX_CLK_H
  8. #include <linux/clk-provider.h>
  9. enum imx_pllv3_type {
  10. IMX_PLLV3_GENERIC,
  11. IMX_PLLV3_SYS,
  12. IMX_PLLV3_USB,
  13. IMX_PLLV3_USB_VF610,
  14. IMX_PLLV3_AV,
  15. IMX_PLLV3_ENET,
  16. IMX_PLLV3_ENET_IMX7,
  17. IMX_PLLV3_SYS_VF610,
  18. IMX_PLLV3_DDR_IMX7,
  19. };
  20. enum imx_pll14xx_type {
  21. PLL_1416X,
  22. PLL_1443X,
  23. };
  24. /* NOTE: Rate table should be kept sorted in descending order. */
  25. struct imx_pll14xx_rate_table {
  26. unsigned int rate;
  27. unsigned int pdiv;
  28. unsigned int mdiv;
  29. unsigned int sdiv;
  30. unsigned int kdiv;
  31. };
  32. struct imx_pll14xx_clk {
  33. enum imx_pll14xx_type type;
  34. const struct imx_pll14xx_rate_table *rate_table;
  35. int rate_count;
  36. int flags;
  37. };
  38. struct clk *imx_clk_pll14xx(const char *name, const char *parent_name,
  39. void __iomem *base,
  40. const struct imx_pll14xx_clk *pll_clk);
  41. struct clk *clk_register_gate2(struct device *dev, const char *name,
  42. const char *parent_name, unsigned long flags,
  43. void __iomem *reg, u8 bit_idx, u8 cgr_val,
  44. u8 clk_gate_flags);
  45. struct clk *imx_clk_pllv3(enum imx_pllv3_type type, const char *name,
  46. const char *parent_name, void __iomem *base,
  47. u32 div_mask);
  48. static inline struct clk *imx_clk_gate2(const char *name, const char *parent,
  49. void __iomem *reg, u8 shift)
  50. {
  51. return clk_register_gate2(NULL, name, parent, CLK_SET_RATE_PARENT, reg,
  52. shift, 0x3, 0);
  53. }
  54. static inline struct clk *imx_clk_gate4(const char *name, const char *parent,
  55. void __iomem *reg, u8 shift)
  56. {
  57. return clk_register_gate2(NULL, name, parent,
  58. CLK_SET_RATE_PARENT | CLK_OPS_PARENT_ENABLE,
  59. reg, shift, 0x3, 0);
  60. }
  61. static inline struct clk *imx_clk_gate4_flags(const char *name,
  62. const char *parent, void __iomem *reg, u8 shift,
  63. unsigned long flags)
  64. {
  65. return clk_register_gate2(NULL, name, parent,
  66. flags | CLK_SET_RATE_PARENT | CLK_OPS_PARENT_ENABLE,
  67. reg, shift, 0x3, 0);
  68. }
  69. static inline struct clk *imx_clk_fixed_factor(const char *name,
  70. const char *parent, unsigned int mult, unsigned int div)
  71. {
  72. return clk_register_fixed_factor(NULL, name, parent,
  73. CLK_SET_RATE_PARENT, mult, div);
  74. }
  75. static inline struct clk *imx_clk_divider(const char *name, const char *parent,
  76. void __iomem *reg, u8 shift, u8 width)
  77. {
  78. return clk_register_divider(NULL, name, parent, CLK_SET_RATE_PARENT,
  79. reg, shift, width, 0);
  80. }
  81. static inline struct clk *
  82. imx_clk_busy_divider(const char *name, const char *parent, void __iomem *reg,
  83. u8 shift, u8 width, void __iomem *busy_reg, u8 busy_shift)
  84. {
  85. return clk_register_divider(NULL, name, parent, CLK_SET_RATE_PARENT,
  86. reg, shift, width, 0);
  87. }
  88. static inline struct clk *imx_clk_divider2(const char *name, const char *parent,
  89. void __iomem *reg, u8 shift, u8 width)
  90. {
  91. return clk_register_divider(NULL, name, parent,
  92. CLK_SET_RATE_PARENT | CLK_OPS_PARENT_ENABLE,
  93. reg, shift, width, 0);
  94. }
  95. struct clk *imx_clk_pfd(const char *name, const char *parent_name,
  96. void __iomem *reg, u8 idx);
  97. struct clk *imx_clk_fixup_mux(const char *name, void __iomem *reg,
  98. u8 shift, u8 width, const char * const *parents,
  99. int num_parents, void (*fixup)(u32 *val));
  100. static inline struct clk *imx_clk_mux_flags(const char *name,
  101. void __iomem *reg, u8 shift, u8 width,
  102. const char * const *parents, int num_parents,
  103. unsigned long flags)
  104. {
  105. return clk_register_mux(NULL, name, parents, num_parents,
  106. flags | CLK_SET_RATE_NO_REPARENT, reg, shift,
  107. width, 0);
  108. }
  109. static inline struct clk *imx_clk_mux2_flags(const char *name,
  110. void __iomem *reg, u8 shift, u8 width,
  111. const char * const *parents,
  112. int num_parents, unsigned long flags)
  113. {
  114. return clk_register_mux(NULL, name, parents, num_parents,
  115. flags | CLK_SET_RATE_NO_REPARENT | CLK_OPS_PARENT_ENABLE,
  116. reg, shift, width, 0);
  117. }
  118. static inline struct clk *imx_clk_mux(const char *name, void __iomem *reg,
  119. u8 shift, u8 width, const char * const *parents,
  120. int num_parents)
  121. {
  122. return clk_register_mux(NULL, name, parents, num_parents,
  123. CLK_SET_RATE_NO_REPARENT, reg, shift,
  124. width, 0);
  125. }
  126. static inline struct clk *
  127. imx_clk_busy_mux(const char *name, void __iomem *reg, u8 shift, u8 width,
  128. void __iomem *busy_reg, u8 busy_shift,
  129. const char * const *parents, int num_parents)
  130. {
  131. return clk_register_mux(NULL, name, parents, num_parents,
  132. CLK_SET_RATE_NO_REPARENT, reg, shift,
  133. width, 0);
  134. }
  135. static inline struct clk *imx_clk_mux2(const char *name, void __iomem *reg,
  136. u8 shift, u8 width, const char * const *parents,
  137. int num_parents)
  138. {
  139. return clk_register_mux(NULL, name, parents, num_parents,
  140. CLK_SET_RATE_NO_REPARENT | CLK_OPS_PARENT_ENABLE,
  141. reg, shift, width, 0);
  142. }
  143. static inline struct clk *imx_clk_gate(const char *name, const char *parent,
  144. void __iomem *reg, u8 shift)
  145. {
  146. return clk_register_gate(NULL, name, parent, CLK_SET_RATE_PARENT, reg,
  147. shift, 0, NULL);
  148. }
  149. static inline struct clk *imx_clk_gate_flags(const char *name, const char *parent,
  150. void __iomem *reg, u8 shift, unsigned long flags)
  151. {
  152. return clk_register_gate(NULL, name, parent, flags | CLK_SET_RATE_PARENT, reg,
  153. shift, 0, NULL);
  154. }
  155. static inline struct clk *imx_clk_gate3(const char *name, const char *parent,
  156. void __iomem *reg, u8 shift)
  157. {
  158. return clk_register_gate(NULL, name, parent,
  159. CLK_SET_RATE_PARENT | CLK_OPS_PARENT_ENABLE,
  160. reg, shift, 0, NULL);
  161. }
  162. struct clk *imx8m_clk_composite_flags(const char *name,
  163. const char * const *parent_names,
  164. int num_parents, void __iomem *reg, unsigned long flags);
  165. #define __imx8m_clk_composite(name, parent_names, reg, flags) \
  166. imx8m_clk_composite_flags(name, parent_names, \
  167. ARRAY_SIZE(parent_names), reg, \
  168. flags | CLK_SET_RATE_NO_REPARENT | CLK_OPS_PARENT_ENABLE)
  169. #define imx8m_clk_composite(name, parent_names, reg) \
  170. __imx8m_clk_composite(name, parent_names, reg, 0)
  171. #define imx8m_clk_composite_critical(name, parent_names, reg) \
  172. __imx8m_clk_composite(name, parent_names, reg, CLK_IS_CRITICAL)
  173. #endif /* __MACH_IMX_CLK_H */