clk-pll14xx.c 8.8 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * Copyright 2017-2019 NXP.
  4. *
  5. * Peng Fan <peng.fan@nxp.com>
  6. */
  7. #include <common.h>
  8. #include <asm/io.h>
  9. #include <malloc.h>
  10. #include <clk-uclass.h>
  11. #include <dm/device.h>
  12. #include <dm/devres.h>
  13. #include <linux/bitops.h>
  14. #include <linux/clk-provider.h>
  15. #include <linux/delay.h>
  16. #include <linux/err.h>
  17. #include <linux/iopoll.h>
  18. #include <clk.h>
  19. #include <div64.h>
  20. #include "clk.h"
  21. #define UBOOT_DM_CLK_IMX_PLL1443X "imx_clk_pll1443x"
  22. #define UBOOT_DM_CLK_IMX_PLL1416X "imx_clk_pll1416x"
  23. #define GNRL_CTL 0x0
  24. #define DIV_CTL 0x4
  25. #define LOCK_STATUS BIT(31)
  26. #define LOCK_SEL_MASK BIT(29)
  27. #define CLKE_MASK BIT(11)
  28. #define RST_MASK BIT(9)
  29. #define BYPASS_MASK BIT(4)
  30. #define MDIV_SHIFT 12
  31. #define MDIV_MASK GENMASK(21, 12)
  32. #define PDIV_SHIFT 4
  33. #define PDIV_MASK GENMASK(9, 4)
  34. #define SDIV_SHIFT 0
  35. #define SDIV_MASK GENMASK(2, 0)
  36. #define KDIV_SHIFT 0
  37. #define KDIV_MASK GENMASK(15, 0)
  38. #define LOCK_TIMEOUT_US 10000
  39. struct clk_pll14xx {
  40. struct clk clk;
  41. void __iomem *base;
  42. enum imx_pll14xx_type type;
  43. const struct imx_pll14xx_rate_table *rate_table;
  44. int rate_count;
  45. };
  46. #define to_clk_pll14xx(_clk) container_of(_clk, struct clk_pll14xx, clk)
  47. static const struct imx_pll14xx_rate_table *imx_get_pll_settings(
  48. struct clk_pll14xx *pll, unsigned long rate)
  49. {
  50. const struct imx_pll14xx_rate_table *rate_table = pll->rate_table;
  51. int i;
  52. for (i = 0; i < pll->rate_count; i++)
  53. if (rate == rate_table[i].rate)
  54. return &rate_table[i];
  55. return NULL;
  56. }
  57. static unsigned long clk_pll1416x_recalc_rate(struct clk *clk)
  58. {
  59. struct clk_pll14xx *pll = to_clk_pll14xx(dev_get_clk_ptr(clk->dev));
  60. u64 fvco = clk_get_parent_rate(clk);
  61. u32 mdiv, pdiv, sdiv, pll_div;
  62. pll_div = readl(pll->base + 4);
  63. mdiv = (pll_div & MDIV_MASK) >> MDIV_SHIFT;
  64. pdiv = (pll_div & PDIV_MASK) >> PDIV_SHIFT;
  65. sdiv = (pll_div & SDIV_MASK) >> SDIV_SHIFT;
  66. fvco *= mdiv;
  67. do_div(fvco, pdiv << sdiv);
  68. return fvco;
  69. }
  70. static unsigned long clk_pll1443x_recalc_rate(struct clk *clk)
  71. {
  72. struct clk_pll14xx *pll = to_clk_pll14xx(dev_get_clk_ptr(clk->dev));
  73. u64 fvco = clk_get_parent_rate(clk);
  74. u32 mdiv, pdiv, sdiv, pll_div_ctl0, pll_div_ctl1;
  75. short int kdiv;
  76. pll_div_ctl0 = readl(pll->base + 4);
  77. pll_div_ctl1 = readl(pll->base + 8);
  78. mdiv = (pll_div_ctl0 & MDIV_MASK) >> MDIV_SHIFT;
  79. pdiv = (pll_div_ctl0 & PDIV_MASK) >> PDIV_SHIFT;
  80. sdiv = (pll_div_ctl0 & SDIV_MASK) >> SDIV_SHIFT;
  81. kdiv = pll_div_ctl1 & KDIV_MASK;
  82. /* fvco = (m * 65536 + k) * Fin / (p * 65536) */
  83. fvco *= (mdiv * 65536 + kdiv);
  84. pdiv *= 65536;
  85. do_div(fvco, pdiv << sdiv);
  86. return fvco;
  87. }
  88. static inline bool clk_pll1416x_mp_change(const struct imx_pll14xx_rate_table *rate,
  89. u32 pll_div)
  90. {
  91. u32 old_mdiv, old_pdiv;
  92. old_mdiv = (pll_div & MDIV_MASK) >> MDIV_SHIFT;
  93. old_pdiv = (pll_div & PDIV_MASK) >> PDIV_SHIFT;
  94. return rate->mdiv != old_mdiv || rate->pdiv != old_pdiv;
  95. }
  96. static inline bool clk_pll1443x_mpk_change(const struct imx_pll14xx_rate_table *rate,
  97. u32 pll_div_ctl0, u32 pll_div_ctl1)
  98. {
  99. u32 old_mdiv, old_pdiv, old_kdiv;
  100. old_mdiv = (pll_div_ctl0 & MDIV_MASK) >> MDIV_SHIFT;
  101. old_pdiv = (pll_div_ctl0 & PDIV_MASK) >> PDIV_SHIFT;
  102. old_kdiv = (pll_div_ctl1 & KDIV_MASK) >> KDIV_SHIFT;
  103. return rate->mdiv != old_mdiv || rate->pdiv != old_pdiv ||
  104. rate->kdiv != old_kdiv;
  105. }
  106. static inline bool clk_pll1443x_mp_change(const struct imx_pll14xx_rate_table *rate,
  107. u32 pll_div_ctl0, u32 pll_div_ctl1)
  108. {
  109. u32 old_mdiv, old_pdiv, old_kdiv;
  110. old_mdiv = (pll_div_ctl0 & MDIV_MASK) >> MDIV_SHIFT;
  111. old_pdiv = (pll_div_ctl0 & PDIV_MASK) >> PDIV_SHIFT;
  112. old_kdiv = (pll_div_ctl1 & KDIV_MASK) >> KDIV_SHIFT;
  113. return rate->mdiv != old_mdiv || rate->pdiv != old_pdiv ||
  114. rate->kdiv != old_kdiv;
  115. }
  116. static int clk_pll14xx_wait_lock(struct clk_pll14xx *pll)
  117. {
  118. u32 val;
  119. return readl_poll_timeout(pll->base, val, val & LOCK_TIMEOUT_US,
  120. LOCK_TIMEOUT_US);
  121. }
  122. static ulong clk_pll1416x_set_rate(struct clk *clk, unsigned long drate)
  123. {
  124. struct clk_pll14xx *pll = to_clk_pll14xx(dev_get_clk_ptr(clk->dev));
  125. const struct imx_pll14xx_rate_table *rate;
  126. u32 tmp, div_val;
  127. int ret;
  128. rate = imx_get_pll_settings(pll, drate);
  129. if (!rate) {
  130. pr_err("%s: Invalid rate : %lu for pll clk %s\n", __func__,
  131. drate, "xxxx");
  132. return -EINVAL;
  133. }
  134. tmp = readl(pll->base + 4);
  135. if (!clk_pll1416x_mp_change(rate, tmp)) {
  136. tmp &= ~(SDIV_MASK) << SDIV_SHIFT;
  137. tmp |= rate->sdiv << SDIV_SHIFT;
  138. writel(tmp, pll->base + 4);
  139. return clk_pll1416x_recalc_rate(clk);
  140. }
  141. /* Bypass clock and set lock to pll output lock */
  142. tmp = readl(pll->base);
  143. tmp |= LOCK_SEL_MASK;
  144. writel(tmp, pll->base);
  145. /* Enable RST */
  146. tmp &= ~RST_MASK;
  147. writel(tmp, pll->base);
  148. /* Enable BYPASS */
  149. tmp |= BYPASS_MASK;
  150. writel(tmp, pll->base);
  151. div_val = (rate->mdiv << MDIV_SHIFT) | (rate->pdiv << PDIV_SHIFT) |
  152. (rate->sdiv << SDIV_SHIFT);
  153. writel(div_val, pll->base + 0x4);
  154. /*
  155. * According to SPEC, t3 - t2 need to be greater than
  156. * 1us and 1/FREF, respectively.
  157. * FREF is FIN / Prediv, the prediv is [1, 63], so choose
  158. * 3us.
  159. */
  160. udelay(3);
  161. /* Disable RST */
  162. tmp |= RST_MASK;
  163. writel(tmp, pll->base);
  164. /* Wait Lock */
  165. ret = clk_pll14xx_wait_lock(pll);
  166. if (ret)
  167. return ret;
  168. /* Bypass */
  169. tmp &= ~BYPASS_MASK;
  170. writel(tmp, pll->base);
  171. return clk_pll1416x_recalc_rate(clk);
  172. }
  173. static ulong clk_pll1443x_set_rate(struct clk *clk, unsigned long drate)
  174. {
  175. struct clk_pll14xx *pll = to_clk_pll14xx(dev_get_clk_ptr(clk->dev));
  176. const struct imx_pll14xx_rate_table *rate;
  177. u32 tmp, div_val;
  178. int ret;
  179. rate = imx_get_pll_settings(pll, drate);
  180. if (!rate) {
  181. pr_err("%s: Invalid rate : %lu for pll clk %s\n", __func__,
  182. drate, "===");
  183. return -EINVAL;
  184. }
  185. tmp = readl(pll->base + 4);
  186. div_val = readl(pll->base + 8);
  187. if (!clk_pll1443x_mpk_change(rate, tmp, div_val)) {
  188. tmp &= ~(SDIV_MASK) << SDIV_SHIFT;
  189. tmp |= rate->sdiv << SDIV_SHIFT;
  190. writel(tmp, pll->base + 4);
  191. return clk_pll1443x_recalc_rate(clk);
  192. }
  193. tmp = readl(pll->base);
  194. /* Enable RST */
  195. tmp &= ~RST_MASK;
  196. writel(tmp, pll->base);
  197. /* Enable BYPASS */
  198. tmp |= BYPASS_MASK;
  199. writel(tmp, pll->base);
  200. div_val = (rate->mdiv << MDIV_SHIFT) | (rate->pdiv << PDIV_SHIFT) |
  201. (rate->sdiv << SDIV_SHIFT);
  202. writel(div_val, pll->base + 0x4);
  203. writel(rate->kdiv << KDIV_SHIFT, pll->base + 0x8);
  204. /*
  205. * According to SPEC, t3 - t2 need to be greater than
  206. * 1us and 1/FREF, respectively.
  207. * FREF is FIN / Prediv, the prediv is [1, 63], so choose
  208. * 3us.
  209. */
  210. udelay(3);
  211. /* Disable RST */
  212. tmp |= RST_MASK;
  213. writel(tmp, pll->base);
  214. /* Wait Lock*/
  215. ret = clk_pll14xx_wait_lock(pll);
  216. if (ret)
  217. return ret;
  218. /* Bypass */
  219. tmp &= ~BYPASS_MASK;
  220. writel(tmp, pll->base);
  221. return clk_pll1443x_recalc_rate(clk);
  222. }
  223. static int clk_pll14xx_prepare(struct clk *clk)
  224. {
  225. struct clk_pll14xx *pll = to_clk_pll14xx(dev_get_clk_ptr(clk->dev));
  226. u32 val;
  227. /*
  228. * RESETB = 1 from 0, PLL starts its normal
  229. * operation after lock time
  230. */
  231. val = readl(pll->base + GNRL_CTL);
  232. val |= RST_MASK;
  233. writel(val, pll->base + GNRL_CTL);
  234. return clk_pll14xx_wait_lock(pll);
  235. }
  236. static int clk_pll14xx_unprepare(struct clk *clk)
  237. {
  238. struct clk_pll14xx *pll = to_clk_pll14xx(dev_get_clk_ptr(clk->dev));
  239. u32 val;
  240. /*
  241. * Set RST to 0, power down mode is enabled and
  242. * every digital block is reset
  243. */
  244. val = readl(pll->base + GNRL_CTL);
  245. val &= ~RST_MASK;
  246. writel(val, pll->base + GNRL_CTL);
  247. return 0;
  248. }
  249. static const struct clk_ops clk_pll1416x_ops = {
  250. .enable = clk_pll14xx_prepare,
  251. .disable = clk_pll14xx_unprepare,
  252. .set_rate = clk_pll1416x_set_rate,
  253. .get_rate = clk_pll1416x_recalc_rate,
  254. };
  255. static const struct clk_ops clk_pll1443x_ops = {
  256. .enable = clk_pll14xx_prepare,
  257. .disable = clk_pll14xx_unprepare,
  258. .set_rate = clk_pll1443x_set_rate,
  259. .get_rate = clk_pll1443x_recalc_rate,
  260. };
  261. struct clk *imx_clk_pll14xx(const char *name, const char *parent_name,
  262. void __iomem *base,
  263. const struct imx_pll14xx_clk *pll_clk)
  264. {
  265. struct clk_pll14xx *pll;
  266. struct clk *clk;
  267. char *type_name;
  268. int ret;
  269. pll = kzalloc(sizeof(*pll), GFP_KERNEL);
  270. if (!pll)
  271. return ERR_PTR(-ENOMEM);
  272. switch (pll_clk->type) {
  273. case PLL_1416X:
  274. type_name = UBOOT_DM_CLK_IMX_PLL1416X;
  275. break;
  276. case PLL_1443X:
  277. type_name = UBOOT_DM_CLK_IMX_PLL1443X;
  278. break;
  279. default:
  280. pr_err("%s: Unknown pll type for pll clk %s\n",
  281. __func__, name);
  282. return ERR_PTR(-EINVAL);
  283. };
  284. pll->base = base;
  285. pll->type = pll_clk->type;
  286. pll->rate_table = pll_clk->rate_table;
  287. pll->rate_count = pll_clk->rate_count;
  288. clk = &pll->clk;
  289. ret = clk_register(clk, type_name, name, parent_name);
  290. if (ret) {
  291. pr_err("%s: failed to register pll %s %d\n",
  292. __func__, name, ret);
  293. kfree(pll);
  294. return ERR_PTR(ret);
  295. }
  296. return clk;
  297. }
  298. U_BOOT_DRIVER(clk_pll1443x) = {
  299. .name = UBOOT_DM_CLK_IMX_PLL1443X,
  300. .id = UCLASS_CLK,
  301. .ops = &clk_pll1443x_ops,
  302. .flags = DM_FLAG_PRE_RELOC,
  303. };
  304. U_BOOT_DRIVER(clk_pll1416x) = {
  305. .name = UBOOT_DM_CLK_IMX_PLL1416X,
  306. .id = UCLASS_CLK,
  307. .ops = &clk_pll1416x_ops,
  308. .flags = DM_FLAG_PRE_RELOC,
  309. };