clk-imxrt1050.c 9.7 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright(C) 2019
  4. * Author(s): Giulio Benetti <giulio.benetti@benettiengineering.com>
  5. */
  6. #include <common.h>
  7. #include <clk.h>
  8. #include <clk-uclass.h>
  9. #include <dm.h>
  10. #include <log.h>
  11. #include <asm/arch/clock.h>
  12. #include <asm/arch/imx-regs.h>
  13. #include <dt-bindings/clock/imxrt1050-clock.h>
  14. #include "clk.h"
  15. static ulong imxrt1050_clk_get_rate(struct clk *clk)
  16. {
  17. struct clk *c;
  18. int ret;
  19. debug("%s(#%lu)\n", __func__, clk->id);
  20. ret = clk_get_by_id(clk->id, &c);
  21. if (ret)
  22. return ret;
  23. return clk_get_rate(c);
  24. }
  25. static ulong imxrt1050_clk_set_rate(struct clk *clk, ulong rate)
  26. {
  27. struct clk *c;
  28. int ret;
  29. debug("%s(#%lu), rate: %lu\n", __func__, clk->id, rate);
  30. ret = clk_get_by_id(clk->id, &c);
  31. if (ret)
  32. return ret;
  33. return clk_set_rate(c, rate);
  34. }
  35. static int __imxrt1050_clk_enable(struct clk *clk, bool enable)
  36. {
  37. struct clk *c;
  38. int ret;
  39. debug("%s(#%lu) en: %d\n", __func__, clk->id, enable);
  40. ret = clk_get_by_id(clk->id, &c);
  41. if (ret)
  42. return ret;
  43. if (enable)
  44. ret = clk_enable(c);
  45. else
  46. ret = clk_disable(c);
  47. return ret;
  48. }
  49. static int imxrt1050_clk_disable(struct clk *clk)
  50. {
  51. return __imxrt1050_clk_enable(clk, 0);
  52. }
  53. static int imxrt1050_clk_enable(struct clk *clk)
  54. {
  55. return __imxrt1050_clk_enable(clk, 1);
  56. }
  57. static int imxrt1050_clk_set_parent(struct clk *clk, struct clk *parent)
  58. {
  59. struct clk *c, *cp;
  60. int ret;
  61. debug("%s(#%lu), parent: %lu\n", __func__, clk->id, parent->id);
  62. ret = clk_get_by_id(clk->id, &c);
  63. if (ret)
  64. return ret;
  65. ret = clk_get_by_id(parent->id, &cp);
  66. if (ret)
  67. return ret;
  68. return clk_set_parent(c, cp);
  69. }
  70. static struct clk_ops imxrt1050_clk_ops = {
  71. .set_rate = imxrt1050_clk_set_rate,
  72. .get_rate = imxrt1050_clk_get_rate,
  73. .enable = imxrt1050_clk_enable,
  74. .disable = imxrt1050_clk_disable,
  75. .set_parent = imxrt1050_clk_set_parent,
  76. };
  77. static const char * const pll_ref_sels[] = {"osc", "dummy", };
  78. static const char * const pll1_bypass_sels[] = {"pll1_arm", "pll1_arm_ref_sel", };
  79. static const char * const pll2_bypass_sels[] = {"pll2_sys", "pll2_sys_ref_sel", };
  80. static const char * const pll3_bypass_sels[] = {"pll3_usb_otg", "pll3_usb_otg_ref_sel", };
  81. static const char * const pll5_bypass_sels[] = {"pll5_video", "pll5_video_ref_sel", };
  82. static const char *const pre_periph_sels[] = { "pll2_sys", "pll2_pfd2_396m", "pll2_pfd0_352m", "arm_podf", };
  83. static const char *const periph_sels[] = { "pre_periph_sel", "todo", };
  84. static const char *const usdhc_sels[] = { "pll2_pfd2_396m", "pll2_pfd0_352m", };
  85. static const char *const lpuart_sels[] = { "pll3_80m", "osc", };
  86. static const char *const semc_alt_sels[] = { "pll2_pfd2_396m", "pll3_pfd1_664_62m", };
  87. static const char *const semc_sels[] = { "periph_sel", "semc_alt_sel", };
  88. static const char *const lcdif_sels[] = { "pll2_sys", "pll3_pfd3_454_74m", "pll5_video", "pll2_pfd0_352m", "pll2_pfd1_594m", "pll3_pfd1_664_62m"};
  89. static int imxrt1050_clk_probe(struct udevice *dev)
  90. {
  91. void *base;
  92. /* Anatop clocks */
  93. base = (void *)ANATOP_BASE_ADDR;
  94. clk_dm(IMXRT1050_CLK_PLL1_REF_SEL,
  95. imx_clk_mux("pll1_arm_ref_sel", base + 0x0, 14, 2,
  96. pll_ref_sels, ARRAY_SIZE(pll_ref_sels)));
  97. clk_dm(IMXRT1050_CLK_PLL2_REF_SEL,
  98. imx_clk_mux("pll2_sys_ref_sel", base + 0x30, 14, 2,
  99. pll_ref_sels, ARRAY_SIZE(pll_ref_sels)));
  100. clk_dm(IMXRT1050_CLK_PLL3_REF_SEL,
  101. imx_clk_mux("pll3_usb_otg_ref_sel", base + 0x10, 14, 2,
  102. pll_ref_sels, ARRAY_SIZE(pll_ref_sels)));
  103. clk_dm(IMXRT1050_CLK_PLL5_REF_SEL,
  104. imx_clk_mux("pll5_video_ref_sel", base + 0xa0, 14, 2,
  105. pll_ref_sels, ARRAY_SIZE(pll_ref_sels)));
  106. clk_dm(IMXRT1050_CLK_PLL1_ARM,
  107. imx_clk_pllv3(IMX_PLLV3_SYS, "pll1_arm", "pll1_arm_ref_sel",
  108. base + 0x0, 0x7f));
  109. clk_dm(IMXRT1050_CLK_PLL2_SYS,
  110. imx_clk_pllv3(IMX_PLLV3_GENERIC, "pll2_sys", "pll2_sys_ref_sel",
  111. base + 0x30, 0x1));
  112. clk_dm(IMXRT1050_CLK_PLL3_USB_OTG,
  113. imx_clk_pllv3(IMX_PLLV3_USB, "pll3_usb_otg",
  114. "pll3_usb_otg_ref_sel",
  115. base + 0x10, 0x1));
  116. clk_dm(IMXRT1050_CLK_PLL5_VIDEO,
  117. imx_clk_pllv3(IMX_PLLV3_AV, "pll5_video", "pll5_video_ref_sel",
  118. base + 0xa0, 0x7f));
  119. /* PLL bypass out */
  120. clk_dm(IMXRT1050_CLK_PLL1_BYPASS,
  121. imx_clk_mux_flags("pll1_bypass", base + 0x0, 16, 1,
  122. pll1_bypass_sels,
  123. ARRAY_SIZE(pll1_bypass_sels),
  124. CLK_SET_RATE_PARENT));
  125. clk_dm(IMXRT1050_CLK_PLL2_BYPASS,
  126. imx_clk_mux_flags("pll2_bypass", base + 0x30, 16, 1,
  127. pll2_bypass_sels,
  128. ARRAY_SIZE(pll2_bypass_sels),
  129. CLK_SET_RATE_PARENT));
  130. clk_dm(IMXRT1050_CLK_PLL3_BYPASS,
  131. imx_clk_mux_flags("pll3_bypass", base + 0x10, 16, 1,
  132. pll3_bypass_sels,
  133. ARRAY_SIZE(pll3_bypass_sels),
  134. CLK_SET_RATE_PARENT));
  135. clk_dm(IMXRT1050_CLK_PLL5_BYPASS,
  136. imx_clk_mux_flags("pll5_bypass", base + 0xa0, 16, 1,
  137. pll5_bypass_sels,
  138. ARRAY_SIZE(pll5_bypass_sels),
  139. CLK_SET_RATE_PARENT));
  140. clk_dm(IMXRT1050_CLK_VIDEO_POST_DIV_SEL,
  141. imx_clk_divider("video_post_div_sel", "pll5_video",
  142. base + 0xa0, 19, 2));
  143. clk_dm(IMXRT1050_CLK_VIDEO_DIV,
  144. imx_clk_divider("video_div", "video_post_div_sel",
  145. base + 0x170, 30, 2));
  146. clk_dm(IMXRT1050_CLK_PLL3_80M,
  147. imx_clk_fixed_factor("pll3_80m", "pll3_usb_otg", 1, 6));
  148. clk_dm(IMXRT1050_CLK_PLL2_PFD0_352M,
  149. imx_clk_pfd("pll2_pfd0_352m", "pll2_sys", base + 0x100, 0));
  150. clk_dm(IMXRT1050_CLK_PLL2_PFD1_594M,
  151. imx_clk_pfd("pll2_pfd1_594m", "pll2_sys", base + 0x100, 1));
  152. clk_dm(IMXRT1050_CLK_PLL2_PFD2_396M,
  153. imx_clk_pfd("pll2_pfd2_396m", "pll2_sys", base + 0x100, 2));
  154. clk_dm(IMXRT1050_CLK_PLL3_PFD1_664_62M,
  155. imx_clk_pfd("pll3_pfd1_664_62m", "pll3_usb_otg", base + 0xf0,
  156. 1));
  157. clk_dm(IMXRT1050_CLK_PLL3_PFD3_454_74M,
  158. imx_clk_pfd("pll3_pfd3_454_74m", "pll3_usb_otg", base + 0xf0,
  159. 3));
  160. /* CCM clocks */
  161. base = dev_read_addr_ptr(dev);
  162. if (base == (void *)FDT_ADDR_T_NONE)
  163. return -EINVAL;
  164. clk_dm(IMXRT1050_CLK_ARM_PODF,
  165. imx_clk_divider("arm_podf", "pll1_arm",
  166. base + 0x10, 0, 3));
  167. clk_dm(IMXRT1050_CLK_PRE_PERIPH_SEL,
  168. imx_clk_mux("pre_periph_sel", base + 0x18, 18, 2,
  169. pre_periph_sels, ARRAY_SIZE(pre_periph_sels)));
  170. clk_dm(IMXRT1050_CLK_PERIPH_SEL,
  171. imx_clk_mux("periph_sel", base + 0x14, 25, 1,
  172. periph_sels, ARRAY_SIZE(periph_sels)));
  173. clk_dm(IMXRT1050_CLK_USDHC1_SEL,
  174. imx_clk_mux("usdhc1_sel", base + 0x1c, 16, 1,
  175. usdhc_sels, ARRAY_SIZE(usdhc_sels)));
  176. clk_dm(IMXRT1050_CLK_USDHC2_SEL,
  177. imx_clk_mux("usdhc2_sel", base + 0x1c, 17, 1,
  178. usdhc_sels, ARRAY_SIZE(usdhc_sels)));
  179. clk_dm(IMXRT1050_CLK_LPUART_SEL,
  180. imx_clk_mux("lpuart_sel", base + 0x24, 6, 1,
  181. lpuart_sels, ARRAY_SIZE(lpuart_sels)));
  182. clk_dm(IMXRT1050_CLK_SEMC_ALT_SEL,
  183. imx_clk_mux("semc_alt_sel", base + 0x14, 7, 1,
  184. semc_alt_sels, ARRAY_SIZE(semc_alt_sels)));
  185. clk_dm(IMXRT1050_CLK_SEMC_SEL,
  186. imx_clk_mux("semc_sel", base + 0x14, 6, 1,
  187. semc_sels, ARRAY_SIZE(semc_sels)));
  188. clk_dm(IMXRT1050_CLK_LCDIF_SEL,
  189. imx_clk_mux("lcdif_sel", base + 0x38, 15, 3,
  190. lcdif_sels, ARRAY_SIZE(lcdif_sels)));
  191. clk_dm(IMXRT1050_CLK_AHB_PODF,
  192. imx_clk_divider("ahb_podf", "periph_sel",
  193. base + 0x14, 10, 3));
  194. clk_dm(IMXRT1050_CLK_USDHC1_PODF,
  195. imx_clk_divider("usdhc1_podf", "usdhc1_sel",
  196. base + 0x24, 11, 3));
  197. clk_dm(IMXRT1050_CLK_USDHC2_PODF,
  198. imx_clk_divider("usdhc2_podf", "usdhc2_sel",
  199. base + 0x24, 16, 3));
  200. clk_dm(IMXRT1050_CLK_LPUART_PODF,
  201. imx_clk_divider("lpuart_podf", "lpuart_sel",
  202. base + 0x24, 0, 6));
  203. clk_dm(IMXRT1050_CLK_SEMC_PODF,
  204. imx_clk_divider("semc_podf", "semc_sel",
  205. base + 0x14, 16, 3));
  206. clk_dm(IMXRT1050_CLK_LCDIF_PRED,
  207. imx_clk_divider("lcdif_pred", "lcdif_sel",
  208. base + 0x38, 12, 3));
  209. clk_dm(IMXRT1050_CLK_LCDIF_PODF,
  210. imx_clk_divider("lcdif_podf", "lcdif_pred",
  211. base + 0x18, 23, 3));
  212. clk_dm(IMXRT1050_CLK_USDHC1,
  213. imx_clk_gate2("usdhc1", "usdhc1_podf", base + 0x80, 2));
  214. clk_dm(IMXRT1050_CLK_USDHC2,
  215. imx_clk_gate2("usdhc2", "usdhc2_podf", base + 0x80, 4));
  216. clk_dm(IMXRT1050_CLK_LPUART1,
  217. imx_clk_gate2("lpuart1", "lpuart_podf", base + 0x7c, 24));
  218. clk_dm(IMXRT1050_CLK_SEMC,
  219. imx_clk_gate2("semc", "semc_podf", base + 0x74, 4));
  220. clk_dm(IMXRT1050_CLK_LCDIF,
  221. imx_clk_gate2("lcdif", "lcdif_podf", base + 0x74, 10));
  222. struct clk *clk, *clk1;
  223. #ifdef CONFIG_SPL_BUILD
  224. /* bypass pll1 before setting its rate */
  225. clk_get_by_id(IMXRT1050_CLK_PLL1_REF_SEL, &clk);
  226. clk_get_by_id(IMXRT1050_CLK_PLL1_BYPASS, &clk1);
  227. clk_set_parent(clk1, clk);
  228. clk_get_by_id(IMXRT1050_CLK_PLL1_ARM, &clk);
  229. clk_enable(clk);
  230. clk_set_rate(clk, 1056000000UL);
  231. clk_get_by_id(IMXRT1050_CLK_PLL1_BYPASS, &clk1);
  232. clk_set_parent(clk1, clk);
  233. clk_get_by_id(IMXRT1050_CLK_SEMC_SEL, &clk1);
  234. clk_get_by_id(IMXRT1050_CLK_SEMC_ALT_SEL, &clk);
  235. clk_set_parent(clk1, clk);
  236. clk_get_by_id(IMXRT1050_CLK_PLL2_SYS, &clk);
  237. clk_enable(clk);
  238. clk_set_rate(clk, 528000000UL);
  239. clk_get_by_id(IMXRT1050_CLK_PLL2_BYPASS, &clk1);
  240. clk_set_parent(clk1, clk);
  241. /* Configure PLL3_USB_OTG to 480MHz */
  242. clk_get_by_id(IMXRT1050_CLK_PLL3_USB_OTG, &clk);
  243. clk_enable(clk);
  244. clk_set_rate(clk, 480000000UL);
  245. clk_get_by_id(IMXRT1050_CLK_PLL3_BYPASS, &clk1);
  246. clk_set_parent(clk1, clk);
  247. #else
  248. /* Set PLL5 for LCDIF to its default 650Mhz */
  249. clk_get_by_id(IMXRT1050_CLK_PLL5_VIDEO, &clk);
  250. clk_enable(clk);
  251. clk_set_rate(clk, 650000000UL);
  252. clk_get_by_id(IMXRT1050_CLK_PLL5_BYPASS, &clk1);
  253. clk_set_parent(clk1, clk);
  254. #endif
  255. return 0;
  256. }
  257. static const struct udevice_id imxrt1050_clk_ids[] = {
  258. { .compatible = "fsl,imxrt1050-ccm" },
  259. { },
  260. };
  261. U_BOOT_DRIVER(imxrt1050_clk) = {
  262. .name = "clk_imxrt1050",
  263. .id = UCLASS_CLK,
  264. .of_match = imxrt1050_clk_ids,
  265. .ops = &imxrt1050_clk_ops,
  266. .probe = imxrt1050_clk_probe,
  267. .flags = DM_FLAG_PRE_RELOC,
  268. };