clk-imxrt1020.c 6.5 KB

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  1. /* SPDX-License-Identifier: GPL-2.0+ */
  2. /*
  3. * Copyright(C) 2020
  4. * Author(s): Giulio Benetti <giulio.benetti@benettiengineering.com>
  5. */
  6. #include <common.h>
  7. #include <clk.h>
  8. #include <clk-uclass.h>
  9. #include <dm.h>
  10. #include <asm/arch/clock.h>
  11. #include <asm/arch/imx-regs.h>
  12. #include <dt-bindings/clock/imxrt1020-clock.h>
  13. #include "clk.h"
  14. static ulong imxrt1020_clk_get_rate(struct clk *clk)
  15. {
  16. struct clk *c;
  17. int ret;
  18. debug("%s(#%lu)\n", __func__, clk->id);
  19. ret = clk_get_by_id(clk->id, &c);
  20. if (ret)
  21. return ret;
  22. return clk_get_rate(c);
  23. }
  24. static ulong imxrt1020_clk_set_rate(struct clk *clk, unsigned long rate)
  25. {
  26. struct clk *c;
  27. int ret;
  28. debug("%s(#%lu), rate: %lu\n", __func__, clk->id, rate);
  29. ret = clk_get_by_id(clk->id, &c);
  30. if (ret)
  31. return ret;
  32. return clk_set_rate(c, rate);
  33. }
  34. static int __imxrt1020_clk_enable(struct clk *clk, bool enable)
  35. {
  36. struct clk *c;
  37. int ret;
  38. debug("%s(#%lu) en: %d\n", __func__, clk->id, enable);
  39. ret = clk_get_by_id(clk->id, &c);
  40. if (ret)
  41. return ret;
  42. if (enable)
  43. ret = clk_enable(c);
  44. else
  45. ret = clk_disable(c);
  46. return ret;
  47. }
  48. static int imxrt1020_clk_disable(struct clk *clk)
  49. {
  50. return __imxrt1020_clk_enable(clk, 0);
  51. }
  52. static int imxrt1020_clk_enable(struct clk *clk)
  53. {
  54. return __imxrt1020_clk_enable(clk, 1);
  55. }
  56. static struct clk_ops imxrt1020_clk_ops = {
  57. .set_rate = imxrt1020_clk_set_rate,
  58. .get_rate = imxrt1020_clk_get_rate,
  59. .enable = imxrt1020_clk_enable,
  60. .disable = imxrt1020_clk_disable,
  61. };
  62. static const char * const pll2_bypass_sels[] = {"pll2_sys", "osc", };
  63. static const char * const pll3_bypass_sels[] = {"pll3_usb_otg", "osc", };
  64. static const char *const pre_periph_sels[] = { "pll2_sys", "pll2_pfd3_297m", "pll3_pfd3_454_74m", "arm_podf", };
  65. static const char *const periph_sels[] = { "pre_periph_sel", "todo", };
  66. static const char *const usdhc_sels[] = { "pll2_pfd2_396m", "pll2_pfd0_352m", };
  67. static const char *const lpuart_sels[] = { "pll3_80m", "osc", };
  68. static const char *const semc_alt_sels[] = { "pll2_pfd2_396m", "pll3_pfd1_664_62m", };
  69. static const char *const semc_sels[] = { "periph_sel", "semc_alt_sel", };
  70. static int imxrt1020_clk_probe(struct udevice *dev)
  71. {
  72. void *base;
  73. /* Anatop clocks */
  74. base = (void *)ANATOP_BASE_ADDR;
  75. clk_dm(IMXRT1020_CLK_PLL2_SYS,
  76. imx_clk_pllv3(IMX_PLLV3_GENERIC, "pll2_sys", "osc",
  77. base + 0x30, 0x1));
  78. clk_dm(IMXRT1020_CLK_PLL3_USB_OTG,
  79. imx_clk_pllv3(IMX_PLLV3_USB, "pll3_usb_otg", "osc",
  80. base + 0x10, 0x1));
  81. /* PLL bypass out */
  82. clk_dm(IMXRT1020_CLK_PLL2_BYPASS,
  83. imx_clk_mux_flags("pll2_bypass", base + 0x30, 16, 1,
  84. pll2_bypass_sels,
  85. ARRAY_SIZE(pll2_bypass_sels),
  86. CLK_SET_RATE_PARENT));
  87. clk_dm(IMXRT1020_CLK_PLL3_BYPASS,
  88. imx_clk_mux_flags("pll3_bypass", base + 0x10, 16, 1,
  89. pll3_bypass_sels,
  90. ARRAY_SIZE(pll3_bypass_sels),
  91. CLK_SET_RATE_PARENT));
  92. clk_dm(IMXRT1020_CLK_PLL3_80M,
  93. imx_clk_fixed_factor("pll3_80m", "pll3_usb_otg", 1, 6));
  94. clk_dm(IMXRT1020_CLK_PLL2_PFD0_352M,
  95. imx_clk_pfd("pll2_pfd0_352m", "pll2_sys", base + 0x100, 0));
  96. clk_dm(IMXRT1020_CLK_PLL2_PFD1_594M,
  97. imx_clk_pfd("pll2_pfd1_594m", "pll2_sys", base + 0x100, 1));
  98. clk_dm(IMXRT1020_CLK_PLL2_PFD2_396M,
  99. imx_clk_pfd("pll2_pfd2_396m", "pll2_sys", base + 0x100, 2));
  100. clk_dm(IMXRT1020_CLK_PLL2_PFD3_297M,
  101. imx_clk_pfd("pll2_pfd3_297m", "pll2_sys", base + 0x100, 3));
  102. clk_dm(IMXRT1020_CLK_PLL3_PFD1_664_62M,
  103. imx_clk_pfd("pll3_pfd1_664_62m", "pll3_usb_otg", base + 0xf0, 1));
  104. clk_dm(IMXRT1020_CLK_PLL3_PFD3_454_74M,
  105. imx_clk_pfd("pll3_pfd3_454_74m", "pll3_usb_otg", base + 0xf0, 3));
  106. /* CCM clocks */
  107. base = dev_read_addr_ptr(dev);
  108. if (base == (void *)FDT_ADDR_T_NONE)
  109. return -EINVAL;
  110. clk_dm(IMXRT1020_CLK_PRE_PERIPH_SEL,
  111. imx_clk_mux("pre_periph_sel", base + 0x18, 18, 2,
  112. pre_periph_sels, ARRAY_SIZE(pre_periph_sels)));
  113. clk_dm(IMXRT1020_CLK_PERIPH_SEL,
  114. imx_clk_mux("periph_sel", base + 0x14, 25, 1,
  115. periph_sels, ARRAY_SIZE(periph_sels)));
  116. clk_dm(IMXRT1020_CLK_USDHC1_SEL,
  117. imx_clk_mux("usdhc1_sel", base + 0x1c, 16, 1,
  118. usdhc_sels, ARRAY_SIZE(usdhc_sels)));
  119. clk_dm(IMXRT1020_CLK_USDHC2_SEL,
  120. imx_clk_mux("usdhc2_sel", base + 0x1c, 17, 1,
  121. usdhc_sels, ARRAY_SIZE(usdhc_sels)));
  122. clk_dm(IMXRT1020_CLK_LPUART_SEL,
  123. imx_clk_mux("lpuart_sel", base + 0x24, 6, 1,
  124. lpuart_sels, ARRAY_SIZE(lpuart_sels)));
  125. clk_dm(IMXRT1020_CLK_SEMC_ALT_SEL,
  126. imx_clk_mux("semc_alt_sel", base + 0x14, 7, 1,
  127. semc_alt_sels, ARRAY_SIZE(semc_alt_sels)));
  128. clk_dm(IMXRT1020_CLK_SEMC_SEL,
  129. imx_clk_mux("semc_sel", base + 0x14, 6, 1,
  130. semc_sels, ARRAY_SIZE(semc_sels)));
  131. clk_dm(IMXRT1020_CLK_AHB_PODF,
  132. imx_clk_divider("ahb_podf", "periph_sel",
  133. base + 0x14, 10, 3));
  134. clk_dm(IMXRT1020_CLK_USDHC1_PODF,
  135. imx_clk_divider("usdhc1_podf", "usdhc1_sel",
  136. base + 0x24, 11, 3));
  137. clk_dm(IMXRT1020_CLK_USDHC2_PODF,
  138. imx_clk_divider("usdhc2_podf", "usdhc2_sel",
  139. base + 0x24, 16, 3));
  140. clk_dm(IMXRT1020_CLK_LPUART_PODF,
  141. imx_clk_divider("lpuart_podf", "lpuart_sel",
  142. base + 0x24, 0, 6));
  143. clk_dm(IMXRT1020_CLK_SEMC_PODF,
  144. imx_clk_divider("semc_podf", "semc_sel",
  145. base + 0x14, 16, 3));
  146. clk_dm(IMXRT1020_CLK_USDHC1,
  147. imx_clk_gate2("usdhc1", "usdhc1_podf", base + 0x80, 2));
  148. clk_dm(IMXRT1020_CLK_USDHC2,
  149. imx_clk_gate2("usdhc2", "usdhc2_podf", base + 0x80, 4));
  150. clk_dm(IMXRT1020_CLK_LPUART1,
  151. imx_clk_gate2("lpuart1", "lpuart_podf", base + 0x7c, 24));
  152. clk_dm(IMXRT1020_CLK_SEMC,
  153. imx_clk_gate2("semc", "semc_podf", base + 0x74, 4));
  154. #ifdef CONFIG_SPL_BUILD
  155. struct clk *clk, *clk1;
  156. clk_get_by_id(IMXRT1020_CLK_SEMC_SEL, &clk1);
  157. clk_get_by_id(IMXRT1020_CLK_SEMC_ALT_SEL, &clk);
  158. clk_set_parent(clk1, clk);
  159. /* Configure PLL3_USB_OTG to 480MHz */
  160. clk_get_by_id(IMXRT1020_CLK_PLL3_USB_OTG, &clk);
  161. clk_enable(clk);
  162. clk_set_rate(clk, 480000000UL);
  163. clk_get_by_id(IMXRT1020_CLK_PLL3_BYPASS, &clk1);
  164. clk_set_parent(clk1, clk);
  165. clk_get_by_id(IMXRT1020_CLK_PLL2_PFD3_297M, &clk);
  166. clk_set_rate(clk, 297000000UL);
  167. clk_get_by_id(IMXRT1020_CLK_PLL2_SYS, &clk);
  168. clk_enable(clk);
  169. clk_set_rate(clk, 528000000UL);
  170. clk_get_by_id(IMXRT1020_CLK_PLL2_BYPASS, &clk1);
  171. clk_set_parent(clk1, clk);
  172. #endif
  173. return 0;
  174. }
  175. static const struct udevice_id imxrt1020_clk_ids[] = {
  176. { .compatible = "fsl,imxrt1020-ccm" },
  177. { },
  178. };
  179. U_BOOT_DRIVER(imxrt1020_clk) = {
  180. .name = "clk_imxrt1020",
  181. .id = UCLASS_CLK,
  182. .of_match = imxrt1020_clk_ids,
  183. .ops = &imxrt1020_clk_ops,
  184. .probe = imxrt1020_clk_probe,
  185. .flags = DM_FLAG_PRE_RELOC,
  186. };