clk-imx8qxp.c 7.1 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * Copyright 2018 NXP
  4. * Peng Fan <peng.fan@nxp.com>
  5. */
  6. #include <common.h>
  7. #include <clk-uclass.h>
  8. #include <dm.h>
  9. #include <log.h>
  10. #include <asm/arch/sci/sci.h>
  11. #include <asm/arch/clock.h>
  12. #include <dt-bindings/clock/imx8qxp-clock.h>
  13. #include <dt-bindings/soc/imx_rsrc.h>
  14. #include <misc.h>
  15. #include "clk-imx8.h"
  16. #if CONFIG_IS_ENABLED(CMD_CLK)
  17. struct imx8_clks imx8_clk_names[] = {
  18. { IMX8QXP_A35_DIV, "A35_DIV" },
  19. { IMX8QXP_I2C0_CLK, "I2C0" },
  20. { IMX8QXP_I2C1_CLK, "I2C1" },
  21. { IMX8QXP_I2C2_CLK, "I2C2" },
  22. { IMX8QXP_I2C3_CLK, "I2C3" },
  23. { IMX8QXP_UART0_CLK, "UART0" },
  24. { IMX8QXP_UART1_CLK, "UART1" },
  25. { IMX8QXP_UART2_CLK, "UART2" },
  26. { IMX8QXP_UART3_CLK, "UART3" },
  27. { IMX8QXP_SDHC0_CLK, "SDHC0" },
  28. { IMX8QXP_SDHC1_CLK, "SDHC1" },
  29. { IMX8QXP_ENET0_AHB_CLK, "ENET0_AHB" },
  30. { IMX8QXP_ENET0_IPG_CLK, "ENET0_IPG" },
  31. { IMX8QXP_ENET0_REF_DIV, "ENET0_REF" },
  32. { IMX8QXP_ENET0_PTP_CLK, "ENET0_PTP" },
  33. { IMX8QXP_ENET1_AHB_CLK, "ENET1_AHB" },
  34. { IMX8QXP_ENET1_IPG_CLK, "ENET1_IPG" },
  35. { IMX8QXP_ENET1_REF_DIV, "ENET1_REF" },
  36. { IMX8QXP_ENET1_PTP_CLK, "ENET1_PTP" },
  37. };
  38. int num_clks = ARRAY_SIZE(imx8_clk_names);
  39. #endif
  40. ulong imx8_clk_get_rate(struct clk *clk)
  41. {
  42. sc_pm_clk_t pm_clk;
  43. ulong rate;
  44. u16 resource;
  45. int ret;
  46. debug("%s(#%lu)\n", __func__, clk->id);
  47. switch (clk->id) {
  48. case IMX8QXP_A35_DIV:
  49. resource = SC_R_A35;
  50. pm_clk = SC_PM_CLK_CPU;
  51. break;
  52. case IMX8QXP_I2C0_CLK:
  53. case IMX8QXP_I2C0_IPG_CLK:
  54. resource = SC_R_I2C_0;
  55. pm_clk = SC_PM_CLK_PER;
  56. break;
  57. case IMX8QXP_I2C1_CLK:
  58. case IMX8QXP_I2C1_IPG_CLK:
  59. resource = SC_R_I2C_1;
  60. pm_clk = SC_PM_CLK_PER;
  61. break;
  62. case IMX8QXP_I2C2_CLK:
  63. case IMX8QXP_I2C2_IPG_CLK:
  64. resource = SC_R_I2C_2;
  65. pm_clk = SC_PM_CLK_PER;
  66. break;
  67. case IMX8QXP_I2C3_CLK:
  68. case IMX8QXP_I2C3_IPG_CLK:
  69. resource = SC_R_I2C_3;
  70. pm_clk = SC_PM_CLK_PER;
  71. break;
  72. case IMX8QXP_SDHC0_IPG_CLK:
  73. case IMX8QXP_SDHC0_CLK:
  74. case IMX8QXP_SDHC0_DIV:
  75. resource = SC_R_SDHC_0;
  76. pm_clk = SC_PM_CLK_PER;
  77. break;
  78. case IMX8QXP_SDHC1_IPG_CLK:
  79. case IMX8QXP_SDHC1_CLK:
  80. case IMX8QXP_SDHC1_DIV:
  81. resource = SC_R_SDHC_1;
  82. pm_clk = SC_PM_CLK_PER;
  83. break;
  84. case IMX8QXP_UART0_IPG_CLK:
  85. case IMX8QXP_UART0_CLK:
  86. resource = SC_R_UART_0;
  87. pm_clk = SC_PM_CLK_PER;
  88. break;
  89. case IMX8QXP_UART1_CLK:
  90. resource = SC_R_UART_1;
  91. pm_clk = SC_PM_CLK_PER;
  92. break;
  93. case IMX8QXP_UART2_CLK:
  94. resource = SC_R_UART_2;
  95. pm_clk = SC_PM_CLK_PER;
  96. break;
  97. case IMX8QXP_UART3_CLK:
  98. resource = SC_R_UART_3;
  99. pm_clk = SC_PM_CLK_PER;
  100. break;
  101. case IMX8QXP_ENET0_IPG_CLK:
  102. case IMX8QXP_ENET0_AHB_CLK:
  103. case IMX8QXP_ENET0_REF_DIV:
  104. case IMX8QXP_ENET0_PTP_CLK:
  105. resource = SC_R_ENET_0;
  106. pm_clk = SC_PM_CLK_PER;
  107. break;
  108. case IMX8QXP_ENET1_IPG_CLK:
  109. case IMX8QXP_ENET1_AHB_CLK:
  110. case IMX8QXP_ENET1_REF_DIV:
  111. case IMX8QXP_ENET1_PTP_CLK:
  112. resource = SC_R_ENET_1;
  113. pm_clk = SC_PM_CLK_PER;
  114. break;
  115. default:
  116. if (clk->id < IMX8QXP_UART0_IPG_CLK ||
  117. clk->id >= IMX8QXP_CLK_END) {
  118. printf("%s(Invalid clk ID #%lu)\n",
  119. __func__, clk->id);
  120. return -EINVAL;
  121. }
  122. return -ENOTSUPP;
  123. };
  124. ret = sc_pm_get_clock_rate(-1, resource, pm_clk,
  125. (sc_pm_clock_rate_t *)&rate);
  126. if (ret) {
  127. printf("%s err %d\n", __func__, ret);
  128. return ret;
  129. }
  130. return rate;
  131. }
  132. ulong imx8_clk_set_rate(struct clk *clk, unsigned long rate)
  133. {
  134. sc_pm_clk_t pm_clk;
  135. u32 new_rate = rate;
  136. u16 resource;
  137. int ret;
  138. debug("%s(#%lu), rate: %lu\n", __func__, clk->id, rate);
  139. switch (clk->id) {
  140. case IMX8QXP_I2C0_CLK:
  141. case IMX8QXP_I2C0_IPG_CLK:
  142. resource = SC_R_I2C_0;
  143. pm_clk = SC_PM_CLK_PER;
  144. break;
  145. case IMX8QXP_I2C1_CLK:
  146. case IMX8QXP_I2C1_IPG_CLK:
  147. resource = SC_R_I2C_1;
  148. pm_clk = SC_PM_CLK_PER;
  149. break;
  150. case IMX8QXP_I2C2_CLK:
  151. case IMX8QXP_I2C2_IPG_CLK:
  152. resource = SC_R_I2C_2;
  153. pm_clk = SC_PM_CLK_PER;
  154. break;
  155. case IMX8QXP_I2C3_CLK:
  156. case IMX8QXP_I2C3_IPG_CLK:
  157. resource = SC_R_I2C_3;
  158. pm_clk = SC_PM_CLK_PER;
  159. break;
  160. case IMX8QXP_UART0_CLK:
  161. resource = SC_R_UART_0;
  162. pm_clk = SC_PM_CLK_PER;
  163. break;
  164. case IMX8QXP_UART1_CLK:
  165. resource = SC_R_UART_1;
  166. pm_clk = SC_PM_CLK_PER;
  167. break;
  168. case IMX8QXP_UART2_CLK:
  169. resource = SC_R_UART_2;
  170. pm_clk = SC_PM_CLK_PER;
  171. break;
  172. case IMX8QXP_UART3_CLK:
  173. resource = SC_R_UART_3;
  174. pm_clk = SC_PM_CLK_PER;
  175. break;
  176. case IMX8QXP_SDHC0_IPG_CLK:
  177. case IMX8QXP_SDHC0_CLK:
  178. case IMX8QXP_SDHC0_DIV:
  179. resource = SC_R_SDHC_0;
  180. pm_clk = SC_PM_CLK_PER;
  181. break;
  182. case IMX8QXP_SDHC1_SEL:
  183. case IMX8QXP_SDHC0_SEL:
  184. return 0;
  185. case IMX8QXP_SDHC1_IPG_CLK:
  186. case IMX8QXP_SDHC1_CLK:
  187. case IMX8QXP_SDHC1_DIV:
  188. resource = SC_R_SDHC_1;
  189. pm_clk = SC_PM_CLK_PER;
  190. break;
  191. case IMX8QXP_ENET0_IPG_CLK:
  192. case IMX8QXP_ENET0_AHB_CLK:
  193. case IMX8QXP_ENET0_REF_DIV:
  194. case IMX8QXP_ENET0_PTP_CLK:
  195. resource = SC_R_ENET_0;
  196. pm_clk = SC_PM_CLK_PER;
  197. break;
  198. case IMX8QXP_ENET1_IPG_CLK:
  199. case IMX8QXP_ENET1_AHB_CLK:
  200. case IMX8QXP_ENET1_REF_DIV:
  201. case IMX8QXP_ENET1_PTP_CLK:
  202. resource = SC_R_ENET_1;
  203. pm_clk = SC_PM_CLK_PER;
  204. break;
  205. default:
  206. if (clk->id < IMX8QXP_UART0_IPG_CLK ||
  207. clk->id >= IMX8QXP_CLK_END) {
  208. printf("%s(Invalid clk ID #%lu)\n",
  209. __func__, clk->id);
  210. return -EINVAL;
  211. }
  212. return -ENOTSUPP;
  213. };
  214. ret = sc_pm_set_clock_rate(-1, resource, pm_clk, &new_rate);
  215. if (ret) {
  216. printf("%s err %d\n", __func__, ret);
  217. return ret;
  218. }
  219. return new_rate;
  220. }
  221. int __imx8_clk_enable(struct clk *clk, bool enable)
  222. {
  223. sc_pm_clk_t pm_clk;
  224. u16 resource;
  225. int ret;
  226. debug("%s(#%lu)\n", __func__, clk->id);
  227. switch (clk->id) {
  228. case IMX8QXP_I2C0_CLK:
  229. case IMX8QXP_I2C0_IPG_CLK:
  230. resource = SC_R_I2C_0;
  231. pm_clk = SC_PM_CLK_PER;
  232. break;
  233. case IMX8QXP_I2C1_CLK:
  234. case IMX8QXP_I2C1_IPG_CLK:
  235. resource = SC_R_I2C_1;
  236. pm_clk = SC_PM_CLK_PER;
  237. break;
  238. case IMX8QXP_I2C2_CLK:
  239. case IMX8QXP_I2C2_IPG_CLK:
  240. resource = SC_R_I2C_2;
  241. pm_clk = SC_PM_CLK_PER;
  242. break;
  243. case IMX8QXP_I2C3_CLK:
  244. case IMX8QXP_I2C3_IPG_CLK:
  245. resource = SC_R_I2C_3;
  246. pm_clk = SC_PM_CLK_PER;
  247. break;
  248. case IMX8QXP_UART0_CLK:
  249. resource = SC_R_UART_0;
  250. pm_clk = SC_PM_CLK_PER;
  251. break;
  252. case IMX8QXP_UART1_CLK:
  253. resource = SC_R_UART_1;
  254. pm_clk = SC_PM_CLK_PER;
  255. break;
  256. case IMX8QXP_UART2_CLK:
  257. resource = SC_R_UART_2;
  258. pm_clk = SC_PM_CLK_PER;
  259. break;
  260. case IMX8QXP_UART3_CLK:
  261. resource = SC_R_UART_3;
  262. pm_clk = SC_PM_CLK_PER;
  263. break;
  264. case IMX8QXP_SDHC0_IPG_CLK:
  265. case IMX8QXP_SDHC0_CLK:
  266. case IMX8QXP_SDHC0_DIV:
  267. resource = SC_R_SDHC_0;
  268. pm_clk = SC_PM_CLK_PER;
  269. break;
  270. case IMX8QXP_SDHC1_IPG_CLK:
  271. case IMX8QXP_SDHC1_CLK:
  272. case IMX8QXP_SDHC1_DIV:
  273. resource = SC_R_SDHC_1;
  274. pm_clk = SC_PM_CLK_PER;
  275. break;
  276. case IMX8QXP_ENET0_IPG_CLK:
  277. case IMX8QXP_ENET0_AHB_CLK:
  278. case IMX8QXP_ENET0_REF_DIV:
  279. case IMX8QXP_ENET0_PTP_CLK:
  280. resource = SC_R_ENET_0;
  281. pm_clk = SC_PM_CLK_PER;
  282. break;
  283. case IMX8QXP_ENET1_IPG_CLK:
  284. case IMX8QXP_ENET1_AHB_CLK:
  285. case IMX8QXP_ENET1_REF_DIV:
  286. case IMX8QXP_ENET1_PTP_CLK:
  287. resource = SC_R_ENET_1;
  288. pm_clk = SC_PM_CLK_PER;
  289. break;
  290. default:
  291. if (clk->id < IMX8QXP_UART0_IPG_CLK ||
  292. clk->id >= IMX8QXP_CLK_END) {
  293. printf("%s(Invalid clk ID #%lu)\n",
  294. __func__, clk->id);
  295. return -EINVAL;
  296. }
  297. return -ENOTSUPP;
  298. }
  299. ret = sc_pm_clock_enable(-1, resource, pm_clk, enable, 0);
  300. if (ret) {
  301. printf("%s err %d\n", __func__, ret);
  302. return ret;
  303. }
  304. return 0;
  305. }