clk-imx8mp.c 19 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * Copyright 2019 NXP
  4. * Peng Fan <peng.fan@nxp.com>
  5. */
  6. #include <common.h>
  7. #include <clk.h>
  8. #include <clk-uclass.h>
  9. #include <dm.h>
  10. #include <log.h>
  11. #include <asm/arch/clock.h>
  12. #include <asm/arch/imx-regs.h>
  13. #include <dt-bindings/clock/imx8mp-clock.h>
  14. #include "clk.h"
  15. #define PLL_1416X_RATE(_rate, _m, _p, _s) \
  16. { \
  17. .rate = (_rate), \
  18. .mdiv = (_m), \
  19. .pdiv = (_p), \
  20. .sdiv = (_s), \
  21. }
  22. #define PLL_1443X_RATE(_rate, _m, _p, _s, _k) \
  23. { \
  24. .rate = (_rate), \
  25. .mdiv = (_m), \
  26. .pdiv = (_p), \
  27. .sdiv = (_s), \
  28. .kdiv = (_k), \
  29. }
  30. static const struct imx_pll14xx_rate_table imx8mp_pll1416x_tbl[] = {
  31. PLL_1416X_RATE(1800000000U, 225, 3, 0),
  32. PLL_1416X_RATE(1600000000U, 200, 3, 0),
  33. PLL_1416X_RATE(1200000000U, 300, 3, 1),
  34. PLL_1416X_RATE(1000000000U, 250, 3, 1),
  35. PLL_1416X_RATE(800000000U, 200, 3, 1),
  36. PLL_1416X_RATE(750000000U, 250, 2, 2),
  37. PLL_1416X_RATE(700000000U, 350, 3, 2),
  38. PLL_1416X_RATE(600000000U, 300, 3, 2),
  39. };
  40. static const struct imx_pll14xx_rate_table imx8mp_drampll_tbl[] = {
  41. PLL_1443X_RATE(650000000U, 325, 3, 2, 0),
  42. };
  43. static struct imx_pll14xx_clk imx8mp_dram_pll __initdata = {
  44. .type = PLL_1443X,
  45. .rate_table = imx8mp_drampll_tbl,
  46. .rate_count = ARRAY_SIZE(imx8mp_drampll_tbl),
  47. };
  48. static struct imx_pll14xx_clk imx8mp_arm_pll __initdata = {
  49. .type = PLL_1416X,
  50. .rate_table = imx8mp_pll1416x_tbl,
  51. .rate_count = ARRAY_SIZE(imx8mp_pll1416x_tbl),
  52. };
  53. static struct imx_pll14xx_clk imx8mp_sys_pll __initdata = {
  54. .type = PLL_1416X,
  55. .rate_table = imx8mp_pll1416x_tbl,
  56. .rate_count = ARRAY_SIZE(imx8mp_pll1416x_tbl),
  57. };
  58. static const char *pll_ref_sels[] = { "clock-osc-24m", "dummy", "dummy", "dummy", };
  59. static const char *dram_pll_bypass_sels[] = {"dram_pll", "dram_pll_ref_sel", };
  60. static const char *arm_pll_bypass_sels[] = {"arm_pll", "arm_pll_ref_sel", };
  61. static const char *sys_pll1_bypass_sels[] = {"sys_pll1", "sys_pll1_ref_sel", };
  62. static const char *sys_pll2_bypass_sels[] = {"sys_pll2", "sys_pll2_ref_sel", };
  63. static const char *sys_pll3_bypass_sels[] = {"sys_pll3", "sys_pll3_ref_sel", };
  64. static const char *imx8mp_a53_sels[] = {"clock-osc-24m", "arm_pll_out", "sys_pll2_500m",
  65. "sys_pll2_1000m", "sys_pll1_800m", "sys_pll1_400m",
  66. "audio_pll1_out", "sys_pll3_out", };
  67. static const char *imx8mp_main_axi_sels[] = {"clock-osc-24m", "sys_pll2_333m", "sys_pll1_800m",
  68. "sys_pll2_250m", "sys_pll2_1000m", "audio_pll1_out",
  69. "video_pll1_out", "sys_pll1_100m",};
  70. static const char *imx8mp_enet_axi_sels[] = {"clock-osc-24m", "sys_pll1_266m", "sys_pll1_800m",
  71. "sys_pll2_250m", "sys_pll2_200m", "audio_pll1_out",
  72. "video_pll1_out", "sys_pll3_out", };
  73. static const char *imx8mp_nand_usdhc_sels[] = {"clock-osc-24m", "sys_pll1_266m", "sys_pll1_800m",
  74. "sys_pll2_200m", "sys_pll1_133m", "sys_pll3_out",
  75. "sys_pll2_250m", "audio_pll1_out", };
  76. static const char *imx8mp_noc_sels[] = {"clock-osc-24m", "sys_pll1_800m", "sys_pll3_out",
  77. "sys_pll2_1000m", "sys_pll2_500m", "audio_pll1_out",
  78. "video_pll1_out", "audio_pll2_out", };
  79. static const char *imx8mp_noc_io_sels[] = {"clock-osc-24m", "sys_pll1_800m", "sys_pll3_out",
  80. "sys_pll2_1000m", "sys_pll2_500m", "audio_pll1_out",
  81. "video_pll1_out", "audio_pll2_out", };
  82. static const char *imx8mp_ahb_sels[] = {"clock-osc-24m", "sys_pll1_133m", "sys_pll1_800m",
  83. "sys_pll1_400m", "sys_pll2_125m", "sys_pll3_out",
  84. "audio_pll1_out", "video_pll1_out", };
  85. static const char *imx8mp_dram_alt_sels[] = {"clock-osc-24m", "sys_pll1_800m", "sys_pll1_100m",
  86. "sys_pll2_500m", "sys_pll2_1000m", "sys_pll3_out",
  87. "audio_pll1_out", "sys_pll1_266m", };
  88. static const char *imx8mp_dram_apb_sels[] = {"clock-osc-24m", "sys_pll2_200m", "sys_pll1_40m",
  89. "sys_pll1_160m", "sys_pll1_800m", "sys_pll3_out",
  90. "sys_pll2_250m", "audio_pll2_out", };
  91. static const char *imx8mp_i2c5_sels[] = {"clock-osc-24m", "sys_pll1_160m", "sys_pll2_50m",
  92. "sys_pll3_out", "audio_pll1_out", "video_pll1_out",
  93. "audio_pll2_out", "sys_pll1_133m", };
  94. static const char *imx8mp_i2c6_sels[] = {"clock-osc-24m", "sys_pll1_160m", "sys_pll2_50m",
  95. "sys_pll3_out", "audio_pll1_out", "video_pll1_out",
  96. "audio_pll2_out", "sys_pll1_133m", };
  97. static const char *imx8mp_usdhc1_sels[] = {"clock-osc-24m", "sys_pll1_400m", "sys_pll1_800m",
  98. "sys_pll2_500m", "sys_pll3_out", "sys_pll1_266m",
  99. "audio_pll2_out", "sys_pll1_100m", };
  100. static const char *imx8mp_usdhc2_sels[] = {"clock-osc-24m", "sys_pll1_400m", "sys_pll1_800m",
  101. "sys_pll2_500m", "sys_pll3_out", "sys_pll1_266m",
  102. "audio_pll2_out", "sys_pll1_100m", };
  103. static const char *imx8mp_i2c1_sels[] = {"clock-osc-24m", "sys_pll1_160m", "sys_pll2_50m",
  104. "sys_pll3_out", "audio_pll1_out", "video_pll1_out",
  105. "audio_pll2_out", "sys_pll1_133m", };
  106. static const char *imx8mp_i2c2_sels[] = {"clock-osc-24m", "sys_pll1_160m", "sys_pll2_50m",
  107. "sys_pll3_out", "audio_pll1_out", "video_pll1_out",
  108. "audio_pll2_out", "sys_pll1_133m", };
  109. static const char *imx8mp_i2c3_sels[] = {"clock-osc-24m", "sys_pll1_160m", "sys_pll2_50m",
  110. "sys_pll3_out", "audio_pll1_out", "video_pll1_out",
  111. "audio_pll2_out", "sys_pll1_133m", };
  112. static const char *imx8mp_i2c4_sels[] = {"clock-osc-24m", "sys_pll1_160m", "sys_pll2_50m",
  113. "sys_pll3_out", "audio_pll1_out", "video_pll1_out",
  114. "audio_pll2_out", "sys_pll1_133m", };
  115. static const char *imx8mp_uart1_sels[] = {"clock-osc-24m", "sys_pll1_80m", "sys_pll2_200m",
  116. "sys_pll2_100m", "sys_pll3_out", "clk_ext2",
  117. "clk_ext4", "audio_pll2_out", };
  118. static const char *imx8mp_uart2_sels[] = {"clock-osc-24m", "sys_pll1_80m", "sys_pll2_200m",
  119. "sys_pll2_100m", "sys_pll3_out", "clk_ext2",
  120. "clk_ext3", "audio_pll2_out", };
  121. static const char *imx8mp_uart3_sels[] = {"clock-osc-24m", "sys_pll1_80m", "sys_pll2_200m",
  122. "sys_pll2_100m", "sys_pll3_out", "clk_ext2",
  123. "clk_ext4", "audio_pll2_out", };
  124. static const char *imx8mp_uart4_sels[] = {"clock-osc-24m", "sys_pll1_80m", "sys_pll2_200m",
  125. "sys_pll2_100m", "sys_pll3_out", "clk_ext2",
  126. "clk_ext3", "audio_pll2_out", };
  127. static const char *imx8mp_gic_sels[] = {"clock-osc-24m", "sys_pll2_200m", "sys_pll1_40m",
  128. "sys_pll2_100m", "sys_pll1_800m",
  129. "sys_pll2_500m", "clk_ext4", "audio_pll2_out" };
  130. static const char *imx8mp_wdog_sels[] = {"clock-osc-24m", "sys_pll1_133m", "sys_pll1_160m",
  131. "vpu_pll_out", "sys_pll2_125m", "sys_pll3_out",
  132. "sys_pll1_80m", "sys_pll2_166m" };
  133. static const char *imx8mp_qspi_sels[] = {"clock-osc-24m", "sys_pll1_400m", "sys_pll2_333m",
  134. "sys_pll2_500m", "audio_pll2_out", "sys_pll1_266m",
  135. "sys_pll3_out", "sys_pll1_100m", };
  136. static const char *imx8mp_usdhc3_sels[] = {"clock-osc-24m", "sys_pll1_400m", "sys_pll1_800m",
  137. "sys_pll2_500m", "sys_pll3_out", "sys_pll1_266m",
  138. "audio_pll2_out", "sys_pll1_100m", };
  139. static const char *imx8mp_enet_ref_sels[] = {"clock-osc-24m", "sys_pll2_125m", "sys_pll2_50m",
  140. "sys_pll2_100m", "sys_pll1_160m", "audio_pll1_out",
  141. "video_pll1_out", "clk_ext4", };
  142. static const char *imx8mp_enet_timer_sels[] = {"clock-osc-24m", "sys_pll2_100m", "audio_pll1_out",
  143. "clk_ext1", "clk_ext2", "clk_ext3",
  144. "clk_ext4", "video_pll1_out", };
  145. static const char *imx8mp_enet_phy_ref_sels[] = {"clock-osc-24m", "sys_pll2_50m", "sys_pll2_125m",
  146. "sys_pll2_200m", "sys_pll2_500m", "audio_pll1_out",
  147. "video_pll1_out", "audio_pll2_out", };
  148. static const char *imx8mp_dram_core_sels[] = {"dram_pll_out", "dram_alt_root", };
  149. static ulong imx8mp_clk_get_rate(struct clk *clk)
  150. {
  151. struct clk *c;
  152. int ret;
  153. debug("%s(#%lu)\n", __func__, clk->id);
  154. ret = clk_get_by_id(clk->id, &c);
  155. if (ret)
  156. return ret;
  157. return clk_get_rate(c);
  158. }
  159. static ulong imx8mp_clk_set_rate(struct clk *clk, unsigned long rate)
  160. {
  161. struct clk *c;
  162. int ret;
  163. debug("%s(#%lu), rate: %lu\n", __func__, clk->id, rate);
  164. ret = clk_get_by_id(clk->id, &c);
  165. if (ret)
  166. return ret;
  167. return clk_set_rate(c, rate);
  168. }
  169. static int __imx8mp_clk_enable(struct clk *clk, bool enable)
  170. {
  171. struct clk *c;
  172. int ret;
  173. debug("%s(#%lu) en: %d\n", __func__, clk->id, enable);
  174. ret = clk_get_by_id(clk->id, &c);
  175. if (ret)
  176. return ret;
  177. if (enable)
  178. ret = clk_enable(c);
  179. else
  180. ret = clk_disable(c);
  181. return ret;
  182. }
  183. static int imx8mp_clk_disable(struct clk *clk)
  184. {
  185. return __imx8mp_clk_enable(clk, 0);
  186. }
  187. static int imx8mp_clk_enable(struct clk *clk)
  188. {
  189. return __imx8mp_clk_enable(clk, 1);
  190. }
  191. static int imx8mp_clk_set_parent(struct clk *clk, struct clk *parent)
  192. {
  193. struct clk *c, *cp;
  194. int ret;
  195. debug("%s(#%lu), parent: %lu\n", __func__, clk->id, parent->id);
  196. ret = clk_get_by_id(clk->id, &c);
  197. if (ret)
  198. return ret;
  199. ret = clk_get_by_id(parent->id, &cp);
  200. if (ret)
  201. return ret;
  202. ret = clk_set_parent(c, cp);
  203. c->dev->parent = cp->dev;
  204. return ret;
  205. }
  206. static struct clk_ops imx8mp_clk_ops = {
  207. .set_rate = imx8mp_clk_set_rate,
  208. .get_rate = imx8mp_clk_get_rate,
  209. .enable = imx8mp_clk_enable,
  210. .disable = imx8mp_clk_disable,
  211. .set_parent = imx8mp_clk_set_parent,
  212. };
  213. static int imx8mp_clk_probe(struct udevice *dev)
  214. {
  215. void __iomem *base;
  216. base = (void *)ANATOP_BASE_ADDR;
  217. clk_dm(IMX8MP_DRAM_PLL_REF_SEL, imx_clk_mux("dram_pll_ref_sel", base + 0x50, 0, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels)));
  218. clk_dm(IMX8MP_ARM_PLL_REF_SEL, imx_clk_mux("arm_pll_ref_sel", base + 0x84, 0, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels)));
  219. clk_dm(IMX8MP_SYS_PLL1_REF_SEL, imx_clk_mux("sys_pll1_ref_sel", base + 0x94, 0, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels)));
  220. clk_dm(IMX8MP_SYS_PLL2_REF_SEL, imx_clk_mux("sys_pll2_ref_sel", base + 0x104, 0, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels)));
  221. clk_dm(IMX8MP_SYS_PLL3_REF_SEL, imx_clk_mux("sys_pll3_ref_sel", base + 0x114, 0, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels)));
  222. clk_dm(IMX8MP_DRAM_PLL, imx_clk_pll14xx("dram_pll", "dram_pll_ref_sel", base + 0x50, &imx8mp_dram_pll));
  223. clk_dm(IMX8MP_ARM_PLL, imx_clk_pll14xx("arm_pll", "arm_pll_ref_sel", base + 0x84, &imx8mp_arm_pll));
  224. clk_dm(IMX8MP_SYS_PLL1, imx_clk_pll14xx("sys_pll1", "sys_pll1_ref_sel", base + 0x94, &imx8mp_sys_pll));
  225. clk_dm(IMX8MP_SYS_PLL2, imx_clk_pll14xx("sys_pll2", "sys_pll2_ref_sel", base + 0x104, &imx8mp_sys_pll));
  226. clk_dm(IMX8MP_SYS_PLL3, imx_clk_pll14xx("sys_pll3", "sys_pll3_ref_sel", base + 0x114, &imx8mp_sys_pll));
  227. clk_dm(IMX8MP_DRAM_PLL_BYPASS, imx_clk_mux_flags("dram_pll_bypass", base + 0x50, 4, 1, dram_pll_bypass_sels, ARRAY_SIZE(dram_pll_bypass_sels), CLK_SET_RATE_PARENT));
  228. clk_dm(IMX8MP_ARM_PLL_BYPASS, imx_clk_mux_flags("arm_pll_bypass", base + 0x84, 4, 1, arm_pll_bypass_sels, ARRAY_SIZE(arm_pll_bypass_sels), CLK_SET_RATE_PARENT));
  229. clk_dm(IMX8MP_SYS_PLL1_BYPASS, imx_clk_mux_flags("sys_pll1_bypass", base + 0x94, 4, 1, sys_pll1_bypass_sels, ARRAY_SIZE(sys_pll1_bypass_sels), CLK_SET_RATE_PARENT));
  230. clk_dm(IMX8MP_SYS_PLL2_BYPASS, imx_clk_mux_flags("sys_pll2_bypass", base + 0x104, 4, 1, sys_pll2_bypass_sels, ARRAY_SIZE(sys_pll2_bypass_sels), CLK_SET_RATE_PARENT));
  231. clk_dm(IMX8MP_SYS_PLL3_BYPASS, imx_clk_mux_flags("sys_pll3_bypass", base + 0x114, 4, 1, sys_pll3_bypass_sels, ARRAY_SIZE(sys_pll3_bypass_sels), CLK_SET_RATE_PARENT));
  232. clk_dm(IMX8MP_DRAM_PLL_OUT, imx_clk_gate("dram_pll_out", "dram_pll_bypass", base + 0x50, 13));
  233. clk_dm(IMX8MP_ARM_PLL_OUT, imx_clk_gate("arm_pll_out", "arm_pll_bypass", base + 0x84, 11));
  234. clk_dm(IMX8MP_SYS_PLL1_OUT, imx_clk_gate("sys_pll1_out", "sys_pll1_bypass", base + 0x94, 11));
  235. clk_dm(IMX8MP_SYS_PLL2_OUT, imx_clk_gate("sys_pll2_out", "sys_pll2_bypass", base + 0x104, 11));
  236. clk_dm(IMX8MP_SYS_PLL3_OUT, imx_clk_gate("sys_pll3_out", "sys_pll3_bypass", base + 0x114, 11));
  237. clk_dm(IMX8MP_SYS_PLL1_40M, imx_clk_fixed_factor("sys_pll1_40m", "sys_pll1_out", 1, 20));
  238. clk_dm(IMX8MP_SYS_PLL1_80M, imx_clk_fixed_factor("sys_pll1_80m", "sys_pll1_out", 1, 10));
  239. clk_dm(IMX8MP_SYS_PLL1_100M, imx_clk_fixed_factor("sys_pll1_100m", "sys_pll1_out", 1, 8));
  240. clk_dm(IMX8MP_SYS_PLL1_133M, imx_clk_fixed_factor("sys_pll1_133m", "sys_pll1_out", 1, 6));
  241. clk_dm(IMX8MP_SYS_PLL1_160M, imx_clk_fixed_factor("sys_pll1_160m", "sys_pll1_out", 1, 5));
  242. clk_dm(IMX8MP_SYS_PLL1_200M, imx_clk_fixed_factor("sys_pll1_200m", "sys_pll1_out", 1, 4));
  243. clk_dm(IMX8MP_SYS_PLL1_266M, imx_clk_fixed_factor("sys_pll1_266m", "sys_pll1_out", 1, 3));
  244. clk_dm(IMX8MP_SYS_PLL1_400M, imx_clk_fixed_factor("sys_pll1_400m", "sys_pll1_out", 1, 2));
  245. clk_dm(IMX8MP_SYS_PLL1_800M, imx_clk_fixed_factor("sys_pll1_800m", "sys_pll1_out", 1, 1));
  246. clk_dm(IMX8MP_SYS_PLL2_50M, imx_clk_fixed_factor("sys_pll2_50m", "sys_pll2_out", 1, 20));
  247. clk_dm(IMX8MP_SYS_PLL2_100M, imx_clk_fixed_factor("sys_pll2_100m", "sys_pll2_out", 1, 10));
  248. clk_dm(IMX8MP_SYS_PLL2_125M, imx_clk_fixed_factor("sys_pll2_125m", "sys_pll2_out", 1, 8));
  249. clk_dm(IMX8MP_SYS_PLL2_166M, imx_clk_fixed_factor("sys_pll2_166m", "sys_pll2_out", 1, 6));
  250. clk_dm(IMX8MP_SYS_PLL2_200M, imx_clk_fixed_factor("sys_pll2_200m", "sys_pll2_out", 1, 5));
  251. clk_dm(IMX8MP_SYS_PLL2_250M, imx_clk_fixed_factor("sys_pll2_250m", "sys_pll2_out", 1, 4));
  252. clk_dm(IMX8MP_SYS_PLL2_333M, imx_clk_fixed_factor("sys_pll2_333m", "sys_pll2_out", 1, 3));
  253. clk_dm(IMX8MP_SYS_PLL2_500M, imx_clk_fixed_factor("sys_pll2_500m", "sys_pll2_out", 1, 2));
  254. clk_dm(IMX8MP_SYS_PLL2_1000M, imx_clk_fixed_factor("sys_pll2_1000m", "sys_pll2_out", 1, 1));
  255. base = dev_read_addr_ptr(dev);
  256. if (!base)
  257. return -EINVAL;
  258. clk_dm(IMX8MP_CLK_A53_SRC, imx_clk_mux2("arm_a53_src", base + 0x8000, 24, 3, imx8mp_a53_sels, ARRAY_SIZE(imx8mp_a53_sels)));
  259. clk_dm(IMX8MP_CLK_A53_CG, imx_clk_gate3("arm_a53_cg", "arm_a53_src", base + 0x8000, 28));
  260. clk_dm(IMX8MP_CLK_A53_DIV, imx_clk_divider2("arm_a53_div", "arm_a53_cg", base + 0x8000, 0, 3));
  261. clk_dm(IMX8MP_CLK_MAIN_AXI, imx8m_clk_composite_critical("main_axi", imx8mp_main_axi_sels, base + 0x8800));
  262. clk_dm(IMX8MP_CLK_ENET_AXI, imx8m_clk_composite_critical("enet_axi", imx8mp_enet_axi_sels, base + 0x8880));
  263. clk_dm(IMX8MP_CLK_NAND_USDHC_BUS, imx8m_clk_composite_critical("nand_usdhc_bus", imx8mp_nand_usdhc_sels, base + 0x8900));
  264. clk_dm(IMX8MP_CLK_NOC, imx8m_clk_composite_critical("noc", imx8mp_noc_sels, base + 0x8d00));
  265. clk_dm(IMX8MP_CLK_NOC_IO, imx8m_clk_composite_critical("noc_io", imx8mp_noc_io_sels, base + 0x8d80));
  266. clk_dm(IMX8MP_CLK_AHB, imx8m_clk_composite_critical("ahb_root", imx8mp_ahb_sels, base + 0x9000));
  267. clk_dm(IMX8MP_CLK_IPG_ROOT, imx_clk_divider2("ipg_root", "ahb_root", base + 0x9080, 0, 1));
  268. clk_dm(IMX8MP_CLK_DRAM_ALT, imx8m_clk_composite("dram_alt", imx8mp_dram_alt_sels, base + 0xa000));
  269. clk_dm(IMX8MP_CLK_DRAM_APB, imx8m_clk_composite_critical("dram_apb", imx8mp_dram_apb_sels, base + 0xa080));
  270. clk_dm(IMX8MP_CLK_I2C5, imx8m_clk_composite("i2c5", imx8mp_i2c5_sels, base + 0xa480));
  271. clk_dm(IMX8MP_CLK_I2C6, imx8m_clk_composite("i2c6", imx8mp_i2c6_sels, base + 0xa500));
  272. clk_dm(IMX8MP_CLK_ENET_REF, imx8m_clk_composite("enet_ref", imx8mp_enet_ref_sels, base + 0xa980));
  273. clk_dm(IMX8MP_CLK_ENET_TIMER, imx8m_clk_composite("enet_timer", imx8mp_enet_timer_sels, base + 0xaa00));
  274. clk_dm(IMX8MP_CLK_ENET_PHY_REF, imx8m_clk_composite("enet_phy_ref", imx8mp_enet_phy_ref_sels, base + 0xaa80));
  275. clk_dm(IMX8MP_CLK_QSPI, imx8m_clk_composite("qspi", imx8mp_qspi_sels, base + 0xab80));
  276. clk_dm(IMX8MP_CLK_USDHC1, imx8m_clk_composite("usdhc1", imx8mp_usdhc1_sels, base + 0xac00));
  277. clk_dm(IMX8MP_CLK_USDHC2, imx8m_clk_composite("usdhc2", imx8mp_usdhc2_sels, base + 0xac80));
  278. clk_dm(IMX8MP_CLK_I2C1, imx8m_clk_composite("i2c1", imx8mp_i2c1_sels, base + 0xad00));
  279. clk_dm(IMX8MP_CLK_I2C2, imx8m_clk_composite("i2c2", imx8mp_i2c2_sels, base + 0xad80));
  280. clk_dm(IMX8MP_CLK_I2C3, imx8m_clk_composite("i2c3", imx8mp_i2c3_sels, base + 0xae00));
  281. clk_dm(IMX8MP_CLK_I2C4, imx8m_clk_composite("i2c4", imx8mp_i2c4_sels, base + 0xae80));
  282. clk_dm(IMX8MP_CLK_UART1, imx8m_clk_composite("uart1", imx8mp_uart1_sels, base + 0xaf00));
  283. clk_dm(IMX8MP_CLK_UART2, imx8m_clk_composite("uart2", imx8mp_uart2_sels, base + 0xaf80));
  284. clk_dm(IMX8MP_CLK_UART3, imx8m_clk_composite("uart3", imx8mp_uart3_sels, base + 0xb000));
  285. clk_dm(IMX8MP_CLK_UART4, imx8m_clk_composite("uart4", imx8mp_uart4_sels, base + 0xb080));
  286. clk_dm(IMX8MP_CLK_GIC, imx8m_clk_composite_critical("gic", imx8mp_gic_sels, base + 0xb200));
  287. clk_dm(IMX8MP_CLK_WDOG, imx8m_clk_composite("wdog", imx8mp_wdog_sels, base + 0xb900));
  288. clk_dm(IMX8MP_CLK_USDHC3, imx8m_clk_composite("usdhc3", imx8mp_usdhc3_sels, base + 0xbc80));
  289. clk_dm(IMX8MP_CLK_DRAM_ALT_ROOT, imx_clk_fixed_factor("dram_alt_root", "dram_alt", 1, 4));
  290. clk_dm(IMX8MP_CLK_DRAM_CORE, imx_clk_mux2_flags("dram_core_clk", base + 0x9800, 24, 1, imx8mp_dram_core_sels, ARRAY_SIZE(imx8mp_dram_core_sels), CLK_IS_CRITICAL));
  291. clk_dm(IMX8MP_CLK_DRAM1_ROOT, imx_clk_gate4_flags("dram1_root_clk", "dram_core_clk", base + 0x4050, 0, CLK_IS_CRITICAL));
  292. clk_dm(IMX8MP_CLK_ENET1_ROOT, imx_clk_gate4("enet1_root_clk", "enet_axi", base + 0x40a0, 0));
  293. clk_dm(IMX8MP_CLK_GPIO1_ROOT, imx_clk_gate4("gpio1_root_clk", "ipg_root", base + 0x40b0, 0));
  294. clk_dm(IMX8MP_CLK_GPIO2_ROOT, imx_clk_gate4("gpio2_root_clk", "ipg_root", base + 0x40c0, 0));
  295. clk_dm(IMX8MP_CLK_GPIO3_ROOT, imx_clk_gate4("gpio3_root_clk", "ipg_root", base + 0x40d0, 0));
  296. clk_dm(IMX8MP_CLK_GPIO4_ROOT, imx_clk_gate4("gpio4_root_clk", "ipg_root", base + 0x40e0, 0));
  297. clk_dm(IMX8MP_CLK_GPIO5_ROOT, imx_clk_gate4("gpio5_root_clk", "ipg_root", base + 0x40f0, 0));
  298. clk_dm(IMX8MP_CLK_I2C1_ROOT, imx_clk_gate4("i2c1_root_clk", "i2c1", base + 0x4170, 0));
  299. clk_dm(IMX8MP_CLK_I2C2_ROOT, imx_clk_gate4("i2c2_root_clk", "i2c2", base + 0x4180, 0));
  300. clk_dm(IMX8MP_CLK_I2C3_ROOT, imx_clk_gate4("i2c3_root_clk", "i2c3", base + 0x4190, 0));
  301. clk_dm(IMX8MP_CLK_I2C4_ROOT, imx_clk_gate4("i2c4_root_clk", "i2c4", base + 0x41a0, 0));
  302. clk_dm(IMX8MP_CLK_QSPI_ROOT, imx_clk_gate4("qspi_root_clk", "qspi", base + 0x42f0, 0));
  303. clk_dm(IMX8MP_CLK_I2C5_ROOT, imx_clk_gate2("i2c5_root_clk", "i2c5", base + 0x4330, 0));
  304. clk_dm(IMX8MP_CLK_I2C6_ROOT, imx_clk_gate2("i2c6_root_clk", "i2c6", base + 0x4340, 0));
  305. clk_dm(IMX8MP_CLK_SIM_ENET_ROOT, imx_clk_gate4("sim_enet_root_clk", "enet_axi", base + 0x4400, 0));
  306. clk_dm(IMX8MP_CLK_UART1_ROOT, imx_clk_gate4("uart1_root_clk", "uart1", base + 0x4490, 0));
  307. clk_dm(IMX8MP_CLK_UART2_ROOT, imx_clk_gate4("uart2_root_clk", "uart2", base + 0x44a0, 0));
  308. clk_dm(IMX8MP_CLK_UART3_ROOT, imx_clk_gate4("uart3_root_clk", "uart3", base + 0x44b0, 0));
  309. clk_dm(IMX8MP_CLK_UART4_ROOT, imx_clk_gate4("uart4_root_clk", "uart4", base + 0x44c0, 0));
  310. clk_dm(IMX8MP_CLK_USDHC1_ROOT, imx_clk_gate4("usdhc1_root_clk", "usdhc1", base + 0x4510, 0));
  311. clk_dm(IMX8MP_CLK_USDHC2_ROOT, imx_clk_gate4("usdhc2_root_clk", "usdhc2", base + 0x4520, 0));
  312. clk_dm(IMX8MP_CLK_WDOG1_ROOT, imx_clk_gate4("wdog1_root_clk", "wdog", base + 0x4530, 0));
  313. clk_dm(IMX8MP_CLK_WDOG2_ROOT, imx_clk_gate4("wdog2_root_clk", "wdog", base + 0x4540, 0));
  314. clk_dm(IMX8MP_CLK_WDOG3_ROOT, imx_clk_gate4("wdog3_root_clk", "wdog", base + 0x4550, 0));
  315. clk_dm(IMX8MP_CLK_USDHC3_ROOT, imx_clk_gate4("usdhc3_root_clk", "usdhc3", base + 0x45e0, 0));
  316. return 0;
  317. }
  318. static const struct udevice_id imx8mp_clk_ids[] = {
  319. { .compatible = "fsl,imx8mp-ccm" },
  320. { },
  321. };
  322. U_BOOT_DRIVER(imx8mp_clk) = {
  323. .name = "clk_imx8mp",
  324. .id = UCLASS_CLK,
  325. .of_match = imx8mp_clk_ids,
  326. .ops = &imx8mp_clk_ops,
  327. .probe = imx8mp_clk_probe,
  328. .flags = DM_FLAG_PRE_RELOC,
  329. };