clk-imx8mn.c 16 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * Copyright 2019 NXP
  4. * Peng Fan <peng.fan@nxp.com>
  5. */
  6. #include <common.h>
  7. #include <clk.h>
  8. #include <clk-uclass.h>
  9. #include <dm.h>
  10. #include <log.h>
  11. #include <asm/arch/clock.h>
  12. #include <asm/arch/imx-regs.h>
  13. #include <dt-bindings/clock/imx8mn-clock.h>
  14. #include "clk.h"
  15. #define PLL_1416X_RATE(_rate, _m, _p, _s) \
  16. { \
  17. .rate = (_rate), \
  18. .mdiv = (_m), \
  19. .pdiv = (_p), \
  20. .sdiv = (_s), \
  21. }
  22. #define PLL_1443X_RATE(_rate, _m, _p, _s, _k) \
  23. { \
  24. .rate = (_rate), \
  25. .mdiv = (_m), \
  26. .pdiv = (_p), \
  27. .sdiv = (_s), \
  28. .kdiv = (_k), \
  29. }
  30. static const struct imx_pll14xx_rate_table imx8mn_pll1416x_tbl[] = {
  31. PLL_1416X_RATE(1800000000U, 225, 3, 0),
  32. PLL_1416X_RATE(1600000000U, 200, 3, 0),
  33. PLL_1416X_RATE(1200000000U, 300, 3, 1),
  34. PLL_1416X_RATE(1000000000U, 250, 3, 1),
  35. PLL_1416X_RATE(800000000U, 200, 3, 1),
  36. PLL_1416X_RATE(750000000U, 250, 2, 2),
  37. PLL_1416X_RATE(700000000U, 350, 3, 2),
  38. PLL_1416X_RATE(600000000U, 300, 3, 2),
  39. };
  40. static const struct imx_pll14xx_rate_table imx8mn_drampll_tbl[] = {
  41. PLL_1443X_RATE(650000000U, 325, 3, 2, 0),
  42. };
  43. static struct imx_pll14xx_clk imx8mn_dram_pll __initdata = {
  44. .type = PLL_1443X,
  45. .rate_table = imx8mn_drampll_tbl,
  46. .rate_count = ARRAY_SIZE(imx8mn_drampll_tbl),
  47. };
  48. static struct imx_pll14xx_clk imx8mn_arm_pll __initdata = {
  49. .type = PLL_1416X,
  50. .rate_table = imx8mn_pll1416x_tbl,
  51. .rate_count = ARRAY_SIZE(imx8mn_pll1416x_tbl),
  52. };
  53. static struct imx_pll14xx_clk imx8mn_sys_pll __initdata = {
  54. .type = PLL_1416X,
  55. .rate_table = imx8mn_pll1416x_tbl,
  56. .rate_count = ARRAY_SIZE(imx8mn_pll1416x_tbl),
  57. };
  58. static const char *pll_ref_sels[] = { "clock-osc-24m", "dummy", "dummy", "dummy", };
  59. static const char *dram_pll_bypass_sels[] = {"dram_pll", "dram_pll_ref_sel", };
  60. static const char *arm_pll_bypass_sels[] = {"arm_pll", "arm_pll_ref_sel", };
  61. static const char *sys_pll1_bypass_sels[] = {"sys_pll1", "sys_pll1_ref_sel", };
  62. static const char *sys_pll2_bypass_sels[] = {"sys_pll2", "sys_pll2_ref_sel", };
  63. static const char *sys_pll3_bypass_sels[] = {"sys_pll3", "sys_pll3_ref_sel", };
  64. static const char *imx8mn_a53_sels[] = {"clock-osc-24m", "arm_pll_out", "sys_pll2_500m", "sys_pll2_1000m",
  65. "sys_pll1_800m", "sys_pll1_400m", "audio_pll1_out", "sys_pll3_out", };
  66. static const char *imx8mn_ahb_sels[] = {"clock-osc-24m", "sys_pll1_133m", "sys_pll1_800m", "sys_pll1_400m",
  67. "sys_pll2_125m", "sys_pll3_out", "audio_pll1_out", "video_pll1_out", };
  68. static const char *imx8mn_enet_axi_sels[] = {"clock-osc-24m", "sys_pll1_266m", "sys_pll1_800m", "sys_pll2_250m",
  69. "sys_pll2_200m", "audio_pll1_out", "video_pll1_out", "sys_pll3_out", };
  70. #ifndef CONFIG_SPL_BUILD
  71. static const char *imx8mn_enet_ref_sels[] = {"clock-osc-24m", "sys_pll2_125m", "sys_pll2_50m", "sys_pll2_100m",
  72. "sys_pll1_160m", "audio_pll1_out", "video_pll1_out", "clk_ext4", };
  73. static const char *imx8mn_enet_timer_sels[] = {"clock-osc-24m", "sys_pll2_100m", "audio_pll1_out", "clk_ext1", "clk_ext2",
  74. "clk_ext3", "clk_ext4", "video_pll1_out", };
  75. static const char *imx8mn_enet_phy_sels[] = {"clock-osc-24m", "sys_pll2_50m", "sys_pll2_125m", "sys_pll2_200m",
  76. "sys_pll2_500m", "video_pll1_out", "audio_pll2_out", };
  77. #endif
  78. static const char *imx8mn_nand_usdhc_sels[] = {"clock-osc-24m", "sys_pll1_266m", "sys_pll1_800m", "sys_pll2_200m",
  79. "sys_pll1_133m", "sys_pll3_out", "sys_pll2_250m", "audio_pll1_out", };
  80. static const char * const imx8mn_usb_bus_sels[] = {"clock-osc-24m", "sys_pll2_500m", "sys_pll1_800m",
  81. "sys_pll2_100m", "sys_pll2_200m", "clk_ext2",
  82. "clk_ext4", "audio_pll2_out", };
  83. static const char *imx8mn_usdhc1_sels[] = {"clock-osc-24m", "sys_pll1_400m", "sys_pll1_800m", "sys_pll2_500m",
  84. "sys_pll3_out", "sys_pll1_266m", "audio_pll2_out", "sys_pll1_100m", };
  85. static const char *imx8mn_usdhc2_sels[] = {"clock-osc-24m", "sys_pll1_400m", "sys_pll1_800m", "sys_pll2_500m",
  86. "sys_pll3_out", "sys_pll1_266m", "audio_pll2_out", "sys_pll1_100m", };
  87. static const char *imx8mn_i2c1_sels[] = {"clock-osc-24m", "sys_pll1_160m", "sys_pll2_50m", "sys_pll3_out", "audio_pll1_out",
  88. "video_pll1_out", "audio_pll2_out", "sys_pll1_133m", };
  89. static const char *imx8mn_i2c2_sels[] = {"clock-osc-24m", "sys_pll1_160m", "sys_pll2_50m", "sys_pll3_out", "audio_pll1_out",
  90. "video_pll1_out", "audio_pll2_out", "sys_pll1_133m", };
  91. static const char *imx8mn_i2c3_sels[] = {"clock-osc-24m", "sys_pll1_160m", "sys_pll2_50m", "sys_pll3_out", "audio_pll1_out",
  92. "video_pll1_out", "audio_pll2_out", "sys_pll1_133m", };
  93. static const char *imx8mn_i2c4_sels[] = {"clock-osc-24m", "sys_pll1_160m", "sys_pll2_50m", "sys_pll3_out", "audio_pll1_out",
  94. "video_pll1_out", "audio_pll2_out", "sys_pll1_133m", };
  95. static const char *imx8mn_wdog_sels[] = {"clock-osc-24m", "sys_pll1_133m", "sys_pll1_160m", "vpu_pll_out",
  96. "sys_pll2_125m", "sys_pll3_out", "sys_pll1_80m", "sys_pll2_166m", };
  97. static const char *imx8mn_usdhc3_sels[] = {"clock-osc-24m", "sys_pll1_400m", "sys_pll1_800m", "sys_pll2_500m",
  98. "sys_pll3_out", "sys_pll1_266m", "audio_pll2_clk", "sys_pll1_100m", };
  99. static const char *imx8mn_qspi_sels[] = {"clock-osc-24m", "sys_pll1_400m", "sys_pll2_333m", "sys_pll2_500m",
  100. "audio_pll2_out", "sys_pll1_266m", "sys_pll3_out", "sys_pll1_100m", };
  101. static const char * const imx8mn_usb_core_sels[] = {"clock-osc-24m", "sys_pll1_100m", "sys_pll1_40m",
  102. "sys_pll2_100m", "sys_pll2_200m", "clk_ext2",
  103. "clk_ext3", "audio_pll2_out", };
  104. static const char * const imx8mn_usb_phy_sels[] = {"clock-osc-24m", "sys_pll1_100m", "sys_pll1_40m",
  105. "sys_pll2_100m", "sys_pll2_200m", "clk_ext2",
  106. "clk_ext3", "audio_pll2_out", };
  107. static ulong imx8mn_clk_get_rate(struct clk *clk)
  108. {
  109. struct clk *c;
  110. int ret;
  111. debug("%s(#%lu)\n", __func__, clk->id);
  112. ret = clk_get_by_id(clk->id, &c);
  113. if (ret)
  114. return ret;
  115. return clk_get_rate(c);
  116. }
  117. static ulong imx8mn_clk_set_rate(struct clk *clk, unsigned long rate)
  118. {
  119. struct clk *c;
  120. int ret;
  121. debug("%s(#%lu), rate: %lu\n", __func__, clk->id, rate);
  122. ret = clk_get_by_id(clk->id, &c);
  123. if (ret)
  124. return ret;
  125. return clk_set_rate(c, rate);
  126. }
  127. static int __imx8mn_clk_enable(struct clk *clk, bool enable)
  128. {
  129. struct clk *c;
  130. int ret;
  131. debug("%s(#%lu) en: %d\n", __func__, clk->id, enable);
  132. ret = clk_get_by_id(clk->id, &c);
  133. if (ret)
  134. return ret;
  135. if (enable)
  136. ret = clk_enable(c);
  137. else
  138. ret = clk_disable(c);
  139. return ret;
  140. }
  141. static int imx8mn_clk_disable(struct clk *clk)
  142. {
  143. return __imx8mn_clk_enable(clk, 0);
  144. }
  145. static int imx8mn_clk_enable(struct clk *clk)
  146. {
  147. return __imx8mn_clk_enable(clk, 1);
  148. }
  149. static int imx8mn_clk_set_parent(struct clk *clk, struct clk *parent)
  150. {
  151. struct clk *c, *cp;
  152. int ret;
  153. debug("%s(#%lu), parent: %lu\n", __func__, clk->id, parent->id);
  154. ret = clk_get_by_id(clk->id, &c);
  155. if (ret)
  156. return ret;
  157. ret = clk_get_by_id(parent->id, &cp);
  158. if (ret)
  159. return ret;
  160. ret = clk_set_parent(c, cp);
  161. c->dev->parent = cp->dev;
  162. return ret;
  163. }
  164. static struct clk_ops imx8mn_clk_ops = {
  165. .set_rate = imx8mn_clk_set_rate,
  166. .get_rate = imx8mn_clk_get_rate,
  167. .enable = imx8mn_clk_enable,
  168. .disable = imx8mn_clk_disable,
  169. .set_parent = imx8mn_clk_set_parent,
  170. };
  171. static int imx8mn_clk_probe(struct udevice *dev)
  172. {
  173. void __iomem *base;
  174. base = (void *)ANATOP_BASE_ADDR;
  175. clk_dm(IMX8MN_DRAM_PLL_REF_SEL,
  176. imx_clk_mux("dram_pll_ref_sel", base + 0x50, 0, 2,
  177. pll_ref_sels, ARRAY_SIZE(pll_ref_sels)));
  178. clk_dm(IMX8MN_ARM_PLL_REF_SEL,
  179. imx_clk_mux("arm_pll_ref_sel", base + 0x84, 0, 2,
  180. pll_ref_sels, ARRAY_SIZE(pll_ref_sels)));
  181. clk_dm(IMX8MN_SYS_PLL1_REF_SEL,
  182. imx_clk_mux("sys_pll1_ref_sel", base + 0x94, 0, 2,
  183. pll_ref_sels, ARRAY_SIZE(pll_ref_sels)));
  184. clk_dm(IMX8MN_SYS_PLL2_REF_SEL,
  185. imx_clk_mux("sys_pll2_ref_sel", base + 0x104, 0, 2,
  186. pll_ref_sels, ARRAY_SIZE(pll_ref_sels)));
  187. clk_dm(IMX8MN_SYS_PLL3_REF_SEL,
  188. imx_clk_mux("sys_pll3_ref_sel", base + 0x114, 0, 2,
  189. pll_ref_sels, ARRAY_SIZE(pll_ref_sels)));
  190. clk_dm(IMX8MN_DRAM_PLL,
  191. imx_clk_pll14xx("dram_pll", "dram_pll_ref_sel",
  192. base + 0x50, &imx8mn_dram_pll));
  193. clk_dm(IMX8MN_ARM_PLL,
  194. imx_clk_pll14xx("arm_pll", "arm_pll_ref_sel",
  195. base + 0x84, &imx8mn_arm_pll));
  196. clk_dm(IMX8MN_SYS_PLL1,
  197. imx_clk_pll14xx("sys_pll1", "sys_pll1_ref_sel",
  198. base + 0x94, &imx8mn_sys_pll));
  199. clk_dm(IMX8MN_SYS_PLL2,
  200. imx_clk_pll14xx("sys_pll2", "sys_pll2_ref_sel",
  201. base + 0x104, &imx8mn_sys_pll));
  202. clk_dm(IMX8MN_SYS_PLL3,
  203. imx_clk_pll14xx("sys_pll3", "sys_pll3_ref_sel",
  204. base + 0x114, &imx8mn_sys_pll));
  205. /* PLL bypass out */
  206. clk_dm(IMX8MN_DRAM_PLL_BYPASS,
  207. imx_clk_mux_flags("dram_pll_bypass", base + 0x50, 4, 1,
  208. dram_pll_bypass_sels,
  209. ARRAY_SIZE(dram_pll_bypass_sels),
  210. CLK_SET_RATE_PARENT));
  211. clk_dm(IMX8MN_ARM_PLL_BYPASS,
  212. imx_clk_mux_flags("arm_pll_bypass", base + 0x84, 4, 1,
  213. arm_pll_bypass_sels,
  214. ARRAY_SIZE(arm_pll_bypass_sels),
  215. CLK_SET_RATE_PARENT));
  216. clk_dm(IMX8MN_SYS_PLL1_BYPASS,
  217. imx_clk_mux_flags("sys_pll1_bypass", base + 0x94, 4, 1,
  218. sys_pll1_bypass_sels,
  219. ARRAY_SIZE(sys_pll1_bypass_sels),
  220. CLK_SET_RATE_PARENT));
  221. clk_dm(IMX8MN_SYS_PLL2_BYPASS,
  222. imx_clk_mux_flags("sys_pll2_bypass", base + 0x104, 4, 1,
  223. sys_pll2_bypass_sels,
  224. ARRAY_SIZE(sys_pll2_bypass_sels),
  225. CLK_SET_RATE_PARENT));
  226. clk_dm(IMX8MN_SYS_PLL3_BYPASS,
  227. imx_clk_mux_flags("sys_pll3_bypass", base + 0x114, 4, 1,
  228. sys_pll3_bypass_sels,
  229. ARRAY_SIZE(sys_pll3_bypass_sels),
  230. CLK_SET_RATE_PARENT));
  231. /* PLL out gate */
  232. clk_dm(IMX8MN_DRAM_PLL_OUT,
  233. imx_clk_gate("dram_pll_out", "dram_pll_bypass",
  234. base + 0x50, 13));
  235. clk_dm(IMX8MN_ARM_PLL_OUT,
  236. imx_clk_gate("arm_pll_out", "arm_pll_bypass",
  237. base + 0x84, 11));
  238. clk_dm(IMX8MN_SYS_PLL1_OUT,
  239. imx_clk_gate("sys_pll1_out", "sys_pll1_bypass",
  240. base + 0x94, 11));
  241. clk_dm(IMX8MN_SYS_PLL2_OUT,
  242. imx_clk_gate("sys_pll2_out", "sys_pll2_bypass",
  243. base + 0x104, 11));
  244. clk_dm(IMX8MN_SYS_PLL3_OUT,
  245. imx_clk_gate("sys_pll3_out", "sys_pll3_bypass",
  246. base + 0x114, 11));
  247. /* SYS PLL fixed output */
  248. clk_dm(IMX8MN_SYS_PLL1_40M,
  249. imx_clk_fixed_factor("sys_pll1_40m", "sys_pll1_out", 1, 20));
  250. clk_dm(IMX8MN_SYS_PLL1_80M,
  251. imx_clk_fixed_factor("sys_pll1_80m", "sys_pll1_out", 1, 10));
  252. clk_dm(IMX8MN_SYS_PLL1_100M,
  253. imx_clk_fixed_factor("sys_pll1_100m", "sys_pll1_out", 1, 8));
  254. clk_dm(IMX8MN_SYS_PLL1_133M,
  255. imx_clk_fixed_factor("sys_pll1_133m", "sys_pll1_out", 1, 6));
  256. clk_dm(IMX8MN_SYS_PLL1_160M,
  257. imx_clk_fixed_factor("sys_pll1_160m", "sys_pll1_out", 1, 5));
  258. clk_dm(IMX8MN_SYS_PLL1_200M,
  259. imx_clk_fixed_factor("sys_pll1_200m", "sys_pll1_out", 1, 4));
  260. clk_dm(IMX8MN_SYS_PLL1_266M,
  261. imx_clk_fixed_factor("sys_pll1_266m", "sys_pll1_out", 1, 3));
  262. clk_dm(IMX8MN_SYS_PLL1_400M,
  263. imx_clk_fixed_factor("sys_pll1_400m", "sys_pll1_out", 1, 2));
  264. clk_dm(IMX8MN_SYS_PLL1_800M,
  265. imx_clk_fixed_factor("sys_pll1_800m", "sys_pll1_out", 1, 1));
  266. clk_dm(IMX8MN_SYS_PLL2_50M,
  267. imx_clk_fixed_factor("sys_pll2_50m", "sys_pll2_out", 1, 20));
  268. clk_dm(IMX8MN_SYS_PLL2_100M,
  269. imx_clk_fixed_factor("sys_pll2_100m", "sys_pll2_out", 1, 10));
  270. clk_dm(IMX8MN_SYS_PLL2_125M,
  271. imx_clk_fixed_factor("sys_pll2_125m", "sys_pll2_out", 1, 8));
  272. clk_dm(IMX8MN_SYS_PLL2_166M,
  273. imx_clk_fixed_factor("sys_pll2_166m", "sys_pll2_out", 1, 6));
  274. clk_dm(IMX8MN_SYS_PLL2_200M,
  275. imx_clk_fixed_factor("sys_pll2_200m", "sys_pll2_out", 1, 5));
  276. clk_dm(IMX8MN_SYS_PLL2_250M,
  277. imx_clk_fixed_factor("sys_pll2_250m", "sys_pll2_out", 1, 4));
  278. clk_dm(IMX8MN_SYS_PLL2_333M,
  279. imx_clk_fixed_factor("sys_pll2_333m", "sys_pll2_out", 1, 3));
  280. clk_dm(IMX8MN_SYS_PLL2_500M,
  281. imx_clk_fixed_factor("sys_pll2_500m", "sys_pll2_out", 1, 2));
  282. clk_dm(IMX8MN_SYS_PLL2_1000M,
  283. imx_clk_fixed_factor("sys_pll2_1000m", "sys_pll2_out", 1, 1));
  284. base = dev_read_addr_ptr(dev);
  285. if (!base)
  286. return -EINVAL;
  287. clk_dm(IMX8MN_CLK_A53_SRC,
  288. imx_clk_mux2("arm_a53_src", base + 0x8000, 24, 3,
  289. imx8mn_a53_sels, ARRAY_SIZE(imx8mn_a53_sels)));
  290. clk_dm(IMX8MN_CLK_A53_CG,
  291. imx_clk_gate3("arm_a53_cg", "arm_a53_src", base + 0x8000, 28));
  292. clk_dm(IMX8MN_CLK_A53_DIV,
  293. imx_clk_divider2("arm_a53_div", "arm_a53_cg",
  294. base + 0x8000, 0, 3));
  295. clk_dm(IMX8MN_CLK_AHB,
  296. imx8m_clk_composite_critical("ahb", imx8mn_ahb_sels,
  297. base + 0x9000));
  298. clk_dm(IMX8MN_CLK_IPG_ROOT,
  299. imx_clk_divider2("ipg_root", "ahb", base + 0x9080, 0, 1));
  300. clk_dm(IMX8MN_CLK_ENET_AXI,
  301. imx8m_clk_composite("enet_axi", imx8mn_enet_axi_sels,
  302. base + 0x8880));
  303. clk_dm(IMX8MN_CLK_NAND_USDHC_BUS,
  304. imx8m_clk_composite_critical("nand_usdhc_bus",
  305. imx8mn_nand_usdhc_sels,
  306. base + 0x8900));
  307. clk_dm(IMX8MN_CLK_USB_BUS,
  308. imx8m_clk_composite("usb_bus", imx8mn_usb_bus_sels, base + 0x8b80));
  309. /* IP */
  310. clk_dm(IMX8MN_CLK_USDHC1,
  311. imx8m_clk_composite("usdhc1", imx8mn_usdhc1_sels,
  312. base + 0xac00));
  313. clk_dm(IMX8MN_CLK_USDHC2,
  314. imx8m_clk_composite("usdhc2", imx8mn_usdhc2_sels,
  315. base + 0xac80));
  316. clk_dm(IMX8MN_CLK_I2C1,
  317. imx8m_clk_composite("i2c1", imx8mn_i2c1_sels, base + 0xad00));
  318. clk_dm(IMX8MN_CLK_I2C2,
  319. imx8m_clk_composite("i2c2", imx8mn_i2c2_sels, base + 0xad80));
  320. clk_dm(IMX8MN_CLK_I2C3,
  321. imx8m_clk_composite("i2c3", imx8mn_i2c3_sels, base + 0xae00));
  322. clk_dm(IMX8MN_CLK_I2C4,
  323. imx8m_clk_composite("i2c4", imx8mn_i2c4_sels, base + 0xae80));
  324. clk_dm(IMX8MN_CLK_WDOG,
  325. imx8m_clk_composite("wdog", imx8mn_wdog_sels, base + 0xb900));
  326. clk_dm(IMX8MN_CLK_USDHC3,
  327. imx8m_clk_composite("usdhc3", imx8mn_usdhc3_sels,
  328. base + 0xbc80));
  329. clk_dm(IMX8MN_CLK_QSPI,
  330. imx8m_clk_composite("qspi", imx8mn_qspi_sels, base + 0xab80));
  331. clk_dm(IMX8MN_CLK_USB_CORE_REF,
  332. imx8m_clk_composite("usb_core_ref", imx8mn_usb_core_sels, base + 0xb100));
  333. clk_dm(IMX8MN_CLK_USB_PHY_REF,
  334. imx8m_clk_composite("usb_phy_ref", imx8mn_usb_phy_sels, base + 0xb180));
  335. clk_dm(IMX8MN_CLK_I2C1_ROOT,
  336. imx_clk_gate4("i2c1_root_clk", "i2c1", base + 0x4170, 0));
  337. clk_dm(IMX8MN_CLK_I2C2_ROOT,
  338. imx_clk_gate4("i2c2_root_clk", "i2c2", base + 0x4180, 0));
  339. clk_dm(IMX8MN_CLK_I2C3_ROOT,
  340. imx_clk_gate4("i2c3_root_clk", "i2c3", base + 0x4190, 0));
  341. clk_dm(IMX8MN_CLK_I2C4_ROOT,
  342. imx_clk_gate4("i2c4_root_clk", "i2c4", base + 0x41a0, 0));
  343. clk_dm(IMX8MN_CLK_OCOTP_ROOT,
  344. imx_clk_gate4("ocotp_root_clk", "ipg_root", base + 0x4220, 0));
  345. clk_dm(IMX8MN_CLK_USDHC1_ROOT,
  346. imx_clk_gate4("usdhc1_root_clk", "usdhc1", base + 0x4510, 0));
  347. clk_dm(IMX8MN_CLK_USDHC2_ROOT,
  348. imx_clk_gate4("usdhc2_root_clk", "usdhc2", base + 0x4520, 0));
  349. clk_dm(IMX8MN_CLK_WDOG1_ROOT,
  350. imx_clk_gate4("wdog1_root_clk", "wdog", base + 0x4530, 0));
  351. clk_dm(IMX8MN_CLK_WDOG2_ROOT,
  352. imx_clk_gate4("wdog2_root_clk", "wdog", base + 0x4540, 0));
  353. clk_dm(IMX8MN_CLK_WDOG3_ROOT,
  354. imx_clk_gate4("wdog3_root_clk", "wdog", base + 0x4550, 0));
  355. clk_dm(IMX8MN_CLK_USDHC3_ROOT,
  356. imx_clk_gate4("usdhc3_root_clk", "usdhc3", base + 0x45e0, 0));
  357. clk_dm(IMX8MN_CLK_QSPI_ROOT,
  358. imx_clk_gate4("qspi_root_clk", "qspi", base + 0x42f0, 0));
  359. clk_dm(IMX8MN_CLK_USB1_CTRL_ROOT,
  360. imx_clk_gate4("usb1_ctrl_root_clk", "usb_bus", base + 0x44d0, 0));
  361. /* clks not needed in SPL stage */
  362. #ifndef CONFIG_SPL_BUILD
  363. clk_dm(IMX8MN_CLK_ENET_REF,
  364. imx8m_clk_composite("enet_ref", imx8mn_enet_ref_sels,
  365. base + 0xa980));
  366. clk_dm(IMX8MN_CLK_ENET_TIMER,
  367. imx8m_clk_composite("enet_timer", imx8mn_enet_timer_sels,
  368. base + 0xaa00));
  369. clk_dm(IMX8MN_CLK_ENET_PHY_REF,
  370. imx8m_clk_composite("enet_phy", imx8mn_enet_phy_sels,
  371. base + 0xaa80));
  372. clk_dm(IMX8MN_CLK_ENET1_ROOT,
  373. imx_clk_gate4("enet1_root_clk", "enet_axi",
  374. base + 0x40a0, 0));
  375. #endif
  376. return 0;
  377. }
  378. static const struct udevice_id imx8mn_clk_ids[] = {
  379. { .compatible = "fsl,imx8mn-ccm" },
  380. { },
  381. };
  382. U_BOOT_DRIVER(imx8mn_clk) = {
  383. .name = "clk_imx8mn",
  384. .id = UCLASS_CLK,
  385. .of_match = imx8mn_clk_ids,
  386. .ops = &imx8mn_clk_ops,
  387. .probe = imx8mn_clk_probe,
  388. .flags = DM_FLAG_PRE_RELOC,
  389. };