clk-imx8mm.c 16 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * Copyright 2019 NXP
  4. * Peng Fan <peng.fan@nxp.com>
  5. */
  6. #include <common.h>
  7. #include <clk.h>
  8. #include <clk-uclass.h>
  9. #include <dm.h>
  10. #include <log.h>
  11. #include <asm/arch/clock.h>
  12. #include <asm/arch/imx-regs.h>
  13. #include <dt-bindings/clock/imx8mm-clock.h>
  14. #include "clk.h"
  15. #define PLL_1416X_RATE(_rate, _m, _p, _s) \
  16. { \
  17. .rate = (_rate), \
  18. .mdiv = (_m), \
  19. .pdiv = (_p), \
  20. .sdiv = (_s), \
  21. }
  22. #define PLL_1443X_RATE(_rate, _m, _p, _s, _k) \
  23. { \
  24. .rate = (_rate), \
  25. .mdiv = (_m), \
  26. .pdiv = (_p), \
  27. .sdiv = (_s), \
  28. .kdiv = (_k), \
  29. }
  30. static const struct imx_pll14xx_rate_table imx8mm_pll1416x_tbl[] = {
  31. PLL_1416X_RATE(1800000000U, 225, 3, 0),
  32. PLL_1416X_RATE(1600000000U, 200, 3, 0),
  33. PLL_1416X_RATE(1200000000U, 300, 3, 1),
  34. PLL_1416X_RATE(1000000000U, 250, 3, 1),
  35. PLL_1416X_RATE(800000000U, 200, 3, 1),
  36. PLL_1416X_RATE(750000000U, 250, 2, 2),
  37. PLL_1416X_RATE(700000000U, 350, 3, 2),
  38. PLL_1416X_RATE(600000000U, 300, 3, 2),
  39. };
  40. static const struct imx_pll14xx_rate_table imx8mm_drampll_tbl[] = {
  41. PLL_1443X_RATE(650000000U, 325, 3, 2, 0),
  42. };
  43. static struct imx_pll14xx_clk imx8mm_dram_pll __initdata = {
  44. .type = PLL_1443X,
  45. .rate_table = imx8mm_drampll_tbl,
  46. .rate_count = ARRAY_SIZE(imx8mm_drampll_tbl),
  47. };
  48. static struct imx_pll14xx_clk imx8mm_arm_pll __initdata = {
  49. .type = PLL_1416X,
  50. .rate_table = imx8mm_pll1416x_tbl,
  51. .rate_count = ARRAY_SIZE(imx8mm_pll1416x_tbl),
  52. };
  53. static struct imx_pll14xx_clk imx8mm_sys_pll __initdata = {
  54. .type = PLL_1416X,
  55. .rate_table = imx8mm_pll1416x_tbl,
  56. .rate_count = ARRAY_SIZE(imx8mm_pll1416x_tbl),
  57. };
  58. static const char *pll_ref_sels[] = { "clock-osc-24m", "dummy", "dummy", "dummy", };
  59. static const char *dram_pll_bypass_sels[] = {"dram_pll", "dram_pll_ref_sel", };
  60. static const char *arm_pll_bypass_sels[] = {"arm_pll", "arm_pll_ref_sel", };
  61. static const char *sys_pll1_bypass_sels[] = {"sys_pll1", "sys_pll1_ref_sel", };
  62. static const char *sys_pll2_bypass_sels[] = {"sys_pll2", "sys_pll2_ref_sel", };
  63. static const char *sys_pll3_bypass_sels[] = {"sys_pll3", "sys_pll3_ref_sel", };
  64. static const char *imx8mm_a53_sels[] = {"clock-osc-24m", "arm_pll_out", "sys_pll2_500m", "sys_pll2_1000m",
  65. "sys_pll1_800m", "sys_pll1_400m", "audio_pll1_out", "sys_pll3_out", };
  66. static const char *imx8mm_ahb_sels[] = {"clock-osc-24m", "sys_pll1_133m", "sys_pll1_800m", "sys_pll1_400m",
  67. "sys_pll2_125m", "sys_pll3_out", "audio_pll1_out", "video_pll1_out", };
  68. static const char *imx8mm_enet_axi_sels[] = {"clock-osc-24m", "sys_pll1_266m", "sys_pll1_800m", "sys_pll2_250m",
  69. "sys_pll2_200m", "audio_pll1_out", "video_pll1_out", "sys_pll3_out", };
  70. #ifndef CONFIG_SPL_BUILD
  71. static const char *imx8mm_enet_ref_sels[] = {"clock-osc-24m", "sys_pll2_125m", "sys_pll2_50m", "sys_pll2_100m",
  72. "sys_pll1_160m", "audio_pll1_out", "video_pll1_out", "clk_ext4", };
  73. static const char *imx8mm_enet_timer_sels[] = {"clock-osc-24m", "sys_pll2_100m", "audio_pll1_out", "clk_ext1", "clk_ext2",
  74. "clk_ext3", "clk_ext4", "video_pll1_out", };
  75. static const char *imx8mm_enet_phy_sels[] = {"clock-osc-24m", "sys_pll2_50m", "sys_pll2_125m", "sys_pll2_200m",
  76. "sys_pll2_500m", "video_pll1_out", "audio_pll2_out", };
  77. #endif
  78. static const char *imx8mm_nand_usdhc_sels[] = {"clock-osc-24m", "sys_pll1_266m", "sys_pll1_800m", "sys_pll2_200m",
  79. "sys_pll1_133m", "sys_pll3_out", "sys_pll2_250m", "audio_pll1_out", };
  80. static const char *imx8mm_usb_bus_sels[] = {"clock-osc-24m", "sys_pll2_500m", "sys_pll1_800m", "sys_pll2_100m",
  81. "sys_pll2_200m", "clk_ext2", "clk_ext4", "audio_pll2_out", };
  82. static const char *imx8mm_usdhc1_sels[] = {"clock-osc-24m", "sys_pll1_400m", "sys_pll1_800m", "sys_pll2_500m",
  83. "sys_pll3_out", "sys_pll1_266m", "audio_pll2_out", "sys_pll1_100m", };
  84. static const char *imx8mm_usdhc2_sels[] = {"clock-osc-24m", "sys_pll1_400m", "sys_pll1_800m", "sys_pll2_500m",
  85. "sys_pll3_out", "sys_pll1_266m", "audio_pll2_out", "sys_pll1_100m", };
  86. static const char *imx8mm_i2c1_sels[] = {"clock-osc-24m", "sys_pll1_160m", "sys_pll2_50m", "sys_pll3_out", "audio_pll1_out",
  87. "video_pll1_out", "audio_pll2_out", "sys_pll1_133m", };
  88. static const char *imx8mm_i2c2_sels[] = {"clock-osc-24m", "sys_pll1_160m", "sys_pll2_50m", "sys_pll3_out", "audio_pll1_out",
  89. "video_pll1_out", "audio_pll2_out", "sys_pll1_133m", };
  90. static const char *imx8mm_i2c3_sels[] = {"clock-osc-24m", "sys_pll1_160m", "sys_pll2_50m", "sys_pll3_out", "audio_pll1_out",
  91. "video_pll1_out", "audio_pll2_out", "sys_pll1_133m", };
  92. static const char *imx8mm_i2c4_sels[] = {"clock-osc-24m", "sys_pll1_160m", "sys_pll2_50m", "sys_pll3_out", "audio_pll1_out",
  93. "video_pll1_out", "audio_pll2_out", "sys_pll1_133m", };
  94. static const char *imx8mm_wdog_sels[] = {"clock-osc-24m", "sys_pll1_133m", "sys_pll1_160m", "vpu_pll_out",
  95. "sys_pll2_125m", "sys_pll3_out", "sys_pll1_80m", "sys_pll2_166m", };
  96. static const char *imx8mm_usdhc3_sels[] = {"clock-osc-24m", "sys_pll1_400m", "sys_pll1_800m", "sys_pll2_500m",
  97. "sys_pll3_out", "sys_pll1_266m", "audio_pll2_clk", "sys_pll1_100m", };
  98. static const char *imx8mm_qspi_sels[] = {"clock-osc-24m", "sys_pll1_400m", "sys_pll2_333m", "sys_pll2_500m",
  99. "audio_pll2_out", "sys_pll1_266m", "sys_pll3_out", "sys_pll1_100m", };
  100. static const char *imx8mm_usb_core_sels[] = {"clock-osc-24m", "sys_pll1_100m", "sys_pll1_40m", "sys_pll2_100m",
  101. "sys_pll2_200m", "clk_ext2", "clk_ext3", "audio_pll2_out", };
  102. static const char *imx8mm_usb_phy_sels[] = {"clock-osc-24m", "sys_pll1_100m", "sys_pll1_40m", "sys_pll2_100m",
  103. "sys_pll2_200m", "clk_ext2", "clk_ext3", "audio_pll2_out", };
  104. static ulong imx8mm_clk_get_rate(struct clk *clk)
  105. {
  106. struct clk *c;
  107. int ret;
  108. debug("%s(#%lu)\n", __func__, clk->id);
  109. ret = clk_get_by_id(clk->id, &c);
  110. if (ret)
  111. return ret;
  112. return clk_get_rate(c);
  113. }
  114. static ulong imx8mm_clk_set_rate(struct clk *clk, unsigned long rate)
  115. {
  116. struct clk *c;
  117. int ret;
  118. debug("%s(#%lu), rate: %lu\n", __func__, clk->id, rate);
  119. ret = clk_get_by_id(clk->id, &c);
  120. if (ret)
  121. return ret;
  122. return clk_set_rate(c, rate);
  123. }
  124. static int __imx8mm_clk_enable(struct clk *clk, bool enable)
  125. {
  126. struct clk *c;
  127. int ret;
  128. debug("%s(#%lu) en: %d\n", __func__, clk->id, enable);
  129. ret = clk_get_by_id(clk->id, &c);
  130. if (ret)
  131. return ret;
  132. if (enable)
  133. ret = clk_enable(c);
  134. else
  135. ret = clk_disable(c);
  136. return ret;
  137. }
  138. static int imx8mm_clk_disable(struct clk *clk)
  139. {
  140. return __imx8mm_clk_enable(clk, 0);
  141. }
  142. static int imx8mm_clk_enable(struct clk *clk)
  143. {
  144. return __imx8mm_clk_enable(clk, 1);
  145. }
  146. static int imx8mm_clk_set_parent(struct clk *clk, struct clk *parent)
  147. {
  148. struct clk *c, *cp;
  149. int ret;
  150. debug("%s(#%lu), parent: %lu\n", __func__, clk->id, parent->id);
  151. ret = clk_get_by_id(clk->id, &c);
  152. if (ret)
  153. return ret;
  154. ret = clk_get_by_id(parent->id, &cp);
  155. if (ret)
  156. return ret;
  157. ret = clk_set_parent(c, cp);
  158. c->dev->parent = cp->dev;
  159. return ret;
  160. }
  161. static struct clk_ops imx8mm_clk_ops = {
  162. .set_rate = imx8mm_clk_set_rate,
  163. .get_rate = imx8mm_clk_get_rate,
  164. .enable = imx8mm_clk_enable,
  165. .disable = imx8mm_clk_disable,
  166. .set_parent = imx8mm_clk_set_parent,
  167. };
  168. static int imx8mm_clk_probe(struct udevice *dev)
  169. {
  170. void __iomem *base;
  171. base = (void *)ANATOP_BASE_ADDR;
  172. clk_dm(IMX8MM_DRAM_PLL_REF_SEL,
  173. imx_clk_mux("dram_pll_ref_sel", base + 0x50, 0, 2,
  174. pll_ref_sels, ARRAY_SIZE(pll_ref_sels)));
  175. clk_dm(IMX8MM_ARM_PLL_REF_SEL,
  176. imx_clk_mux("arm_pll_ref_sel", base + 0x84, 0, 2,
  177. pll_ref_sels, ARRAY_SIZE(pll_ref_sels)));
  178. clk_dm(IMX8MM_SYS_PLL1_REF_SEL,
  179. imx_clk_mux("sys_pll1_ref_sel", base + 0x94, 0, 2,
  180. pll_ref_sels, ARRAY_SIZE(pll_ref_sels)));
  181. clk_dm(IMX8MM_SYS_PLL2_REF_SEL,
  182. imx_clk_mux("sys_pll2_ref_sel", base + 0x104, 0, 2,
  183. pll_ref_sels, ARRAY_SIZE(pll_ref_sels)));
  184. clk_dm(IMX8MM_SYS_PLL3_REF_SEL,
  185. imx_clk_mux("sys_pll3_ref_sel", base + 0x114, 0, 2,
  186. pll_ref_sels, ARRAY_SIZE(pll_ref_sels)));
  187. clk_dm(IMX8MM_DRAM_PLL,
  188. imx_clk_pll14xx("dram_pll", "dram_pll_ref_sel",
  189. base + 0x50, &imx8mm_dram_pll));
  190. clk_dm(IMX8MM_ARM_PLL,
  191. imx_clk_pll14xx("arm_pll", "arm_pll_ref_sel",
  192. base + 0x84, &imx8mm_arm_pll));
  193. clk_dm(IMX8MM_SYS_PLL1,
  194. imx_clk_pll14xx("sys_pll1", "sys_pll1_ref_sel",
  195. base + 0x94, &imx8mm_sys_pll));
  196. clk_dm(IMX8MM_SYS_PLL2,
  197. imx_clk_pll14xx("sys_pll2", "sys_pll2_ref_sel",
  198. base + 0x104, &imx8mm_sys_pll));
  199. clk_dm(IMX8MM_SYS_PLL3,
  200. imx_clk_pll14xx("sys_pll3", "sys_pll3_ref_sel",
  201. base + 0x114, &imx8mm_sys_pll));
  202. /* PLL bypass out */
  203. clk_dm(IMX8MM_DRAM_PLL_BYPASS,
  204. imx_clk_mux_flags("dram_pll_bypass", base + 0x50, 4, 1,
  205. dram_pll_bypass_sels,
  206. ARRAY_SIZE(dram_pll_bypass_sels),
  207. CLK_SET_RATE_PARENT));
  208. clk_dm(IMX8MM_ARM_PLL_BYPASS,
  209. imx_clk_mux_flags("arm_pll_bypass", base + 0x84, 4, 1,
  210. arm_pll_bypass_sels,
  211. ARRAY_SIZE(arm_pll_bypass_sels),
  212. CLK_SET_RATE_PARENT));
  213. clk_dm(IMX8MM_SYS_PLL1_BYPASS,
  214. imx_clk_mux_flags("sys_pll1_bypass", base + 0x94, 4, 1,
  215. sys_pll1_bypass_sels,
  216. ARRAY_SIZE(sys_pll1_bypass_sels),
  217. CLK_SET_RATE_PARENT));
  218. clk_dm(IMX8MM_SYS_PLL2_BYPASS,
  219. imx_clk_mux_flags("sys_pll2_bypass", base + 0x104, 4, 1,
  220. sys_pll2_bypass_sels,
  221. ARRAY_SIZE(sys_pll2_bypass_sels),
  222. CLK_SET_RATE_PARENT));
  223. clk_dm(IMX8MM_SYS_PLL3_BYPASS,
  224. imx_clk_mux_flags("sys_pll3_bypass", base + 0x114, 4, 1,
  225. sys_pll3_bypass_sels,
  226. ARRAY_SIZE(sys_pll3_bypass_sels),
  227. CLK_SET_RATE_PARENT));
  228. /* PLL out gate */
  229. clk_dm(IMX8MM_DRAM_PLL_OUT,
  230. imx_clk_gate("dram_pll_out", "dram_pll_bypass",
  231. base + 0x50, 13));
  232. clk_dm(IMX8MM_ARM_PLL_OUT,
  233. imx_clk_gate("arm_pll_out", "arm_pll_bypass",
  234. base + 0x84, 11));
  235. clk_dm(IMX8MM_SYS_PLL1_OUT,
  236. imx_clk_gate("sys_pll1_out", "sys_pll1_bypass",
  237. base + 0x94, 11));
  238. clk_dm(IMX8MM_SYS_PLL2_OUT,
  239. imx_clk_gate("sys_pll2_out", "sys_pll2_bypass",
  240. base + 0x104, 11));
  241. clk_dm(IMX8MM_SYS_PLL3_OUT,
  242. imx_clk_gate("sys_pll3_out", "sys_pll3_bypass",
  243. base + 0x114, 11));
  244. /* SYS PLL fixed output */
  245. clk_dm(IMX8MM_SYS_PLL1_40M,
  246. imx_clk_fixed_factor("sys_pll1_40m", "sys_pll1_out", 1, 20));
  247. clk_dm(IMX8MM_SYS_PLL1_80M,
  248. imx_clk_fixed_factor("sys_pll1_80m", "sys_pll1_out", 1, 10));
  249. clk_dm(IMX8MM_SYS_PLL1_100M,
  250. imx_clk_fixed_factor("sys_pll1_100m", "sys_pll1_out", 1, 8));
  251. clk_dm(IMX8MM_SYS_PLL1_133M,
  252. imx_clk_fixed_factor("sys_pll1_133m", "sys_pll1_out", 1, 6));
  253. clk_dm(IMX8MM_SYS_PLL1_160M,
  254. imx_clk_fixed_factor("sys_pll1_160m", "sys_pll1_out", 1, 5));
  255. clk_dm(IMX8MM_SYS_PLL1_200M,
  256. imx_clk_fixed_factor("sys_pll1_200m", "sys_pll1_out", 1, 4));
  257. clk_dm(IMX8MM_SYS_PLL1_266M,
  258. imx_clk_fixed_factor("sys_pll1_266m", "sys_pll1_out", 1, 3));
  259. clk_dm(IMX8MM_SYS_PLL1_400M,
  260. imx_clk_fixed_factor("sys_pll1_400m", "sys_pll1_out", 1, 2));
  261. clk_dm(IMX8MM_SYS_PLL1_800M,
  262. imx_clk_fixed_factor("sys_pll1_800m", "sys_pll1_out", 1, 1));
  263. clk_dm(IMX8MM_SYS_PLL2_50M,
  264. imx_clk_fixed_factor("sys_pll2_50m", "sys_pll2_out", 1, 20));
  265. clk_dm(IMX8MM_SYS_PLL2_100M,
  266. imx_clk_fixed_factor("sys_pll2_100m", "sys_pll2_out", 1, 10));
  267. clk_dm(IMX8MM_SYS_PLL2_125M,
  268. imx_clk_fixed_factor("sys_pll2_125m", "sys_pll2_out", 1, 8));
  269. clk_dm(IMX8MM_SYS_PLL2_166M,
  270. imx_clk_fixed_factor("sys_pll2_166m", "sys_pll2_out", 1, 6));
  271. clk_dm(IMX8MM_SYS_PLL2_200M,
  272. imx_clk_fixed_factor("sys_pll2_200m", "sys_pll2_out", 1, 5));
  273. clk_dm(IMX8MM_SYS_PLL2_250M,
  274. imx_clk_fixed_factor("sys_pll2_250m", "sys_pll2_out", 1, 4));
  275. clk_dm(IMX8MM_SYS_PLL2_333M,
  276. imx_clk_fixed_factor("sys_pll2_333m", "sys_pll2_out", 1, 3));
  277. clk_dm(IMX8MM_SYS_PLL2_500M,
  278. imx_clk_fixed_factor("sys_pll2_500m", "sys_pll2_out", 1, 2));
  279. clk_dm(IMX8MM_SYS_PLL2_1000M,
  280. imx_clk_fixed_factor("sys_pll2_1000m", "sys_pll2_out", 1, 1));
  281. base = dev_read_addr_ptr(dev);
  282. if (!base)
  283. return -EINVAL;
  284. clk_dm(IMX8MM_CLK_A53_SRC,
  285. imx_clk_mux2("arm_a53_src", base + 0x8000, 24, 3,
  286. imx8mm_a53_sels, ARRAY_SIZE(imx8mm_a53_sels)));
  287. clk_dm(IMX8MM_CLK_A53_CG,
  288. imx_clk_gate3("arm_a53_cg", "arm_a53_src", base + 0x8000, 28));
  289. clk_dm(IMX8MM_CLK_A53_DIV,
  290. imx_clk_divider2("arm_a53_div", "arm_a53_cg",
  291. base + 0x8000, 0, 3));
  292. clk_dm(IMX8MM_CLK_AHB,
  293. imx8m_clk_composite_critical("ahb", imx8mm_ahb_sels,
  294. base + 0x9000));
  295. clk_dm(IMX8MM_CLK_IPG_ROOT,
  296. imx_clk_divider2("ipg_root", "ahb", base + 0x9080, 0, 1));
  297. clk_dm(IMX8MM_CLK_ENET_AXI,
  298. imx8m_clk_composite("enet_axi", imx8mm_enet_axi_sels,
  299. base + 0x8880));
  300. clk_dm(IMX8MM_CLK_NAND_USDHC_BUS,
  301. imx8m_clk_composite_critical("nand_usdhc_bus",
  302. imx8mm_nand_usdhc_sels,
  303. base + 0x8900));
  304. clk_dm(IMX8MM_CLK_USB_BUS,
  305. imx8m_clk_composite("usb_bus", imx8mm_usb_bus_sels, base + 0x8b80));
  306. /* IP */
  307. clk_dm(IMX8MM_CLK_USDHC1,
  308. imx8m_clk_composite("usdhc1", imx8mm_usdhc1_sels,
  309. base + 0xac00));
  310. clk_dm(IMX8MM_CLK_USDHC2,
  311. imx8m_clk_composite("usdhc2", imx8mm_usdhc2_sels,
  312. base + 0xac80));
  313. clk_dm(IMX8MM_CLK_I2C1,
  314. imx8m_clk_composite("i2c1", imx8mm_i2c1_sels, base + 0xad00));
  315. clk_dm(IMX8MM_CLK_I2C2,
  316. imx8m_clk_composite("i2c2", imx8mm_i2c2_sels, base + 0xad80));
  317. clk_dm(IMX8MM_CLK_I2C3,
  318. imx8m_clk_composite("i2c3", imx8mm_i2c3_sels, base + 0xae00));
  319. clk_dm(IMX8MM_CLK_I2C4,
  320. imx8m_clk_composite("i2c4", imx8mm_i2c4_sels, base + 0xae80));
  321. clk_dm(IMX8MM_CLK_WDOG,
  322. imx8m_clk_composite("wdog", imx8mm_wdog_sels, base + 0xb900));
  323. clk_dm(IMX8MM_CLK_USDHC3,
  324. imx8m_clk_composite("usdhc3", imx8mm_usdhc3_sels,
  325. base + 0xbc80));
  326. clk_dm(IMX8MM_CLK_QSPI,
  327. imx8m_clk_composite("qspi", imx8mm_qspi_sels, base + 0xab80));
  328. clk_dm(IMX8MM_CLK_USB_CORE_REF,
  329. imx8m_clk_composite("usb_core_ref", imx8mm_usb_core_sels, base + 0xb100));
  330. clk_dm(IMX8MM_CLK_USB_PHY_REF,
  331. imx8m_clk_composite("usb_phy_ref", imx8mm_usb_phy_sels, base + 0xb180));
  332. clk_dm(IMX8MM_CLK_I2C1_ROOT,
  333. imx_clk_gate4("i2c1_root_clk", "i2c1", base + 0x4170, 0));
  334. clk_dm(IMX8MM_CLK_I2C2_ROOT,
  335. imx_clk_gate4("i2c2_root_clk", "i2c2", base + 0x4180, 0));
  336. clk_dm(IMX8MM_CLK_I2C3_ROOT,
  337. imx_clk_gate4("i2c3_root_clk", "i2c3", base + 0x4190, 0));
  338. clk_dm(IMX8MM_CLK_I2C4_ROOT,
  339. imx_clk_gate4("i2c4_root_clk", "i2c4", base + 0x41a0, 0));
  340. clk_dm(IMX8MM_CLK_OCOTP_ROOT,
  341. imx_clk_gate4("ocotp_root_clk", "ipg_root", base + 0x4220, 0));
  342. clk_dm(IMX8MM_CLK_USDHC1_ROOT,
  343. imx_clk_gate4("usdhc1_root_clk", "usdhc1", base + 0x4510, 0));
  344. clk_dm(IMX8MM_CLK_USDHC2_ROOT,
  345. imx_clk_gate4("usdhc2_root_clk", "usdhc2", base + 0x4520, 0));
  346. clk_dm(IMX8MM_CLK_WDOG1_ROOT,
  347. imx_clk_gate4("wdog1_root_clk", "wdog", base + 0x4530, 0));
  348. clk_dm(IMX8MM_CLK_WDOG2_ROOT,
  349. imx_clk_gate4("wdog2_root_clk", "wdog", base + 0x4540, 0));
  350. clk_dm(IMX8MM_CLK_WDOG3_ROOT,
  351. imx_clk_gate4("wdog3_root_clk", "wdog", base + 0x4550, 0));
  352. clk_dm(IMX8MM_CLK_USDHC3_ROOT,
  353. imx_clk_gate4("usdhc3_root_clk", "usdhc3", base + 0x45e0, 0));
  354. clk_dm(IMX8MM_CLK_QSPI_ROOT,
  355. imx_clk_gate4("qspi_root_clk", "qspi", base + 0x42f0, 0));
  356. clk_dm(IMX8MM_CLK_USB1_CTRL_ROOT,
  357. imx_clk_gate4("usb1_ctrl_root_clk", "usb_bus", base + 0x44d0, 0));
  358. /* clks not needed in SPL stage */
  359. #ifndef CONFIG_SPL_BUILD
  360. clk_dm(IMX8MM_CLK_ENET_REF,
  361. imx8m_clk_composite("enet_ref", imx8mm_enet_ref_sels,
  362. base + 0xa980));
  363. clk_dm(IMX8MM_CLK_ENET_TIMER,
  364. imx8m_clk_composite("enet_timer", imx8mm_enet_timer_sels,
  365. base + 0xaa00));
  366. clk_dm(IMX8MM_CLK_ENET_PHY_REF,
  367. imx8m_clk_composite("enet_phy", imx8mm_enet_phy_sels,
  368. base + 0xaa80));
  369. clk_dm(IMX8MM_CLK_ENET1_ROOT,
  370. imx_clk_gate4("enet1_root_clk", "enet_axi",
  371. base + 0x40a0, 0));
  372. #endif
  373. return 0;
  374. }
  375. static const struct udevice_id imx8mm_clk_ids[] = {
  376. { .compatible = "fsl,imx8mm-ccm" },
  377. { },
  378. };
  379. U_BOOT_DRIVER(imx8mm_clk) = {
  380. .name = "clk_imx8mm",
  381. .id = UCLASS_CLK,
  382. .of_match = imx8mm_clk_ids,
  383. .ops = &imx8mm_clk_ops,
  384. .probe = imx8mm_clk_probe,
  385. .flags = DM_FLAG_PRE_RELOC,
  386. };