clk-composite-8m.c 4.2 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * Copyright 2019 NXP
  4. */
  5. #include <common.h>
  6. #include <log.h>
  7. #include <asm/io.h>
  8. #include <malloc.h>
  9. #include <clk-uclass.h>
  10. #include <dm/device.h>
  11. #include <dm/devres.h>
  12. #include <linux/clk-provider.h>
  13. #include <clk.h>
  14. #include "clk.h"
  15. #include <linux/err.h>
  16. #define UBOOT_DM_CLK_IMX_COMPOSITE "imx_clk_composite"
  17. #define PCG_PREDIV_SHIFT 16
  18. #define PCG_PREDIV_WIDTH 3
  19. #define PCG_PREDIV_MAX 8
  20. #define PCG_DIV_SHIFT 0
  21. #define PCG_DIV_WIDTH 6
  22. #define PCG_DIV_MAX 64
  23. #define PCG_PCS_SHIFT 24
  24. #define PCG_PCS_MASK 0x7
  25. #define PCG_CGC_SHIFT 28
  26. static unsigned long imx8m_clk_composite_divider_recalc_rate(struct clk *clk)
  27. {
  28. struct clk_divider *divider = (struct clk_divider *)to_clk_divider(clk);
  29. struct clk_composite *composite = (struct clk_composite *)clk->data;
  30. ulong parent_rate = clk_get_parent_rate(&composite->clk);
  31. unsigned long prediv_rate;
  32. unsigned int prediv_value;
  33. unsigned int div_value;
  34. debug("%s: name %s prate: %lu reg: %p\n", __func__,
  35. (&composite->clk)->dev->name, parent_rate, divider->reg);
  36. prediv_value = readl(divider->reg) >> divider->shift;
  37. prediv_value &= clk_div_mask(divider->width);
  38. prediv_rate = divider_recalc_rate(clk, parent_rate, prediv_value,
  39. NULL, divider->flags,
  40. divider->width);
  41. div_value = readl(divider->reg) >> PCG_DIV_SHIFT;
  42. div_value &= clk_div_mask(PCG_DIV_WIDTH);
  43. return divider_recalc_rate(clk, prediv_rate, div_value, NULL,
  44. divider->flags, PCG_DIV_WIDTH);
  45. }
  46. static int imx8m_clk_composite_compute_dividers(unsigned long rate,
  47. unsigned long parent_rate,
  48. int *prediv, int *postdiv)
  49. {
  50. int div1, div2;
  51. int error = INT_MAX;
  52. int ret = -EINVAL;
  53. *prediv = 1;
  54. *postdiv = 1;
  55. for (div1 = 1; div1 <= PCG_PREDIV_MAX; div1++) {
  56. for (div2 = 1; div2 <= PCG_DIV_MAX; div2++) {
  57. int new_error = ((parent_rate / div1) / div2) - rate;
  58. if (abs(new_error) < abs(error)) {
  59. *prediv = div1;
  60. *postdiv = div2;
  61. error = new_error;
  62. ret = 0;
  63. }
  64. }
  65. }
  66. return ret;
  67. }
  68. /*
  69. * The clk are bound to a dev, because it is part of composite clk
  70. * use composite clk to get dev
  71. */
  72. static ulong imx8m_clk_composite_divider_set_rate(struct clk *clk,
  73. unsigned long rate)
  74. {
  75. struct clk_divider *divider = (struct clk_divider *)to_clk_divider(clk);
  76. struct clk_composite *composite = (struct clk_composite *)clk->data;
  77. ulong parent_rate = clk_get_parent_rate(&composite->clk);
  78. int prediv_value;
  79. int div_value;
  80. int ret;
  81. u32 val;
  82. ret = imx8m_clk_composite_compute_dividers(rate, parent_rate,
  83. &prediv_value, &div_value);
  84. if (ret)
  85. return ret;
  86. val = readl(divider->reg);
  87. val &= ~((clk_div_mask(divider->width) << divider->shift) |
  88. (clk_div_mask(PCG_DIV_WIDTH) << PCG_DIV_SHIFT));
  89. val |= (u32)(prediv_value - 1) << divider->shift;
  90. val |= (u32)(div_value - 1) << PCG_DIV_SHIFT;
  91. writel(val, divider->reg);
  92. return clk_get_rate(&composite->clk);
  93. }
  94. static const struct clk_ops imx8m_clk_composite_divider_ops = {
  95. .get_rate = imx8m_clk_composite_divider_recalc_rate,
  96. .set_rate = imx8m_clk_composite_divider_set_rate,
  97. };
  98. struct clk *imx8m_clk_composite_flags(const char *name,
  99. const char * const *parent_names,
  100. int num_parents, void __iomem *reg,
  101. unsigned long flags)
  102. {
  103. struct clk *clk = ERR_PTR(-ENOMEM);
  104. struct clk_divider *div = NULL;
  105. struct clk_gate *gate = NULL;
  106. struct clk_mux *mux = NULL;
  107. mux = kzalloc(sizeof(*mux), GFP_KERNEL);
  108. if (!mux)
  109. goto fail;
  110. mux->reg = reg;
  111. mux->shift = PCG_PCS_SHIFT;
  112. mux->mask = PCG_PCS_MASK;
  113. mux->num_parents = num_parents;
  114. mux->flags = flags;
  115. mux->parent_names = parent_names;
  116. div = kzalloc(sizeof(*div), GFP_KERNEL);
  117. if (!div)
  118. goto fail;
  119. div->reg = reg;
  120. div->shift = PCG_PREDIV_SHIFT;
  121. div->width = PCG_PREDIV_WIDTH;
  122. div->flags = CLK_DIVIDER_ROUND_CLOSEST | flags;
  123. gate = kzalloc(sizeof(*gate), GFP_KERNEL);
  124. if (!gate)
  125. goto fail;
  126. gate->reg = reg;
  127. gate->bit_idx = PCG_CGC_SHIFT;
  128. gate->flags = flags;
  129. clk = clk_register_composite(NULL, name,
  130. parent_names, num_parents,
  131. &mux->clk, &clk_mux_ops, &div->clk,
  132. &imx8m_clk_composite_divider_ops,
  133. &gate->clk, &clk_gate_ops, flags);
  134. if (IS_ERR(clk))
  135. goto fail;
  136. return clk;
  137. fail:
  138. kfree(gate);
  139. kfree(div);
  140. kfree(mux);
  141. return ERR_CAST(clk);
  142. }