clk-cdce9xx.c 5.3 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Texas Instruments CDCE913/925/937/949 clock synthesizer driver
  4. *
  5. * Copyright (C) 2019 Texas Instruments Incorporated - http://www.ti.com/
  6. * Tero Kristo <t-kristo@ti.com>
  7. *
  8. * Based on Linux kernel clk-cdce925.c.
  9. */
  10. #include <common.h>
  11. #include <dm.h>
  12. #include <errno.h>
  13. #include <clk-uclass.h>
  14. #include <i2c.h>
  15. #include <dm/device_compat.h>
  16. #include <linux/bitops.h>
  17. #define MAX_NUMBER_OF_PLLS 4
  18. #define MAX_NUMER_OF_OUTPUTS 9
  19. #define CDCE9XX_REG_GLOBAL1 0x01
  20. #define CDCE9XX_REG_Y1SPIPDIVH 0x02
  21. #define CDCE9XX_REG_PDIV1L 0x03
  22. #define CDCE9XX_REG_XCSEL 0x05
  23. #define CDCE9XX_PDIV1_H_MASK 0x3
  24. #define CDCE9XX_REG_PDIV(clk) (0x16 + (((clk) - 1) & 1) + \
  25. ((clk) - 1) / 2 * 0x10)
  26. #define CDCE9XX_PDIV_MASK 0x7f
  27. #define CDCE9XX_BYTE_TRANSFER BIT(7)
  28. struct cdce9xx_chip_info {
  29. int num_plls;
  30. int num_outputs;
  31. };
  32. struct cdce9xx_clk_data {
  33. struct udevice *i2c;
  34. struct cdce9xx_chip_info *chip;
  35. u32 xtal_rate;
  36. };
  37. static const struct cdce9xx_chip_info cdce913_chip_info = {
  38. .num_plls = 1, .num_outputs = 3,
  39. };
  40. static const struct cdce9xx_chip_info cdce925_chip_info = {
  41. .num_plls = 2, .num_outputs = 5,
  42. };
  43. static const struct cdce9xx_chip_info cdce937_chip_info = {
  44. .num_plls = 3, .num_outputs = 7,
  45. };
  46. static const struct cdce9xx_chip_info cdce949_chip_info = {
  47. .num_plls = 4, .num_outputs = 9,
  48. };
  49. static int cdce9xx_reg_read(struct udevice *dev, u8 addr, u8 *buf)
  50. {
  51. struct cdce9xx_clk_data *data = dev_get_priv(dev);
  52. int ret;
  53. ret = dm_i2c_read(data->i2c, addr | CDCE9XX_BYTE_TRANSFER, buf, 1);
  54. if (ret)
  55. dev_err(dev, "%s: failed for addr:%x, ret:%d\n", __func__,
  56. addr, ret);
  57. return ret;
  58. }
  59. static int cdce9xx_reg_write(struct udevice *dev, u8 addr, u8 val)
  60. {
  61. struct cdce9xx_clk_data *data = dev_get_priv(dev);
  62. int ret;
  63. ret = dm_i2c_write(data->i2c, addr | CDCE9XX_BYTE_TRANSFER, &val, 1);
  64. if (ret)
  65. dev_err(dev, "%s: failed for addr:%x, ret:%d\n", __func__,
  66. addr, ret);
  67. return ret;
  68. }
  69. static int cdce9xx_clk_of_xlate(struct clk *clk,
  70. struct ofnode_phandle_args *args)
  71. {
  72. struct cdce9xx_clk_data *data = dev_get_priv(clk->dev);
  73. if (args->args_count != 1)
  74. return -EINVAL;
  75. if (args->args[0] > data->chip->num_outputs)
  76. return -EINVAL;
  77. clk->id = args->args[0];
  78. return 0;
  79. }
  80. static int cdce9xx_clk_probe(struct udevice *dev)
  81. {
  82. struct cdce9xx_clk_data *data = dev_get_priv(dev);
  83. struct cdce9xx_chip_info *chip = (void *)dev_get_driver_data(dev);
  84. int ret;
  85. u32 val;
  86. struct clk clk;
  87. val = (u32)dev_read_addr_ptr(dev);
  88. ret = i2c_get_chip(dev->parent, val, 1, &data->i2c);
  89. if (ret) {
  90. dev_err(dev, "I2C probe failed.\n");
  91. return ret;
  92. }
  93. data->chip = chip;
  94. ret = clk_get_by_index(dev, 0, &clk);
  95. data->xtal_rate = clk_get_rate(&clk);
  96. val = dev_read_u32_default(dev, "xtal-load-pf", -1);
  97. if (val >= 0)
  98. cdce9xx_reg_write(dev, CDCE9XX_REG_XCSEL, val << 3);
  99. return 0;
  100. }
  101. static u16 cdce9xx_clk_get_pdiv(struct clk *clk)
  102. {
  103. u8 val;
  104. u16 pdiv;
  105. int ret;
  106. if (clk->id == 0) {
  107. ret = cdce9xx_reg_read(clk->dev, CDCE9XX_REG_Y1SPIPDIVH, &val);
  108. if (ret)
  109. return 0;
  110. pdiv = (val & CDCE9XX_PDIV1_H_MASK) << 8;
  111. ret = cdce9xx_reg_read(clk->dev, CDCE9XX_REG_PDIV1L, &val);
  112. if (ret)
  113. return 0;
  114. pdiv |= val;
  115. } else {
  116. ret = cdce9xx_reg_read(clk->dev, CDCE9XX_REG_PDIV(clk->id),
  117. &val);
  118. if (ret)
  119. return 0;
  120. pdiv = val & CDCE9XX_PDIV_MASK;
  121. }
  122. return pdiv;
  123. }
  124. static u32 cdce9xx_clk_get_parent_rate(struct clk *clk)
  125. {
  126. struct cdce9xx_clk_data *data = dev_get_priv(clk->dev);
  127. return data->xtal_rate;
  128. }
  129. static ulong cdce9xx_clk_get_rate(struct clk *clk)
  130. {
  131. u32 parent_rate;
  132. u16 pdiv;
  133. parent_rate = cdce9xx_clk_get_parent_rate(clk);
  134. pdiv = cdce9xx_clk_get_pdiv(clk);
  135. return parent_rate / pdiv;
  136. }
  137. static ulong cdce9xx_clk_set_rate(struct clk *clk, ulong rate)
  138. {
  139. u32 parent_rate;
  140. int pdiv;
  141. u32 diff;
  142. u8 val;
  143. int ret;
  144. parent_rate = cdce9xx_clk_get_parent_rate(clk);
  145. pdiv = parent_rate / rate;
  146. diff = rate - parent_rate / pdiv;
  147. if (rate - parent_rate / (pdiv + 1) < diff)
  148. pdiv++;
  149. if (clk->id == 0) {
  150. ret = cdce9xx_reg_read(clk->dev, CDCE9XX_REG_Y1SPIPDIVH, &val);
  151. if (ret)
  152. return ret;
  153. val &= ~CDCE9XX_PDIV1_H_MASK;
  154. val |= (pdiv >> 8);
  155. ret = cdce9xx_reg_write(clk->dev, CDCE9XX_REG_Y1SPIPDIVH, val);
  156. if (ret)
  157. return ret;
  158. ret = cdce9xx_reg_write(clk->dev, CDCE9XX_REG_PDIV1L,
  159. (pdiv & 0xff));
  160. if (ret)
  161. return ret;
  162. } else {
  163. ret = cdce9xx_reg_read(clk->dev, CDCE9XX_REG_PDIV(clk->id),
  164. &val);
  165. if (ret)
  166. return ret;
  167. val &= ~CDCE9XX_PDIV_MASK;
  168. val |= pdiv;
  169. ret = cdce9xx_reg_write(clk->dev, CDCE9XX_REG_PDIV(clk->id),
  170. val);
  171. if (ret)
  172. return ret;
  173. }
  174. return 0;
  175. }
  176. static const struct udevice_id cdce9xx_clk_of_match[] = {
  177. { .compatible = "ti,cdce913", .data = (u32)&cdce913_chip_info },
  178. { .compatible = "ti,cdce925", .data = (u32)&cdce925_chip_info },
  179. { .compatible = "ti,cdce937", .data = (u32)&cdce937_chip_info },
  180. { .compatible = "ti,cdce949", .data = (u32)&cdce949_chip_info },
  181. { /* sentinel */ },
  182. };
  183. static const struct clk_ops cdce9xx_clk_ops = {
  184. .of_xlate = cdce9xx_clk_of_xlate,
  185. .get_rate = cdce9xx_clk_get_rate,
  186. .set_rate = cdce9xx_clk_set_rate,
  187. };
  188. U_BOOT_DRIVER(cdce9xx_clk) = {
  189. .name = "cdce9xx-clk",
  190. .id = UCLASS_CLK,
  191. .of_match = cdce9xx_clk_of_match,
  192. .probe = cdce9xx_clk_probe,
  193. .priv_auto_alloc_size = sizeof(struct cdce9xx_clk_data),
  194. .ops = &cdce9xx_clk_ops,
  195. };