compat.c 22 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Compatible code for non CCF AT91 platforms.
  4. *
  5. * Copyright (C) 2020 Microchip Technology Inc. and its subsidiaries
  6. *
  7. * Author: Claudiu Beznea <claudiu.beznea@microchip.com>
  8. */
  9. #include <common.h>
  10. #include <clk-uclass.h>
  11. #include <dm.h>
  12. #include <dm/device_compat.h>
  13. #include <dm/lists.h>
  14. #include <dm/util.h>
  15. #include <mach/at91_pmc.h>
  16. #include <mach/at91_sfr.h>
  17. #include <regmap.h>
  18. #include <syscon.h>
  19. #include "pmc.h"
  20. DECLARE_GLOBAL_DATA_PTR;
  21. struct pmc_platdata {
  22. struct at91_pmc *reg_base;
  23. struct regmap *regmap_sfr;
  24. };
  25. static const struct udevice_id at91_pmc_match[] = {
  26. { .compatible = "atmel,at91rm9200-pmc" },
  27. { .compatible = "atmel,at91sam9260-pmc" },
  28. { .compatible = "atmel,at91sam9g45-pmc" },
  29. { .compatible = "atmel,at91sam9n12-pmc" },
  30. { .compatible = "atmel,at91sam9x5-pmc" },
  31. { .compatible = "atmel,sama5d3-pmc" },
  32. { .compatible = "atmel,sama5d2-pmc" },
  33. {}
  34. };
  35. U_BOOT_DRIVER(at91_pmc) = {
  36. .name = "at91-pmc",
  37. .id = UCLASS_SIMPLE_BUS,
  38. .of_match = at91_pmc_match,
  39. };
  40. static int at91_pmc_core_probe(struct udevice *dev)
  41. {
  42. struct pmc_platdata *plat = dev_get_platdata(dev);
  43. dev = dev_get_parent(dev);
  44. plat->reg_base = dev_read_addr_ptr(dev);
  45. return 0;
  46. }
  47. /**
  48. * at91_clk_sub_device_bind() - for the at91 clock driver
  49. * Recursively bind its children as clk devices.
  50. *
  51. * @return: 0 on success, or negative error code on failure
  52. */
  53. int at91_clk_sub_device_bind(struct udevice *dev, const char *drv_name)
  54. {
  55. const void *fdt = gd->fdt_blob;
  56. int offset = dev_of_offset(dev);
  57. bool pre_reloc_only = !(gd->flags & GD_FLG_RELOC);
  58. const char *name;
  59. int ret;
  60. for (offset = fdt_first_subnode(fdt, offset);
  61. offset > 0;
  62. offset = fdt_next_subnode(fdt, offset)) {
  63. if (pre_reloc_only &&
  64. !ofnode_pre_reloc(offset_to_ofnode(offset)))
  65. continue;
  66. /*
  67. * If this node has "compatible" property, this is not
  68. * a clock sub-node, but a normal device. skip.
  69. */
  70. fdt_get_property(fdt, offset, "compatible", &ret);
  71. if (ret >= 0)
  72. continue;
  73. if (ret != -FDT_ERR_NOTFOUND)
  74. return ret;
  75. name = fdt_get_name(fdt, offset, NULL);
  76. if (!name)
  77. return -EINVAL;
  78. ret = device_bind_driver_to_node(dev, drv_name, name,
  79. offset_to_ofnode(offset), NULL);
  80. if (ret)
  81. return ret;
  82. }
  83. return 0;
  84. }
  85. int at91_clk_of_xlate(struct clk *clk, struct ofnode_phandle_args *args)
  86. {
  87. int periph;
  88. if (args->args_count) {
  89. debug("Invalid args_count: %d\n", args->args_count);
  90. return -EINVAL;
  91. }
  92. periph = fdtdec_get_uint(gd->fdt_blob, dev_of_offset(clk->dev), "reg",
  93. -1);
  94. if (periph < 0)
  95. return -EINVAL;
  96. clk->id = periph;
  97. return 0;
  98. }
  99. int at91_clk_probe(struct udevice *dev)
  100. {
  101. struct udevice *dev_periph_container, *dev_pmc;
  102. struct pmc_platdata *plat = dev_get_platdata(dev);
  103. dev_periph_container = dev_get_parent(dev);
  104. dev_pmc = dev_get_parent(dev_periph_container);
  105. plat->reg_base = dev_read_addr_ptr(dev_pmc);
  106. return 0;
  107. }
  108. /* SCKC specific code. */
  109. static const struct udevice_id at91_sckc_match[] = {
  110. { .compatible = "atmel,at91sam9x5-sckc" },
  111. {}
  112. };
  113. U_BOOT_DRIVER(at91_sckc) = {
  114. .name = "at91-sckc",
  115. .id = UCLASS_SIMPLE_BUS,
  116. .of_match = at91_sckc_match,
  117. };
  118. /* Slow clock specific code. */
  119. static int at91_slow_clk_enable(struct clk *clk)
  120. {
  121. return 0;
  122. }
  123. static ulong at91_slow_clk_get_rate(struct clk *clk)
  124. {
  125. return CONFIG_SYS_AT91_SLOW_CLOCK;
  126. }
  127. static struct clk_ops at91_slow_clk_ops = {
  128. .enable = at91_slow_clk_enable,
  129. .get_rate = at91_slow_clk_get_rate,
  130. };
  131. static const struct udevice_id at91_slow_clk_match[] = {
  132. { .compatible = "atmel,at91sam9x5-clk-slow" },
  133. {}
  134. };
  135. U_BOOT_DRIVER(at91_slow_clk) = {
  136. .name = "at91-slow-clk",
  137. .id = UCLASS_CLK,
  138. .of_match = at91_slow_clk_match,
  139. .ops = &at91_slow_clk_ops,
  140. };
  141. /* Master clock specific code. */
  142. static ulong at91_master_clk_get_rate(struct clk *clk)
  143. {
  144. return gd->arch.mck_rate_hz;
  145. }
  146. static struct clk_ops at91_master_clk_ops = {
  147. .get_rate = at91_master_clk_get_rate,
  148. };
  149. static const struct udevice_id at91_master_clk_match[] = {
  150. { .compatible = "atmel,at91rm9200-clk-master" },
  151. { .compatible = "atmel,at91sam9x5-clk-master" },
  152. {}
  153. };
  154. U_BOOT_DRIVER(at91_master_clk) = {
  155. .name = "at91-master-clk",
  156. .id = UCLASS_CLK,
  157. .of_match = at91_master_clk_match,
  158. .ops = &at91_master_clk_ops,
  159. };
  160. /* Main osc clock specific code. */
  161. static int main_osc_clk_enable(struct clk *clk)
  162. {
  163. struct pmc_platdata *plat = dev_get_platdata(clk->dev);
  164. struct at91_pmc *pmc = plat->reg_base;
  165. if (readl(&pmc->sr) & AT91_PMC_MOSCSELS)
  166. return 0;
  167. return -EINVAL;
  168. }
  169. static ulong main_osc_clk_get_rate(struct clk *clk)
  170. {
  171. return gd->arch.main_clk_rate_hz;
  172. }
  173. static struct clk_ops main_osc_clk_ops = {
  174. .enable = main_osc_clk_enable,
  175. .get_rate = main_osc_clk_get_rate,
  176. };
  177. static int main_osc_clk_probe(struct udevice *dev)
  178. {
  179. return at91_pmc_core_probe(dev);
  180. }
  181. static const struct udevice_id main_osc_clk_match[] = {
  182. { .compatible = "atmel,at91sam9x5-clk-main" },
  183. {}
  184. };
  185. U_BOOT_DRIVER(at91sam9x5_main_osc_clk) = {
  186. .name = "at91sam9x5-main-osc-clk",
  187. .id = UCLASS_CLK,
  188. .of_match = main_osc_clk_match,
  189. .probe = main_osc_clk_probe,
  190. .platdata_auto_alloc_size = sizeof(struct pmc_platdata),
  191. .ops = &main_osc_clk_ops,
  192. };
  193. /* PLLA clock specific code. */
  194. static int plla_clk_enable(struct clk *clk)
  195. {
  196. struct pmc_platdata *plat = dev_get_platdata(clk->dev);
  197. struct at91_pmc *pmc = plat->reg_base;
  198. if (readl(&pmc->sr) & AT91_PMC_LOCKA)
  199. return 0;
  200. return -EINVAL;
  201. }
  202. static ulong plla_clk_get_rate(struct clk *clk)
  203. {
  204. return gd->arch.plla_rate_hz;
  205. }
  206. static struct clk_ops plla_clk_ops = {
  207. .enable = plla_clk_enable,
  208. .get_rate = plla_clk_get_rate,
  209. };
  210. static int plla_clk_probe(struct udevice *dev)
  211. {
  212. return at91_pmc_core_probe(dev);
  213. }
  214. static const struct udevice_id plla_clk_match[] = {
  215. { .compatible = "atmel,sama5d3-clk-pll" },
  216. {}
  217. };
  218. U_BOOT_DRIVER(at91_plla_clk) = {
  219. .name = "at91-plla-clk",
  220. .id = UCLASS_CLK,
  221. .of_match = plla_clk_match,
  222. .probe = plla_clk_probe,
  223. .platdata_auto_alloc_size = sizeof(struct pmc_platdata),
  224. .ops = &plla_clk_ops,
  225. };
  226. /* PLLA DIV clock specific code. */
  227. static int at91_plladiv_clk_enable(struct clk *clk)
  228. {
  229. return 0;
  230. }
  231. static ulong at91_plladiv_clk_get_rate(struct clk *clk)
  232. {
  233. struct pmc_platdata *plat = dev_get_platdata(clk->dev);
  234. struct at91_pmc *pmc = plat->reg_base;
  235. struct clk source;
  236. ulong clk_rate;
  237. int ret;
  238. ret = clk_get_by_index(clk->dev, 0, &source);
  239. if (ret)
  240. return -EINVAL;
  241. clk_rate = clk_get_rate(&source);
  242. if (readl(&pmc->mckr) & AT91_PMC_MCKR_PLLADIV_2)
  243. clk_rate /= 2;
  244. return clk_rate;
  245. }
  246. static ulong at91_plladiv_clk_set_rate(struct clk *clk, ulong rate)
  247. {
  248. struct pmc_platdata *plat = dev_get_platdata(clk->dev);
  249. struct at91_pmc *pmc = plat->reg_base;
  250. struct clk source;
  251. ulong parent_rate;
  252. int ret;
  253. ret = clk_get_by_index(clk->dev, 0, &source);
  254. if (ret)
  255. return -EINVAL;
  256. parent_rate = clk_get_rate(&source);
  257. if ((parent_rate != rate) && ((parent_rate) / 2 != rate))
  258. return -EINVAL;
  259. if (parent_rate != rate) {
  260. writel((readl(&pmc->mckr) | AT91_PMC_MCKR_PLLADIV_2),
  261. &pmc->mckr);
  262. }
  263. return 0;
  264. }
  265. static struct clk_ops at91_plladiv_clk_ops = {
  266. .enable = at91_plladiv_clk_enable,
  267. .get_rate = at91_plladiv_clk_get_rate,
  268. .set_rate = at91_plladiv_clk_set_rate,
  269. };
  270. static int at91_plladiv_clk_probe(struct udevice *dev)
  271. {
  272. return at91_pmc_core_probe(dev);
  273. }
  274. static const struct udevice_id at91_plladiv_clk_match[] = {
  275. { .compatible = "atmel,at91sam9x5-clk-plldiv" },
  276. {}
  277. };
  278. U_BOOT_DRIVER(at91_plladiv_clk) = {
  279. .name = "at91-plladiv-clk",
  280. .id = UCLASS_CLK,
  281. .of_match = at91_plladiv_clk_match,
  282. .probe = at91_plladiv_clk_probe,
  283. .platdata_auto_alloc_size = sizeof(struct pmc_platdata),
  284. .ops = &at91_plladiv_clk_ops,
  285. };
  286. /* System clock specific code. */
  287. #define SYSTEM_MAX_ID 31
  288. /**
  289. * at91_system_clk_bind() - for the system clock driver
  290. * Recursively bind its children as clk devices.
  291. *
  292. * @return: 0 on success, or negative error code on failure
  293. */
  294. static int at91_system_clk_bind(struct udevice *dev)
  295. {
  296. return at91_clk_sub_device_bind(dev, "system-clk");
  297. }
  298. static const struct udevice_id at91_system_clk_match[] = {
  299. { .compatible = "atmel,at91rm9200-clk-system" },
  300. {}
  301. };
  302. U_BOOT_DRIVER(at91_system_clk) = {
  303. .name = "at91-system-clk",
  304. .id = UCLASS_MISC,
  305. .of_match = at91_system_clk_match,
  306. .bind = at91_system_clk_bind,
  307. };
  308. static inline int is_pck(int id)
  309. {
  310. return (id >= 8) && (id <= 15);
  311. }
  312. static ulong system_clk_get_rate(struct clk *clk)
  313. {
  314. struct clk clk_dev;
  315. int ret;
  316. ret = clk_get_by_index(clk->dev, 0, &clk_dev);
  317. if (ret)
  318. return -EINVAL;
  319. return clk_get_rate(&clk_dev);
  320. }
  321. static ulong system_clk_set_rate(struct clk *clk, ulong rate)
  322. {
  323. struct clk clk_dev;
  324. int ret;
  325. ret = clk_get_by_index(clk->dev, 0, &clk_dev);
  326. if (ret)
  327. return -EINVAL;
  328. return clk_set_rate(&clk_dev, rate);
  329. }
  330. static int system_clk_enable(struct clk *clk)
  331. {
  332. struct pmc_platdata *plat = dev_get_platdata(clk->dev);
  333. struct at91_pmc *pmc = plat->reg_base;
  334. u32 mask;
  335. if (clk->id > SYSTEM_MAX_ID)
  336. return -EINVAL;
  337. mask = BIT(clk->id);
  338. writel(mask, &pmc->scer);
  339. /**
  340. * For the programmable clocks the Ready status in the PMC
  341. * status register should be checked after enabling.
  342. * For other clocks this is unnecessary.
  343. */
  344. if (!is_pck(clk->id))
  345. return 0;
  346. while (!(readl(&pmc->sr) & mask))
  347. ;
  348. return 0;
  349. }
  350. static struct clk_ops system_clk_ops = {
  351. .of_xlate = at91_clk_of_xlate,
  352. .get_rate = system_clk_get_rate,
  353. .set_rate = system_clk_set_rate,
  354. .enable = system_clk_enable,
  355. };
  356. U_BOOT_DRIVER(system_clk) = {
  357. .name = "system-clk",
  358. .id = UCLASS_CLK,
  359. .probe = at91_clk_probe,
  360. .platdata_auto_alloc_size = sizeof(struct pmc_platdata),
  361. .ops = &system_clk_ops,
  362. };
  363. /* Peripheral clock specific code. */
  364. #define PERIPHERAL_ID_MIN 2
  365. #define PERIPHERAL_ID_MAX 31
  366. #define PERIPHERAL_MASK(id) (1 << ((id) & PERIPHERAL_ID_MAX))
  367. enum periph_clk_type {
  368. CLK_PERIPH_AT91RM9200 = 0,
  369. CLK_PERIPH_AT91SAM9X5,
  370. };
  371. /**
  372. * sam9x5_periph_clk_bind() - for the periph clock driver
  373. * Recursively bind its children as clk devices.
  374. *
  375. * @return: 0 on success, or negative error code on failure
  376. */
  377. static int sam9x5_periph_clk_bind(struct udevice *dev)
  378. {
  379. return at91_clk_sub_device_bind(dev, "periph-clk");
  380. }
  381. static const struct udevice_id sam9x5_periph_clk_match[] = {
  382. {
  383. .compatible = "atmel,at91rm9200-clk-peripheral",
  384. .data = CLK_PERIPH_AT91RM9200,
  385. },
  386. {
  387. .compatible = "atmel,at91sam9x5-clk-peripheral",
  388. .data = CLK_PERIPH_AT91SAM9X5,
  389. },
  390. {}
  391. };
  392. U_BOOT_DRIVER(sam9x5_periph_clk) = {
  393. .name = "sam9x5-periph-clk",
  394. .id = UCLASS_MISC,
  395. .of_match = sam9x5_periph_clk_match,
  396. .bind = sam9x5_periph_clk_bind,
  397. };
  398. static int periph_clk_enable(struct clk *clk)
  399. {
  400. struct pmc_platdata *plat = dev_get_platdata(clk->dev);
  401. struct at91_pmc *pmc = plat->reg_base;
  402. enum periph_clk_type clk_type;
  403. void *addr;
  404. if (clk->id < PERIPHERAL_ID_MIN)
  405. return -1;
  406. clk_type = dev_get_driver_data(dev_get_parent(clk->dev));
  407. if (clk_type == CLK_PERIPH_AT91RM9200) {
  408. addr = &pmc->pcer;
  409. if (clk->id > PERIPHERAL_ID_MAX)
  410. addr = &pmc->pcer1;
  411. setbits_le32(addr, PERIPHERAL_MASK(clk->id));
  412. } else {
  413. writel(clk->id & AT91_PMC_PCR_PID_MASK, &pmc->pcr);
  414. setbits_le32(&pmc->pcr,
  415. AT91_PMC_PCR_CMD_WRITE | AT91_PMC_PCR_EN);
  416. }
  417. return 0;
  418. }
  419. static ulong periph_get_rate(struct clk *clk)
  420. {
  421. struct udevice *dev;
  422. struct clk clk_dev;
  423. ulong clk_rate;
  424. int ret;
  425. dev = dev_get_parent(clk->dev);
  426. ret = clk_get_by_index(dev, 0, &clk_dev);
  427. if (ret)
  428. return ret;
  429. clk_rate = clk_get_rate(&clk_dev);
  430. clk_free(&clk_dev);
  431. return clk_rate;
  432. }
  433. static struct clk_ops periph_clk_ops = {
  434. .of_xlate = at91_clk_of_xlate,
  435. .enable = periph_clk_enable,
  436. .get_rate = periph_get_rate,
  437. };
  438. U_BOOT_DRIVER(clk_periph) = {
  439. .name = "periph-clk",
  440. .id = UCLASS_CLK,
  441. .platdata_auto_alloc_size = sizeof(struct pmc_platdata),
  442. .probe = at91_clk_probe,
  443. .ops = &periph_clk_ops,
  444. };
  445. /* UTMI clock specific code. */
  446. #ifdef CONFIG_AT91_UTMI
  447. /*
  448. * The purpose of this clock is to generate a 480 MHz signal. A different
  449. * rate can't be configured.
  450. */
  451. #define UTMI_RATE 480000000
  452. static int utmi_clk_enable(struct clk *clk)
  453. {
  454. struct pmc_platdata *plat = dev_get_platdata(clk->dev);
  455. struct at91_pmc *pmc = plat->reg_base;
  456. struct clk clk_dev;
  457. ulong clk_rate;
  458. u32 utmi_ref_clk_freq;
  459. u32 tmp;
  460. int err;
  461. int timeout = 2000000;
  462. if (readl(&pmc->sr) & AT91_PMC_LOCKU)
  463. return 0;
  464. /*
  465. * If mainck rate is different from 12 MHz, we have to configure the
  466. * FREQ field of the SFR_UTMICKTRIM register to generate properly
  467. * the utmi clock.
  468. */
  469. err = clk_get_by_index(clk->dev, 0, &clk_dev);
  470. if (err)
  471. return -EINVAL;
  472. clk_rate = clk_get_rate(&clk_dev);
  473. switch (clk_rate) {
  474. case 12000000:
  475. utmi_ref_clk_freq = 0;
  476. break;
  477. case 16000000:
  478. utmi_ref_clk_freq = 1;
  479. break;
  480. case 24000000:
  481. utmi_ref_clk_freq = 2;
  482. break;
  483. /*
  484. * Not supported on SAMA5D2 but it's not an issue since MAINCK
  485. * maximum value is 24 MHz.
  486. */
  487. case 48000000:
  488. utmi_ref_clk_freq = 3;
  489. break;
  490. default:
  491. printf("UTMICK: unsupported mainck rate\n");
  492. return -EINVAL;
  493. }
  494. if (plat->regmap_sfr) {
  495. err = regmap_read(plat->regmap_sfr, AT91_SFR_UTMICKTRIM, &tmp);
  496. if (err)
  497. return -EINVAL;
  498. tmp &= ~AT91_UTMICKTRIM_FREQ;
  499. tmp |= utmi_ref_clk_freq;
  500. err = regmap_write(plat->regmap_sfr, AT91_SFR_UTMICKTRIM, tmp);
  501. if (err)
  502. return -EINVAL;
  503. } else if (utmi_ref_clk_freq) {
  504. printf("UTMICK: sfr node required\n");
  505. return -EINVAL;
  506. }
  507. tmp = readl(&pmc->uckr);
  508. tmp |= AT91_PMC_UPLLEN |
  509. AT91_PMC_UPLLCOUNT |
  510. AT91_PMC_BIASEN;
  511. writel(tmp, &pmc->uckr);
  512. while ((--timeout) && !(readl(&pmc->sr) & AT91_PMC_LOCKU))
  513. ;
  514. if (!timeout) {
  515. printf("UTMICK: timeout waiting for UPLL lock\n");
  516. return -ETIMEDOUT;
  517. }
  518. return 0;
  519. }
  520. static ulong utmi_clk_get_rate(struct clk *clk)
  521. {
  522. /* UTMI clk rate is fixed. */
  523. return UTMI_RATE;
  524. }
  525. static struct clk_ops utmi_clk_ops = {
  526. .enable = utmi_clk_enable,
  527. .get_rate = utmi_clk_get_rate,
  528. };
  529. static int utmi_clk_ofdata_to_platdata(struct udevice *dev)
  530. {
  531. struct pmc_platdata *plat = dev_get_platdata(dev);
  532. struct udevice *syscon;
  533. uclass_get_device_by_phandle(UCLASS_SYSCON, dev,
  534. "regmap-sfr", &syscon);
  535. if (syscon)
  536. plat->regmap_sfr = syscon_get_regmap(syscon);
  537. return 0;
  538. }
  539. static int utmi_clk_probe(struct udevice *dev)
  540. {
  541. return at91_pmc_core_probe(dev);
  542. }
  543. static const struct udevice_id utmi_clk_match[] = {
  544. { .compatible = "atmel,at91sam9x5-clk-utmi" },
  545. {}
  546. };
  547. U_BOOT_DRIVER(at91sam9x5_utmi_clk) = {
  548. .name = "at91sam9x5-utmi-clk",
  549. .id = UCLASS_CLK,
  550. .of_match = utmi_clk_match,
  551. .probe = utmi_clk_probe,
  552. .ofdata_to_platdata = utmi_clk_ofdata_to_platdata,
  553. .platdata_auto_alloc_size = sizeof(struct pmc_platdata),
  554. .ops = &utmi_clk_ops,
  555. };
  556. #endif /* CONFIG_AT91_UTMI */
  557. /* H32MX clock specific code. */
  558. #ifdef CONFIG_AT91_H32MX
  559. #define H32MX_MAX_FREQ 90000000
  560. static ulong sama5d4_h32mx_clk_get_rate(struct clk *clk)
  561. {
  562. struct pmc_platdata *plat = dev_get_platdata(clk->dev);
  563. struct at91_pmc *pmc = plat->reg_base;
  564. ulong rate = gd->arch.mck_rate_hz;
  565. if (readl(&pmc->mckr) & AT91_PMC_MCKR_H32MXDIV)
  566. rate /= 2;
  567. if (rate > H32MX_MAX_FREQ)
  568. dev_dbg(clk->dev, "H32MX clock is too fast\n");
  569. return rate;
  570. }
  571. static struct clk_ops sama5d4_h32mx_clk_ops = {
  572. .get_rate = sama5d4_h32mx_clk_get_rate,
  573. };
  574. static int sama5d4_h32mx_clk_probe(struct udevice *dev)
  575. {
  576. return at91_pmc_core_probe(dev);
  577. }
  578. static const struct udevice_id sama5d4_h32mx_clk_match[] = {
  579. { .compatible = "atmel,sama5d4-clk-h32mx" },
  580. {}
  581. };
  582. U_BOOT_DRIVER(sama5d4_h32mx_clk) = {
  583. .name = "sama5d4-h32mx-clk",
  584. .id = UCLASS_CLK,
  585. .of_match = sama5d4_h32mx_clk_match,
  586. .probe = sama5d4_h32mx_clk_probe,
  587. .platdata_auto_alloc_size = sizeof(struct pmc_platdata),
  588. .ops = &sama5d4_h32mx_clk_ops,
  589. };
  590. #endif /* CONFIG_AT91_H32MX */
  591. /* Generic clock specific code. */
  592. #ifdef CONFIG_AT91_GENERIC_CLK
  593. #define GENERATED_SOURCE_MAX 6
  594. #define GENERATED_MAX_DIV 255
  595. /**
  596. * generated_clk_bind() - for the generated clock driver
  597. * Recursively bind its children as clk devices.
  598. *
  599. * @return: 0 on success, or negative error code on failure
  600. */
  601. static int generated_clk_bind(struct udevice *dev)
  602. {
  603. return at91_clk_sub_device_bind(dev, "generic-clk");
  604. }
  605. static const struct udevice_id generated_clk_match[] = {
  606. { .compatible = "atmel,sama5d2-clk-generated" },
  607. {}
  608. };
  609. U_BOOT_DRIVER(generated_clk) = {
  610. .name = "generated-clk",
  611. .id = UCLASS_MISC,
  612. .of_match = generated_clk_match,
  613. .bind = generated_clk_bind,
  614. };
  615. struct generic_clk_priv {
  616. u32 num_parents;
  617. };
  618. static ulong generic_clk_get_rate(struct clk *clk)
  619. {
  620. struct pmc_platdata *plat = dev_get_platdata(clk->dev);
  621. struct at91_pmc *pmc = plat->reg_base;
  622. struct clk parent;
  623. ulong clk_rate;
  624. u32 tmp, gckdiv;
  625. u8 clock_source, parent_index;
  626. int ret;
  627. writel(clk->id & AT91_PMC_PCR_PID_MASK, &pmc->pcr);
  628. tmp = readl(&pmc->pcr);
  629. clock_source = (tmp >> AT91_PMC_PCR_GCKCSS_OFFSET) &
  630. AT91_PMC_PCR_GCKCSS_MASK;
  631. gckdiv = (tmp >> AT91_PMC_PCR_GCKDIV_OFFSET) & AT91_PMC_PCR_GCKDIV_MASK;
  632. parent_index = clock_source - 1;
  633. ret = clk_get_by_index(dev_get_parent(clk->dev), parent_index, &parent);
  634. if (ret)
  635. return 0;
  636. clk_rate = clk_get_rate(&parent) / (gckdiv + 1);
  637. clk_free(&parent);
  638. return clk_rate;
  639. }
  640. static ulong generic_clk_set_rate(struct clk *clk, ulong rate)
  641. {
  642. struct pmc_platdata *plat = dev_get_platdata(clk->dev);
  643. struct at91_pmc *pmc = plat->reg_base;
  644. struct generic_clk_priv *priv = dev_get_priv(clk->dev);
  645. struct clk parent, best_parent;
  646. ulong tmp_rate, best_rate = rate, parent_rate;
  647. int tmp_diff, best_diff = -1;
  648. u32 div, best_div = 0;
  649. u8 best_parent_index, best_clock_source = 0;
  650. u8 i;
  651. u32 tmp;
  652. int ret;
  653. for (i = 0; i < priv->num_parents; i++) {
  654. ret = clk_get_by_index(dev_get_parent(clk->dev), i, &parent);
  655. if (ret)
  656. return ret;
  657. parent_rate = clk_get_rate(&parent);
  658. if (IS_ERR_VALUE(parent_rate))
  659. return parent_rate;
  660. for (div = 1; div < GENERATED_MAX_DIV + 2; div++) {
  661. tmp_rate = DIV_ROUND_CLOSEST(parent_rate, div);
  662. tmp_diff = abs(rate - tmp_rate);
  663. if (best_diff < 0 || best_diff > tmp_diff) {
  664. best_rate = tmp_rate;
  665. best_diff = tmp_diff;
  666. best_div = div - 1;
  667. best_parent = parent;
  668. best_parent_index = i;
  669. best_clock_source = best_parent_index + 1;
  670. }
  671. if (!best_diff || tmp_rate < rate)
  672. break;
  673. }
  674. if (!best_diff)
  675. break;
  676. }
  677. debug("GCK: best parent: %s, best_rate = %ld, best_div = %d\n",
  678. best_parent.dev->name, best_rate, best_div);
  679. ret = clk_enable(&best_parent);
  680. if (ret)
  681. return ret;
  682. writel(clk->id & AT91_PMC_PCR_PID_MASK, &pmc->pcr);
  683. tmp = readl(&pmc->pcr);
  684. tmp &= ~(AT91_PMC_PCR_GCKDIV | AT91_PMC_PCR_GCKCSS);
  685. tmp |= AT91_PMC_PCR_GCKCSS_(best_clock_source) |
  686. AT91_PMC_PCR_CMD_WRITE |
  687. AT91_PMC_PCR_GCKDIV_(best_div) |
  688. AT91_PMC_PCR_GCKEN;
  689. writel(tmp, &pmc->pcr);
  690. while (!(readl(&pmc->sr) & AT91_PMC_GCKRDY))
  691. ;
  692. return 0;
  693. }
  694. static struct clk_ops generic_clk_ops = {
  695. .of_xlate = at91_clk_of_xlate,
  696. .get_rate = generic_clk_get_rate,
  697. .set_rate = generic_clk_set_rate,
  698. };
  699. static int generic_clk_ofdata_to_platdata(struct udevice *dev)
  700. {
  701. struct generic_clk_priv *priv = dev_get_priv(dev);
  702. u32 cells[GENERATED_SOURCE_MAX];
  703. u32 num_parents;
  704. num_parents = fdtdec_get_int_array_count(gd->fdt_blob,
  705. dev_of_offset(dev_get_parent(dev)), "clocks", cells,
  706. GENERATED_SOURCE_MAX);
  707. if (!num_parents)
  708. return -1;
  709. priv->num_parents = num_parents;
  710. return 0;
  711. }
  712. U_BOOT_DRIVER(generic_clk) = {
  713. .name = "generic-clk",
  714. .id = UCLASS_CLK,
  715. .probe = at91_clk_probe,
  716. .ofdata_to_platdata = generic_clk_ofdata_to_platdata,
  717. .priv_auto_alloc_size = sizeof(struct generic_clk_priv),
  718. .platdata_auto_alloc_size = sizeof(struct pmc_platdata),
  719. .ops = &generic_clk_ops,
  720. };
  721. #endif /* CONFIG_AT91_GENERIC_CLK */
  722. /* USB clock specific code. */
  723. #ifdef CONFIG_AT91_USB_CLK
  724. #define AT91_USB_CLK_SOURCE_MAX 2
  725. #define AT91_USB_CLK_MAX_DIV 15
  726. struct at91_usb_clk_priv {
  727. u32 num_clksource;
  728. };
  729. static ulong at91_usb_clk_get_rate(struct clk *clk)
  730. {
  731. struct pmc_platdata *plat = dev_get_platdata(clk->dev);
  732. struct at91_pmc *pmc = plat->reg_base;
  733. struct clk source;
  734. u32 tmp, usbdiv;
  735. u8 source_index;
  736. int ret;
  737. tmp = readl(&pmc->pcr);
  738. source_index = (tmp >> AT91_PMC_USB_USBS_OFFSET) &
  739. AT91_PMC_USB_USBS_MASK;
  740. usbdiv = (tmp >> AT91_PMC_USB_DIV_OFFSET) & AT91_PMC_USB_DIV_MASK;
  741. ret = clk_get_by_index(clk->dev, source_index, &source);
  742. if (ret)
  743. return 0;
  744. return clk_get_rate(&source) / (usbdiv + 1);
  745. }
  746. static ulong at91_usb_clk_set_rate(struct clk *clk, ulong rate)
  747. {
  748. struct pmc_platdata *plat = dev_get_platdata(clk->dev);
  749. struct at91_pmc *pmc = plat->reg_base;
  750. struct at91_usb_clk_priv *priv = dev_get_priv(clk->dev);
  751. struct clk source, best_source;
  752. ulong tmp_rate, best_rate = rate, source_rate;
  753. int tmp_diff, best_diff = -1;
  754. u32 div, best_div = 0;
  755. u8 best_source_index = 0;
  756. u8 i;
  757. u32 tmp;
  758. int ret;
  759. for (i = 0; i < priv->num_clksource; i++) {
  760. ret = clk_get_by_index(clk->dev, i, &source);
  761. if (ret)
  762. return ret;
  763. source_rate = clk_get_rate(&source);
  764. if (IS_ERR_VALUE(source_rate))
  765. return source_rate;
  766. for (div = 1; div < AT91_USB_CLK_MAX_DIV + 2; div++) {
  767. tmp_rate = DIV_ROUND_CLOSEST(source_rate, div);
  768. tmp_diff = abs(rate - tmp_rate);
  769. if (best_diff < 0 || best_diff > tmp_diff) {
  770. best_rate = tmp_rate;
  771. best_diff = tmp_diff;
  772. best_div = div - 1;
  773. best_source = source;
  774. best_source_index = i;
  775. }
  776. if (!best_diff || tmp_rate < rate)
  777. break;
  778. }
  779. if (!best_diff)
  780. break;
  781. }
  782. debug("AT91 USB: best sourc: %s, best_rate = %ld, best_div = %d\n",
  783. best_source.dev->name, best_rate, best_div);
  784. ret = clk_enable(&best_source);
  785. if (ret)
  786. return ret;
  787. tmp = AT91_PMC_USB_USBS_(best_source_index) |
  788. AT91_PMC_USB_DIV_(best_div);
  789. writel(tmp, &pmc->usb);
  790. return 0;
  791. }
  792. static struct clk_ops at91_usb_clk_ops = {
  793. .get_rate = at91_usb_clk_get_rate,
  794. .set_rate = at91_usb_clk_set_rate,
  795. };
  796. static int at91_usb_clk_ofdata_to_platdata(struct udevice *dev)
  797. {
  798. struct at91_usb_clk_priv *priv = dev_get_priv(dev);
  799. u32 cells[AT91_USB_CLK_SOURCE_MAX];
  800. u32 num_clksource;
  801. num_clksource = fdtdec_get_int_array_count(gd->fdt_blob,
  802. dev_of_offset(dev),
  803. "clocks", cells,
  804. AT91_USB_CLK_SOURCE_MAX);
  805. if (!num_clksource)
  806. return -1;
  807. priv->num_clksource = num_clksource;
  808. return 0;
  809. }
  810. static int at91_usb_clk_probe(struct udevice *dev)
  811. {
  812. return at91_pmc_core_probe(dev);
  813. }
  814. static const struct udevice_id at91_usb_clk_match[] = {
  815. { .compatible = "atmel,at91sam9x5-clk-usb" },
  816. {}
  817. };
  818. U_BOOT_DRIVER(at91_usb_clk) = {
  819. .name = "at91-usb-clk",
  820. .id = UCLASS_CLK,
  821. .of_match = at91_usb_clk_match,
  822. .probe = at91_usb_clk_probe,
  823. .ofdata_to_platdata = at91_usb_clk_ofdata_to_platdata,
  824. .priv_auto_alloc_size = sizeof(struct at91_usb_clk_priv),
  825. .platdata_auto_alloc_size = sizeof(struct pmc_platdata),
  826. .ops = &at91_usb_clk_ops,
  827. };
  828. #endif /* CONFIG_AT91_USB_CLK */