cache-v5l2.c 4.5 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * Copyright (C) 2019 Andes Technology Corporation
  4. * Rick Chen, Andes Technology Corporation <rick@andestech.com>
  5. */
  6. #include <common.h>
  7. #include <command.h>
  8. #include <cache.h>
  9. #include <dm.h>
  10. #include <hang.h>
  11. #include <asm/io.h>
  12. #include <dm/ofnode.h>
  13. #include <linux/bitops.h>
  14. struct l2cache {
  15. volatile u64 configure;
  16. volatile u64 control;
  17. volatile u64 hpm0;
  18. volatile u64 hpm1;
  19. volatile u64 hpm2;
  20. volatile u64 hpm3;
  21. volatile u64 error_status;
  22. volatile u64 ecc_error;
  23. volatile u64 cctl_command0;
  24. volatile u64 cctl_access_line0;
  25. volatile u64 cctl_command1;
  26. volatile u64 cctl_access_line1;
  27. volatile u64 cctl_command2;
  28. volatile u64 cctl_access_line2;
  29. volatile u64 cctl_command3;
  30. volatile u64 cctl_access_line4;
  31. volatile u64 cctl_status;
  32. };
  33. /* Control Register */
  34. #define L2_ENABLE 0x1
  35. /* prefetch */
  36. #define IPREPETCH_OFF 3
  37. #define DPREPETCH_OFF 5
  38. #define IPREPETCH_MSK (3 << IPREPETCH_OFF)
  39. #define DPREPETCH_MSK (3 << DPREPETCH_OFF)
  40. /* tag ram */
  41. #define TRAMOCTL_OFF 8
  42. #define TRAMICTL_OFF 10
  43. #define TRAMOCTL_MSK (3 << TRAMOCTL_OFF)
  44. #define TRAMICTL_MSK BIT(TRAMICTL_OFF)
  45. /* data ram */
  46. #define DRAMOCTL_OFF 11
  47. #define DRAMICTL_OFF 13
  48. #define DRAMOCTL_MSK (3 << DRAMOCTL_OFF)
  49. #define DRAMICTL_MSK BIT(DRAMICTL_OFF)
  50. /* CCTL Command Register */
  51. #define CCTL_CMD_REG(base, hart) ((ulong)(base) + 0x40 + (hart) * 0x10)
  52. #define L2_WBINVAL_ALL 0x12
  53. /* CCTL Status Register */
  54. #define CCTL_STATUS_MSK(hart) (0xf << ((hart) * 4))
  55. #define CCTL_STATUS_IDLE(hart) (0 << ((hart) * 4))
  56. #define CCTL_STATUS_PROCESS(hart) (1 << ((hart) * 4))
  57. #define CCTL_STATUS_ILLEGAL(hart) (2 << ((hart) * 4))
  58. DECLARE_GLOBAL_DATA_PTR;
  59. struct v5l2_plat {
  60. struct l2cache *regs;
  61. u32 iprefetch;
  62. u32 dprefetch;
  63. u32 tram_ctl[2];
  64. u32 dram_ctl[2];
  65. };
  66. static int v5l2_enable(struct udevice *dev)
  67. {
  68. struct v5l2_plat *plat = dev_get_platdata(dev);
  69. volatile struct l2cache *regs = plat->regs;
  70. if (regs)
  71. setbits_le32(&regs->control, L2_ENABLE);
  72. return 0;
  73. }
  74. static int v5l2_disable(struct udevice *dev)
  75. {
  76. struct v5l2_plat *plat = dev_get_platdata(dev);
  77. volatile struct l2cache *regs = plat->regs;
  78. u8 hart = gd->arch.boot_hart;
  79. void __iomem *cctlcmd = (void __iomem *)CCTL_CMD_REG(regs, hart);
  80. if ((regs) && (readl(&regs->control) & L2_ENABLE)) {
  81. writel(L2_WBINVAL_ALL, cctlcmd);
  82. while ((readl(&regs->cctl_status) & CCTL_STATUS_MSK(hart))) {
  83. if ((readl(&regs->cctl_status) & CCTL_STATUS_ILLEGAL(hart))) {
  84. printf("L2 flush illegal! hanging...");
  85. hang();
  86. }
  87. }
  88. clrbits_le32(&regs->control, L2_ENABLE);
  89. }
  90. return 0;
  91. }
  92. static int v5l2_ofdata_to_platdata(struct udevice *dev)
  93. {
  94. struct v5l2_plat *plat = dev_get_platdata(dev);
  95. struct l2cache *regs;
  96. regs = (struct l2cache *)dev_read_addr(dev);
  97. plat->regs = regs;
  98. plat->iprefetch = -EINVAL;
  99. plat->dprefetch = -EINVAL;
  100. plat->tram_ctl[0] = -EINVAL;
  101. plat->dram_ctl[0] = -EINVAL;
  102. /* Instruction and data fetch prefetch depth */
  103. dev_read_u32(dev, "andes,inst-prefetch", &plat->iprefetch);
  104. dev_read_u32(dev, "andes,data-prefetch", &plat->dprefetch);
  105. /* Set tag RAM and data RAM setup and output cycle */
  106. dev_read_u32_array(dev, "andes,tag-ram-ctl", plat->tram_ctl, 2);
  107. dev_read_u32_array(dev, "andes,data-ram-ctl", plat->dram_ctl, 2);
  108. return 0;
  109. }
  110. static int v5l2_probe(struct udevice *dev)
  111. {
  112. struct v5l2_plat *plat = dev_get_platdata(dev);
  113. struct l2cache *regs = plat->regs;
  114. u32 ctl_val;
  115. ctl_val = readl(&regs->control);
  116. if (!(ctl_val & L2_ENABLE))
  117. ctl_val |= L2_ENABLE;
  118. if (plat->iprefetch != -EINVAL) {
  119. ctl_val &= ~(IPREPETCH_MSK);
  120. ctl_val |= (plat->iprefetch << IPREPETCH_OFF);
  121. }
  122. if (plat->dprefetch != -EINVAL) {
  123. ctl_val &= ~(DPREPETCH_MSK);
  124. ctl_val |= (plat->dprefetch << DPREPETCH_OFF);
  125. }
  126. if (plat->tram_ctl[0] != -EINVAL) {
  127. ctl_val &= ~(TRAMOCTL_MSK | TRAMICTL_MSK);
  128. ctl_val |= plat->tram_ctl[0] << TRAMOCTL_OFF;
  129. ctl_val |= plat->tram_ctl[1] << TRAMICTL_OFF;
  130. }
  131. if (plat->dram_ctl[0] != -EINVAL) {
  132. ctl_val &= ~(DRAMOCTL_MSK | DRAMICTL_MSK);
  133. ctl_val |= plat->dram_ctl[0] << DRAMOCTL_OFF;
  134. ctl_val |= plat->dram_ctl[1] << DRAMICTL_OFF;
  135. }
  136. writel(ctl_val, &regs->control);
  137. return 0;
  138. }
  139. static const struct udevice_id v5l2_cache_ids[] = {
  140. { .compatible = "v5l2cache" },
  141. {}
  142. };
  143. static const struct cache_ops v5l2_cache_ops = {
  144. .enable = v5l2_enable,
  145. .disable = v5l2_disable,
  146. };
  147. U_BOOT_DRIVER(v5l2_cache) = {
  148. .name = "v5l2_cache",
  149. .id = UCLASS_CACHE,
  150. .of_match = v5l2_cache_ids,
  151. .ofdata_to_platdata = v5l2_ofdata_to_platdata,
  152. .probe = v5l2_probe,
  153. .platdata_auto_alloc_size = sizeof(struct v5l2_plat),
  154. .ops = &v5l2_cache_ops,
  155. .flags = DM_FLAG_PRE_RELOC,
  156. };