sata_sil3114.h 3.7 KB

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  1. /* SPDX-License-Identifier: GPL-2.0+ */
  2. /*
  3. * Copyright (C) Excito Elektronik i Skåne AB, All rights reserved.
  4. * Author: Tor Krill <tor@excito.com>
  5. */
  6. #ifndef SATA_SIL3114_H
  7. #define SATA_SIL3114_H
  8. struct sata_ioports {
  9. unsigned long cmd_addr;
  10. unsigned long data_addr;
  11. unsigned long error_addr;
  12. unsigned long feature_addr;
  13. unsigned long nsect_addr;
  14. unsigned long lbal_addr;
  15. unsigned long lbam_addr;
  16. unsigned long lbah_addr;
  17. unsigned long device_addr;
  18. unsigned long status_addr;
  19. unsigned long command_addr;
  20. unsigned long altstatus_addr;
  21. unsigned long ctl_addr;
  22. unsigned long bmdma_addr;
  23. unsigned long scr_addr;
  24. };
  25. struct sata_port {
  26. unsigned char port_no; /* primary=0, secondary=1 */
  27. struct sata_ioports ioaddr; /* ATA cmd/ctl/dma reg blks */
  28. unsigned char ctl_reg;
  29. unsigned char last_ctl;
  30. unsigned char port_state; /* 1-port is available and */
  31. /* 0-port is not available */
  32. unsigned char dev_mask;
  33. };
  34. /* Missing ata defines */
  35. #define ATA_CMD_STANDBY 0xE2
  36. #define ATA_CMD_STANDBYNOW1 0xE0
  37. #define ATA_CMD_IDLE 0xE3
  38. #define ATA_CMD_IDLEIMMEDIATE 0xE1
  39. /* Defines for SIL3114 chip */
  40. /* PCI defines */
  41. #define SIL_VEND_ID 0x1095
  42. #define SIL3114_DEVICE_ID 0x3114
  43. /* some vendor specific registers */
  44. #define VND_SYSCONFSTAT 0x88 /* System Configuration Status and Command */
  45. #define VND_SYSCONFSTAT_CHN_0_INTBLOCK (1<<22)
  46. #define VND_SYSCONFSTAT_CHN_1_INTBLOCK (1<<23)
  47. #define VND_SYSCONFSTAT_CHN_2_INTBLOCK (1<<24)
  48. #define VND_SYSCONFSTAT_CHN_3_INTBLOCK (1<<25)
  49. /* internal registers mapped by BAR5 */
  50. /* SATA Control*/
  51. #define VND_SCONTROL_CH0 0x100
  52. #define VND_SCONTROL_CH1 0x180
  53. #define VND_SCONTROL_CH2 0x300
  54. #define VND_SCONTROL_CH3 0x380
  55. #define SATA_SC_IPM_T2P (1<<16)
  56. #define SATA_SC_IPM_T2S (2<<16)
  57. #define SATA_SC_SPD_1_5 (1<<4)
  58. #define SATA_SC_SPD_3_0 (2<<4)
  59. #define SATA_SC_DET_RST (1) /* ATA Reset sequence */
  60. #define SATA_SC_DET_PDIS (4) /* PHY Disable */
  61. /* SATA Status */
  62. #define VND_SSTATUS_CH0 0x104
  63. #define VND_SSTATUS_CH1 0x184
  64. #define VND_SSTATUS_CH2 0x304
  65. #define VND_SSTATUS_CH3 0x384
  66. #define SATA_SS_IPM_ACTIVE (1<<8)
  67. #define SATA_SS_IPM_PARTIAL (2<<8)
  68. #define SATA_SS_IPM_SLUMBER (6<<8)
  69. #define SATA_SS_SPD_1_5 (1<<4)
  70. #define SATA_SS_SPD_3_0 (2<<4)
  71. #define SATA_DET_P_NOPHY (1) /* Device presence but no PHY connection established */
  72. #define SATA_DET_PRES (3) /* Device presence and active PHY */
  73. #define SATA_DET_OFFLINE (4) /* Device offline or in loopback mode */
  74. /* Task file registers in BAR5 mapping */
  75. #define VND_TF0_CH0 0x80
  76. #define VND_TF0_CH1 0xc0
  77. #define VND_TF0_CH2 0x280
  78. #define VND_TF0_CH3 0x2c0
  79. #define VND_TF1_CH0 0x88
  80. #define VND_TF1_CH1 0xc8
  81. #define VND_TF1_CH2 0x288
  82. #define VND_TF1_CH3 0x2c8
  83. #define VND_TF2_CH0 0x88
  84. #define VND_TF2_CH1 0xc8
  85. #define VND_TF2_CH2 0x288
  86. #define VND_TF2_CH3 0x2c8
  87. #define VND_BMDMA_CH0 0x00
  88. #define VND_BMDMA_CH1 0x08
  89. #define VND_BMDMA_CH2 0x200
  90. #define VND_BMDMA_CH3 0x208
  91. #define VND_BMDMA2_CH0 0x10
  92. #define VND_BMDMA2_CH1 0x18
  93. #define VND_BMDMA2_CH2 0x210
  94. #define VND_BMDMA2_CH3 0x218
  95. /* FIFO control */
  96. #define VND_FIFOCFG_CH0 0x40
  97. #define VND_FIFOCFG_CH1 0x44
  98. #define VND_FIFOCFG_CH2 0x240
  99. #define VND_FIFOCFG_CH3 0x244
  100. /* Task File configuration and status */
  101. #define VND_TF_CNST_CH0 0xa0
  102. #define VND_TF_CNST_CH1 0xe0
  103. #define VND_TF_CNST_CH2 0x2a0
  104. #define VND_TF_CNST_CH3 0x2e0
  105. #define VND_TF_CNST_BFCMD (1<<1)
  106. #define VND_TF_CNST_CHNRST (1<<2)
  107. #define VND_TF_CNST_VDMA (1<<10)
  108. #define VND_TF_CNST_INTST (1<<11)
  109. #define VND_TF_CNST_WDTO (1<<12)
  110. #define VND_TF_CNST_WDEN (1<<13)
  111. #define VND_TF_CNST_WDIEN (1<<14)
  112. /* for testing */
  113. #define VND_SSDR 0x04c /* System Software Data Register */
  114. #define VND_FMACS 0x050 /* Flash Memory Address control and status */
  115. #endif