sata_sil.c 22 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330331332333334335336337338339340341342343344345346347348349350351352353354355356357358359360361362363364365366367368369370371372373374375376377378379380381382383384385386387388389390391392393394395396397398399400401402403404405406407408409410411412413414415416417418419420421422423424425426427428429430431432433434435436437438439440441442443444445446447448449450451452453454455456457458459460461462463464465466467468469470471472473474475476477478479480481482483484485486487488489490491492493494495496497498499500501502503504505506507508509510511512513514515516517518519520521522523524525526527528529530531532533534535536537538539540541542543544545546547548549550551552553554555556557558559560561562563564565566567568569570571572573574575576577578579580581582583584585586587588589590591592593594595596597598599600601602603604605606607608609610611612613614615616617618619620621622623624625626627628629630631632633634635636637638639640641642643644645646647648649650651652653654655656657658659660661662663664665666667668669670671672673674675676677678679680681682683684685686687688689690691692693694695696697698699700701702703704705706707708709710711712713714715716717718719720721722723724725726727728729730731732733734735736737738739740741742743744745746747748749750751752753754755756757758759760761762763764765766767768769770771772773774775776777778779780781782783784785786787788789790791792793794795796797798799800801802803804805806807808809810811812813814815816817818819820821822823824825826827828829830831832833834835836837838839840841842843844845846847848849850851852853854855856857858859860861862863864865866867868869870871872873874875876877878879880881882883884885886887888889890891892893894895896897898899900901902903904905906907908909910911912913914915916917918919920921922923924925926927
  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright (C) 2011 Freescale Semiconductor, Inc.
  4. * Copyright 2019 NXP
  5. * Author: Tang Yuantian <b29983@freescale.com>
  6. */
  7. #include <common.h>
  8. #include <cpu_func.h>
  9. #include <log.h>
  10. #include <pci.h>
  11. #include <command.h>
  12. #include <asm/byteorder.h>
  13. #include <malloc.h>
  14. #include <asm/io.h>
  15. #include <fis.h>
  16. #include <sata.h>
  17. #include <libata.h>
  18. #include <sata.h>
  19. #include <linux/delay.h>
  20. #if CONFIG_IS_ENABLED(BLK)
  21. #include <dm.h>
  22. #include <blk.h>
  23. #include <dm/device-internal.h>
  24. #endif
  25. #include "sata_sil.h"
  26. #ifdef CONFIG_DM_PCI
  27. #define virt_to_bus(devno, v) dm_pci_virt_to_mem(devno, (void *) (v))
  28. #else
  29. #define virt_to_bus(devno, v) pci_virt_to_mem(devno, (void *) (v))
  30. #endif
  31. /* just compatible ahci_ops */
  32. struct sil_ops {
  33. int *rev0;
  34. int *rev1;
  35. int (*scan)(struct udevice *dev);
  36. };
  37. static struct sata_info sata_info;
  38. static struct pci_device_id supported[] = {
  39. { PCI_DEVICE(PCI_VENDOR_ID_SILICONIMAGE, PCI_DEVICE_ID_SIL3131) },
  40. { PCI_DEVICE(PCI_VENDOR_ID_SILICONIMAGE, PCI_DEVICE_ID_SIL3132) },
  41. { PCI_DEVICE(PCI_VENDOR_ID_SILICONIMAGE, PCI_DEVICE_ID_SIL3124) },
  42. {}
  43. };
  44. static void sil_sata_dump_fis(struct sata_fis_d2h *s)
  45. {
  46. printf("Status FIS dump:\n");
  47. printf("fis_type: %02x\n", s->fis_type);
  48. printf("pm_port_i: %02x\n", s->pm_port_i);
  49. printf("status: %02x\n", s->status);
  50. printf("error: %02x\n", s->error);
  51. printf("lba_low: %02x\n", s->lba_low);
  52. printf("lba_mid: %02x\n", s->lba_mid);
  53. printf("lba_high: %02x\n", s->lba_high);
  54. printf("device: %02x\n", s->device);
  55. printf("lba_low_exp: %02x\n", s->lba_low_exp);
  56. printf("lba_mid_exp: %02x\n", s->lba_mid_exp);
  57. printf("lba_high_exp: %02x\n", s->lba_high_exp);
  58. printf("res1: %02x\n", s->res1);
  59. printf("sector_count: %02x\n", s->sector_count);
  60. printf("sector_count_exp: %02x\n", s->sector_count_exp);
  61. }
  62. static const char *sata_spd_string(unsigned int speed)
  63. {
  64. static const char * const spd_str[] = {
  65. "1.5 Gbps",
  66. "3.0 Gbps",
  67. "6.0 Gbps",
  68. };
  69. if ((speed - 1) > 2)
  70. return "<unknown>";
  71. return spd_str[speed - 1];
  72. }
  73. static u32 ata_wait_register(void *reg, u32 mask,
  74. u32 val, int timeout_msec)
  75. {
  76. u32 tmp;
  77. tmp = readl(reg);
  78. while ((tmp & mask) == val && timeout_msec > 0) {
  79. mdelay(1);
  80. timeout_msec--;
  81. tmp = readl(reg);
  82. }
  83. return tmp;
  84. }
  85. static void sil_config_port(void *port)
  86. {
  87. /* configure IRQ WoC */
  88. writel(PORT_CS_IRQ_WOC, port + PORT_CTRL_CLR);
  89. /* zero error counters. */
  90. writew(0x8000, port + PORT_DECODE_ERR_THRESH);
  91. writew(0x8000, port + PORT_CRC_ERR_THRESH);
  92. writew(0x8000, port + PORT_HSHK_ERR_THRESH);
  93. writew(0x0000, port + PORT_DECODE_ERR_CNT);
  94. writew(0x0000, port + PORT_CRC_ERR_CNT);
  95. writew(0x0000, port + PORT_HSHK_ERR_CNT);
  96. /* always use 64bit activation */
  97. writel(PORT_CS_32BIT_ACTV, port + PORT_CTRL_CLR);
  98. /* clear port multiplier enable and resume bits */
  99. writel(PORT_CS_PMP_EN | PORT_CS_PMP_RESUME, port + PORT_CTRL_CLR);
  100. }
  101. static int sil_init_port(void *port)
  102. {
  103. u32 tmp;
  104. writel(PORT_CS_INIT, port + PORT_CTRL_STAT);
  105. ata_wait_register(port + PORT_CTRL_STAT,
  106. PORT_CS_INIT, PORT_CS_INIT, 100);
  107. tmp = ata_wait_register(port + PORT_CTRL_STAT,
  108. PORT_CS_RDY, 0, 100);
  109. if ((tmp & (PORT_CS_INIT | PORT_CS_RDY)) != PORT_CS_RDY)
  110. return 1;
  111. return 0;
  112. }
  113. static void sil_read_fis(struct sil_sata *sata, int tag,
  114. struct sata_fis_d2h *fis)
  115. {
  116. void *port = sata->port;
  117. struct sil_prb *prb;
  118. int i;
  119. u32 *src, *dst;
  120. prb = port + PORT_LRAM + tag * PORT_LRAM_SLOT_SZ;
  121. src = (u32 *)&prb->fis;
  122. dst = (u32 *)fis;
  123. for (i = 0; i < sizeof(struct sata_fis_h2d); i += 4)
  124. *dst++ = readl(src++);
  125. }
  126. static int sil_exec_cmd(struct sil_sata *sata, struct sil_cmd_block *pcmd,
  127. int tag)
  128. {
  129. void *port = sata->port;
  130. u64 paddr = virt_to_bus(sata->devno, pcmd);
  131. u32 irq_mask, irq_stat;
  132. int rc;
  133. writel(PORT_IRQ_COMPLETE | PORT_IRQ_ERROR, port + PORT_IRQ_ENABLE_CLR);
  134. /* better to add momery barrior here */
  135. writel((u32)paddr, port + PORT_CMD_ACTIVATE + tag * 8);
  136. writel((u64)paddr >> 32, port + PORT_CMD_ACTIVATE + tag * 8 + 4);
  137. irq_mask = (PORT_IRQ_COMPLETE | PORT_IRQ_ERROR) << PORT_IRQ_RAW_SHIFT;
  138. irq_stat = ata_wait_register(port + PORT_IRQ_STAT, irq_mask,
  139. 0, 10000);
  140. /* clear IRQs */
  141. writel(irq_mask, port + PORT_IRQ_STAT);
  142. irq_stat >>= PORT_IRQ_RAW_SHIFT;
  143. if (irq_stat & PORT_IRQ_COMPLETE)
  144. rc = 0;
  145. else {
  146. /* force port into known state */
  147. sil_init_port(port);
  148. if (irq_stat & PORT_IRQ_ERROR)
  149. rc = 1; /* error */
  150. else
  151. rc = 2; /* busy */
  152. }
  153. return rc;
  154. }
  155. static int sil_cmd_set_feature(struct sil_sata *sata)
  156. {
  157. struct sil_cmd_block cmdb, *pcmd = &cmdb;
  158. struct sata_fis_d2h fis;
  159. u8 udma_cap;
  160. int ret;
  161. memset((void *)&cmdb, 0, sizeof(struct sil_cmd_block));
  162. pcmd->prb.fis.fis_type = SATA_FIS_TYPE_REGISTER_H2D;
  163. pcmd->prb.fis.pm_port_c = (1 << 7);
  164. pcmd->prb.fis.command = ATA_CMD_SET_FEATURES;
  165. pcmd->prb.fis.features = SETFEATURES_XFER;
  166. /* First check the device capablity */
  167. udma_cap = (u8)(sata->udma & 0xff);
  168. debug("udma_cap %02x\n", udma_cap);
  169. if (udma_cap == ATA_UDMA6)
  170. pcmd->prb.fis.sector_count = XFER_UDMA_6;
  171. if (udma_cap == ATA_UDMA5)
  172. pcmd->prb.fis.sector_count = XFER_UDMA_5;
  173. if (udma_cap == ATA_UDMA4)
  174. pcmd->prb.fis.sector_count = XFER_UDMA_4;
  175. if (udma_cap == ATA_UDMA3)
  176. pcmd->prb.fis.sector_count = XFER_UDMA_3;
  177. ret = sil_exec_cmd(sata, pcmd, 0);
  178. if (ret) {
  179. sil_read_fis(sata, 0, &fis);
  180. printf("Err: exe cmd(0x%x).\n",
  181. readl(sata->port + PORT_SERROR));
  182. sil_sata_dump_fis(&fis);
  183. return 1;
  184. }
  185. return 0;
  186. }
  187. static void sil_sata_init_wcache(struct sil_sata *sata, u16 *id)
  188. {
  189. if (ata_id_has_wcache(id) && ata_id_wcache_enabled(id))
  190. sata->wcache = 1;
  191. if (ata_id_has_flush(id))
  192. sata->flush = 1;
  193. if (ata_id_has_flush_ext(id))
  194. sata->flush_ext = 1;
  195. }
  196. static void sil_sata_set_feature_by_id(struct sil_sata *sata, u16 *id)
  197. {
  198. #ifdef CONFIG_LBA48
  199. /* Check if support LBA48 */
  200. if (ata_id_has_lba48(id)) {
  201. sata->lba48 = 1;
  202. debug("Device supports LBA48\n");
  203. } else {
  204. debug("Device supports LBA28\n");
  205. }
  206. #endif
  207. sil_sata_init_wcache(sata, id);
  208. sil_cmd_set_feature(sata);
  209. }
  210. static int sil_cmd_identify_device(struct sil_sata *sata, u16 *id)
  211. {
  212. struct sil_cmd_block cmdb, *pcmd = &cmdb;
  213. struct sata_fis_d2h fis;
  214. int ret;
  215. memset((void *)&cmdb, 0, sizeof(struct sil_cmd_block));
  216. pcmd->prb.ctrl = cpu_to_le16(PRB_CTRL_PROTOCOL);
  217. pcmd->prb.prot = cpu_to_le16(PRB_PROT_READ);
  218. pcmd->prb.fis.fis_type = SATA_FIS_TYPE_REGISTER_H2D;
  219. pcmd->prb.fis.pm_port_c = (1 << 7);
  220. pcmd->prb.fis.command = ATA_CMD_ID_ATA;
  221. pcmd->sge.addr = cpu_to_le64(virt_to_bus(sata->devno, id));
  222. pcmd->sge.cnt = cpu_to_le32(sizeof(id[0]) * ATA_ID_WORDS);
  223. pcmd->sge.flags = cpu_to_le32(SGE_TRM);
  224. ret = sil_exec_cmd(sata, pcmd, 0);
  225. if (ret) {
  226. sil_read_fis(sata, 0, &fis);
  227. printf("Err: id cmd(0x%x).\n", readl(sata->port + PORT_SERROR));
  228. sil_sata_dump_fis(&fis);
  229. return 1;
  230. }
  231. ata_swap_buf_le16(id, ATA_ID_WORDS);
  232. return 0;
  233. }
  234. static int sil_cmd_soft_reset(struct sil_sata *sata)
  235. {
  236. struct sil_cmd_block cmdb, *pcmd = &cmdb;
  237. struct sata_fis_d2h fis;
  238. void *port = sata->port;
  239. int ret;
  240. /* put the port into known state */
  241. if (sil_init_port(port)) {
  242. printf("SRST: port %d not ready\n", sata->id);
  243. return 1;
  244. }
  245. memset((void *)&cmdb, 0, sizeof(struct sil_cmd_block));
  246. pcmd->prb.ctrl = cpu_to_le16(PRB_CTRL_SRST);
  247. pcmd->prb.fis.fis_type = SATA_FIS_TYPE_REGISTER_H2D;
  248. pcmd->prb.fis.pm_port_c = 0xf;
  249. ret = sil_exec_cmd(sata, &cmdb, 0);
  250. if (ret) {
  251. sil_read_fis(sata, 0, &fis);
  252. printf("SRST cmd error.\n");
  253. sil_sata_dump_fis(&fis);
  254. return 1;
  255. }
  256. return 0;
  257. }
  258. static ulong sil_sata_rw_cmd(struct sil_sata *sata, ulong start, ulong blkcnt,
  259. u8 *buffer, int is_write)
  260. {
  261. struct sil_cmd_block cmdb, *pcmd = &cmdb;
  262. struct sata_fis_d2h fis;
  263. u64 block;
  264. int ret;
  265. block = (u64)start;
  266. memset(pcmd, 0, sizeof(struct sil_cmd_block));
  267. pcmd->prb.ctrl = cpu_to_le16(PRB_CTRL_PROTOCOL);
  268. pcmd->prb.fis.fis_type = SATA_FIS_TYPE_REGISTER_H2D;
  269. pcmd->prb.fis.pm_port_c = (1 << 7);
  270. if (is_write) {
  271. pcmd->prb.fis.command = ATA_CMD_WRITE;
  272. pcmd->prb.prot = cpu_to_le16(PRB_PROT_WRITE);
  273. } else {
  274. pcmd->prb.fis.command = ATA_CMD_READ;
  275. pcmd->prb.prot = cpu_to_le16(PRB_PROT_READ);
  276. }
  277. pcmd->prb.fis.device = ATA_LBA;
  278. pcmd->prb.fis.device |= (block >> 24) & 0xf;
  279. pcmd->prb.fis.lba_high = (block >> 16) & 0xff;
  280. pcmd->prb.fis.lba_mid = (block >> 8) & 0xff;
  281. pcmd->prb.fis.lba_low = block & 0xff;
  282. pcmd->prb.fis.sector_count = (u8)blkcnt & 0xff;
  283. pcmd->sge.addr = cpu_to_le64(virt_to_bus(sata->devno, buffer));
  284. pcmd->sge.cnt = cpu_to_le32(blkcnt * ATA_SECT_SIZE);
  285. pcmd->sge.flags = cpu_to_le32(SGE_TRM);
  286. ret = sil_exec_cmd(sata, pcmd, 0);
  287. if (ret) {
  288. sil_read_fis(sata, 0, &fis);
  289. printf("Err: rw cmd(0x%08x).\n",
  290. readl(sata->port + PORT_SERROR));
  291. sil_sata_dump_fis(&fis);
  292. return 1;
  293. }
  294. return blkcnt;
  295. }
  296. static ulong sil_sata_rw_cmd_ext(struct sil_sata *sata, ulong start,
  297. ulong blkcnt, u8 *buffer, int is_write)
  298. {
  299. struct sil_cmd_block cmdb, *pcmd = &cmdb;
  300. struct sata_fis_d2h fis;
  301. u64 block;
  302. int ret;
  303. block = (u64)start;
  304. memset(pcmd, 0, sizeof(struct sil_cmd_block));
  305. pcmd->prb.ctrl = cpu_to_le16(PRB_CTRL_PROTOCOL);
  306. pcmd->prb.fis.fis_type = SATA_FIS_TYPE_REGISTER_H2D;
  307. pcmd->prb.fis.pm_port_c = (1 << 7);
  308. if (is_write) {
  309. pcmd->prb.fis.command = ATA_CMD_WRITE_EXT;
  310. pcmd->prb.prot = cpu_to_le16(PRB_PROT_WRITE);
  311. } else {
  312. pcmd->prb.fis.command = ATA_CMD_READ_EXT;
  313. pcmd->prb.prot = cpu_to_le16(PRB_PROT_READ);
  314. }
  315. pcmd->prb.fis.lba_high_exp = (block >> 40) & 0xff;
  316. pcmd->prb.fis.lba_mid_exp = (block >> 32) & 0xff;
  317. pcmd->prb.fis.lba_low_exp = (block >> 24) & 0xff;
  318. pcmd->prb.fis.lba_high = (block >> 16) & 0xff;
  319. pcmd->prb.fis.lba_mid = (block >> 8) & 0xff;
  320. pcmd->prb.fis.lba_low = block & 0xff;
  321. pcmd->prb.fis.device = ATA_LBA;
  322. pcmd->prb.fis.sector_count_exp = (blkcnt >> 8) & 0xff;
  323. pcmd->prb.fis.sector_count = blkcnt & 0xff;
  324. pcmd->sge.addr = cpu_to_le64(virt_to_bus(sata->devno, buffer));
  325. pcmd->sge.cnt = cpu_to_le32(blkcnt * ATA_SECT_SIZE);
  326. pcmd->sge.flags = cpu_to_le32(SGE_TRM);
  327. ret = sil_exec_cmd(sata, pcmd, 0);
  328. if (ret) {
  329. sil_read_fis(sata, 0, &fis);
  330. printf("Err: rw ext cmd(0x%08x).\n",
  331. readl(sata->port + PORT_SERROR));
  332. sil_sata_dump_fis(&fis);
  333. return 1;
  334. }
  335. return blkcnt;
  336. }
  337. static ulong sil_sata_rw_lba28(struct sil_sata *sata, ulong blknr,
  338. lbaint_t blkcnt, const void *buffer,
  339. int is_write)
  340. {
  341. ulong start, blks, max_blks;
  342. u8 *addr;
  343. start = blknr;
  344. blks = blkcnt;
  345. addr = (u8 *)buffer;
  346. max_blks = ATA_MAX_SECTORS;
  347. do {
  348. if (blks > max_blks) {
  349. sil_sata_rw_cmd(sata, start, max_blks, addr, is_write);
  350. start += max_blks;
  351. blks -= max_blks;
  352. addr += ATA_SECT_SIZE * max_blks;
  353. } else {
  354. sil_sata_rw_cmd(sata, start, blks, addr, is_write);
  355. start += blks;
  356. blks = 0;
  357. addr += ATA_SECT_SIZE * blks;
  358. }
  359. } while (blks != 0);
  360. return blkcnt;
  361. }
  362. static ulong sil_sata_rw_lba48(struct sil_sata *sata, ulong blknr,
  363. lbaint_t blkcnt, const void *buffer,
  364. int is_write)
  365. {
  366. ulong start, blks, max_blks;
  367. u8 *addr;
  368. start = blknr;
  369. blks = blkcnt;
  370. addr = (u8 *)buffer;
  371. max_blks = ATA_MAX_SECTORS_LBA48;
  372. do {
  373. if (blks > max_blks) {
  374. sil_sata_rw_cmd_ext(sata, start, max_blks,
  375. addr, is_write);
  376. start += max_blks;
  377. blks -= max_blks;
  378. addr += ATA_SECT_SIZE * max_blks;
  379. } else {
  380. sil_sata_rw_cmd_ext(sata, start, blks,
  381. addr, is_write);
  382. start += blks;
  383. blks = 0;
  384. addr += ATA_SECT_SIZE * blks;
  385. }
  386. } while (blks != 0);
  387. return blkcnt;
  388. }
  389. static void sil_sata_cmd_flush_cache(struct sil_sata *sata)
  390. {
  391. struct sil_cmd_block cmdb, *pcmd = &cmdb;
  392. memset((void *)pcmd, 0, sizeof(struct sil_cmd_block));
  393. pcmd->prb.fis.fis_type = SATA_FIS_TYPE_REGISTER_H2D;
  394. pcmd->prb.fis.pm_port_c = (1 << 7);
  395. pcmd->prb.fis.command = ATA_CMD_FLUSH;
  396. sil_exec_cmd(sata, pcmd, 0);
  397. }
  398. static void sil_sata_cmd_flush_cache_ext(struct sil_sata *sata)
  399. {
  400. struct sil_cmd_block cmdb, *pcmd = &cmdb;
  401. memset((void *)pcmd, 0, sizeof(struct sil_cmd_block));
  402. pcmd->prb.fis.fis_type = SATA_FIS_TYPE_REGISTER_H2D;
  403. pcmd->prb.fis.pm_port_c = (1 << 7);
  404. pcmd->prb.fis.command = ATA_CMD_FLUSH_EXT;
  405. sil_exec_cmd(sata, pcmd, 0);
  406. }
  407. /*
  408. * SATA interface between low level driver and command layer
  409. */
  410. #if !CONFIG_IS_ENABLED(BLK)
  411. ulong sata_read(int dev, ulong blknr, lbaint_t blkcnt, void *buffer)
  412. {
  413. struct sil_sata *sata = (struct sil_sata *)sata_dev_desc[dev].priv;
  414. #else
  415. static ulong sata_read(struct udevice *dev, lbaint_t blknr, lbaint_t blkcnt,
  416. void *buffer)
  417. {
  418. struct sil_sata_priv *priv = dev_get_platdata(dev);
  419. int port_number = priv->port_num;
  420. struct sil_sata *sata = priv->sil_sata_desc[port_number];
  421. #endif
  422. ulong rc;
  423. if (sata->lba48)
  424. rc = sil_sata_rw_lba48(sata, blknr, blkcnt, buffer, READ_CMD);
  425. else
  426. rc = sil_sata_rw_lba28(sata, blknr, blkcnt, buffer, READ_CMD);
  427. return rc;
  428. }
  429. /*
  430. * SATA interface between low level driver and command layer
  431. */
  432. #if !CONFIG_IS_ENABLED(BLK)
  433. ulong sata_write(int dev, ulong blknr, lbaint_t blkcnt, const void *buffer)
  434. {
  435. struct sil_sata *sata = (struct sil_sata *)sata_dev_desc[dev].priv;
  436. #else
  437. ulong sata_write(struct udevice *dev, lbaint_t blknr, lbaint_t blkcnt,
  438. const void *buffer)
  439. {
  440. struct sil_sata_priv *priv = dev_get_platdata(dev);
  441. int port_number = priv->port_num;
  442. struct sil_sata *sata = priv->sil_sata_desc[port_number];
  443. #endif
  444. ulong rc;
  445. if (sata->lba48) {
  446. rc = sil_sata_rw_lba48(sata, blknr, blkcnt, buffer, WRITE_CMD);
  447. if (sata->wcache && sata->flush_ext)
  448. sil_sata_cmd_flush_cache_ext(sata);
  449. } else {
  450. rc = sil_sata_rw_lba28(sata, blknr, blkcnt, buffer, WRITE_CMD);
  451. if (sata->wcache && sata->flush)
  452. sil_sata_cmd_flush_cache(sata);
  453. }
  454. return rc;
  455. }
  456. #if !CONFIG_IS_ENABLED(BLK)
  457. static int sil_init_sata(int dev)
  458. {
  459. #else
  460. static int sil_init_sata(struct udevice *uc_dev, int dev)
  461. {
  462. struct sil_sata_priv *priv = dev_get_platdata(uc_dev);
  463. #endif
  464. struct sil_sata *sata;
  465. void *port;
  466. u32 tmp;
  467. int cnt;
  468. printf("SATA#%d:\n", dev);
  469. port = (void *)sata_info.iobase[1] +
  470. PORT_REGS_SIZE * (dev - sata_info.portbase);
  471. /* Initial PHY setting */
  472. writel(0x20c, port + PORT_PHY_CFG);
  473. /* clear port RST */
  474. tmp = readl(port + PORT_CTRL_STAT);
  475. if (tmp & PORT_CS_PORT_RST) {
  476. writel(PORT_CS_PORT_RST, port + PORT_CTRL_CLR);
  477. tmp = ata_wait_register(port + PORT_CTRL_STAT,
  478. PORT_CS_PORT_RST, PORT_CS_PORT_RST, 100);
  479. if (tmp & PORT_CS_PORT_RST)
  480. printf("Err: Failed to clear port RST\n");
  481. }
  482. /* Check if device is present */
  483. for (cnt = 0; cnt < 100; cnt++) {
  484. tmp = readl(port + PORT_SSTATUS);
  485. if ((tmp & 0xF) == 0x3)
  486. break;
  487. mdelay(1);
  488. }
  489. tmp = readl(port + PORT_SSTATUS);
  490. if ((tmp & 0xf) != 0x3) {
  491. printf(" (No RDY)\n");
  492. return 1;
  493. }
  494. /* Wait for port ready */
  495. tmp = ata_wait_register(port + PORT_CTRL_STAT,
  496. PORT_CS_RDY, PORT_CS_RDY, 100);
  497. if ((tmp & PORT_CS_RDY) != PORT_CS_RDY) {
  498. printf("%d port not ready.\n", dev);
  499. return 1;
  500. }
  501. /* configure port */
  502. sil_config_port(port);
  503. /* Reset port */
  504. writel(PORT_CS_DEV_RST, port + PORT_CTRL_STAT);
  505. readl(port + PORT_CTRL_STAT);
  506. tmp = ata_wait_register(port + PORT_CTRL_STAT, PORT_CS_DEV_RST,
  507. PORT_CS_DEV_RST, 100);
  508. if (tmp & PORT_CS_DEV_RST) {
  509. printf("%d port reset failed.\n", dev);
  510. return 1;
  511. }
  512. sata = (struct sil_sata *)malloc(sizeof(struct sil_sata));
  513. if (!sata) {
  514. printf("%d no memory.\n", dev);
  515. return 1;
  516. }
  517. memset((void *)sata, 0, sizeof(struct sil_sata));
  518. /* Save the private struct to block device struct */
  519. #if !CONFIG_IS_ENABLED(BLK)
  520. sata_dev_desc[dev].priv = (void *)sata;
  521. sata->devno = sata_info.devno;
  522. #else
  523. priv->sil_sata_desc[dev] = sata;
  524. priv->port_num = dev;
  525. #ifdef CONFIG_DM_PCI
  526. sata->devno = uc_dev->parent;
  527. #else
  528. sata->devno = sata_info.devno;
  529. #endif /* CONFIG_DM_PCI */
  530. #endif
  531. sata->id = dev;
  532. sata->port = port;
  533. sprintf(sata->name, "SATA#%d", dev);
  534. sil_cmd_soft_reset(sata);
  535. tmp = readl(port + PORT_SSTATUS);
  536. tmp = (tmp >> 4) & 0xf;
  537. printf(" (%s)\n", sata_spd_string(tmp));
  538. return 0;
  539. }
  540. #if !CONFIG_IS_ENABLED(BLK)
  541. /*
  542. * SATA interface between low level driver and command layer
  543. */
  544. int init_sata(int dev)
  545. {
  546. static int init_done, idx;
  547. pci_dev_t devno;
  548. u16 word;
  549. if (init_done == 1 && dev < sata_info.maxport)
  550. goto init_start;
  551. init_done = 1;
  552. /* Find PCI device(s) */
  553. devno = pci_find_devices(supported, idx++);
  554. if (devno == -1)
  555. return 1;
  556. pci_read_config_word(devno, PCI_DEVICE_ID, &word);
  557. /* get the port count */
  558. word &= 0xf;
  559. sata_info.portbase = 0;
  560. sata_info.maxport = sata_info.portbase + word;
  561. sata_info.devno = devno;
  562. /* Read out all BARs */
  563. sata_info.iobase[0] = (ulong)pci_map_bar(devno,
  564. PCI_BASE_ADDRESS_0, PCI_REGION_MEM);
  565. sata_info.iobase[1] = (ulong)pci_map_bar(devno,
  566. PCI_BASE_ADDRESS_2, PCI_REGION_MEM);
  567. /* mask out the unused bits */
  568. sata_info.iobase[0] &= 0xffffff80;
  569. sata_info.iobase[1] &= 0xfffffc00;
  570. /* Enable Bus Mastering and memory region */
  571. pci_write_config_word(devno, PCI_COMMAND,
  572. PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER);
  573. /* Check if mem accesses and Bus Mastering are enabled. */
  574. pci_read_config_word(devno, PCI_COMMAND, &word);
  575. if (!(word & PCI_COMMAND_MEMORY) ||
  576. (!(word & PCI_COMMAND_MASTER))) {
  577. printf("Error: Can not enable MEM access or Bus Mastering.\n");
  578. debug("PCI command: %04x\n", word);
  579. return 1;
  580. }
  581. /* GPIO off */
  582. writel(0, (void *)(sata_info.iobase[0] + HOST_FLASH_CMD));
  583. /* clear global reset & mask interrupts during initialization */
  584. writel(0, (void *)(sata_info.iobase[0] + HOST_CTRL));
  585. init_start:
  586. return sil_init_sata(dev);
  587. }
  588. int reset_sata(int dev)
  589. {
  590. return 0;
  591. }
  592. /*
  593. * SATA interface between low level driver and command layer
  594. */
  595. int scan_sata(int dev)
  596. {
  597. struct sil_sata *sata = (struct sil_sata *)sata_dev_desc[dev].priv;
  598. #else
  599. static int scan_sata(struct udevice *blk_dev, int dev)
  600. {
  601. struct blk_desc *desc = dev_get_uclass_platdata(blk_dev);
  602. struct sil_sata_priv *priv = dev_get_platdata(blk_dev);
  603. struct sil_sata *sata = priv->sil_sata_desc[dev];
  604. #endif
  605. unsigned char serial[ATA_ID_SERNO_LEN + 1];
  606. unsigned char firmware[ATA_ID_FW_REV_LEN + 1];
  607. unsigned char product[ATA_ID_PROD_LEN + 1];
  608. u16 *id;
  609. id = (u16 *)malloc(ATA_ID_WORDS * 2);
  610. if (!id) {
  611. printf("Id malloc failed\n");
  612. return 1;
  613. }
  614. sil_cmd_identify_device(sata, id);
  615. sil_sata_set_feature_by_id(sata, id);
  616. /* Serial number */
  617. ata_id_c_string(id, serial, ATA_ID_SERNO, sizeof(serial));
  618. /* Firmware version */
  619. ata_id_c_string(id, firmware, ATA_ID_FW_REV, sizeof(firmware));
  620. /* Product model */
  621. ata_id_c_string(id, product, ATA_ID_PROD, sizeof(product));
  622. #if !CONFIG_IS_ENABLED(BLK)
  623. memcpy(sata_dev_desc[dev].product, serial, sizeof(serial));
  624. memcpy(sata_dev_desc[dev].revision, firmware, sizeof(firmware));
  625. memcpy(sata_dev_desc[dev].vendor, product, sizeof(product));
  626. /* Totoal sectors */
  627. sata_dev_desc[dev].lba = ata_id_n_sectors(id);
  628. #ifdef CONFIG_LBA48
  629. sata_dev_desc[dev].lba48 = sata->lba48;
  630. #endif
  631. #else
  632. memcpy(desc->product, serial, sizeof(serial));
  633. memcpy(desc->revision, firmware, sizeof(firmware));
  634. memcpy(desc->vendor, product, sizeof(product));
  635. desc->lba = ata_id_n_sectors(id);
  636. #ifdef CONFIG_LBA48
  637. desc->lba48 = sata->lba48;
  638. #endif
  639. #endif
  640. #ifdef DEBUG
  641. ata_dump_id(id);
  642. #endif
  643. free((void *)id);
  644. return 0;
  645. }
  646. #if CONFIG_IS_ENABLED(BLK)
  647. static const struct blk_ops sata_sil_blk_ops = {
  648. .read = sata_read,
  649. .write = sata_write,
  650. };
  651. U_BOOT_DRIVER(sata_sil_driver) = {
  652. .name = "sata_sil_blk",
  653. .id = UCLASS_BLK,
  654. .ops = &sata_sil_blk_ops,
  655. .platdata_auto_alloc_size = sizeof(struct sil_sata_priv),
  656. };
  657. static int sil_unbind_device(struct udevice *dev)
  658. {
  659. int ret;
  660. ret = device_remove(dev, DM_REMOVE_NORMAL);
  661. if (ret)
  662. return ret;
  663. ret = device_unbind(dev);
  664. if (ret)
  665. return ret;
  666. return 0;
  667. }
  668. static int sil_pci_probe(struct udevice *dev)
  669. {
  670. struct udevice *blk;
  671. int failed_number;
  672. char sata_name[10];
  673. pci_dev_t devno;
  674. u16 word;
  675. int ret;
  676. int i;
  677. failed_number = 0;
  678. /* Get PCI device number */
  679. devno = dm_pci_get_bdf(dev);
  680. if (devno == -1)
  681. return 1;
  682. dm_pci_read_config16(dev, PCI_DEVICE_ID, &word);
  683. /* get the port count */
  684. word &= 0xf;
  685. sata_info.portbase = 0;
  686. sata_info.maxport = sata_info.portbase + word;
  687. sata_info.devno = devno;
  688. /* Read out all BARs */
  689. sata_info.iobase[0] = (ulong)dm_pci_map_bar(dev,
  690. PCI_BASE_ADDRESS_0, PCI_REGION_MEM);
  691. sata_info.iobase[1] = (ulong)dm_pci_map_bar(dev,
  692. PCI_BASE_ADDRESS_2, PCI_REGION_MEM);
  693. /* mask out the unused bits */
  694. sata_info.iobase[0] &= 0xffffff80;
  695. sata_info.iobase[1] &= 0xfffffc00;
  696. /* Enable Bus Mastering and memory region */
  697. dm_pci_write_config16(dev, PCI_COMMAND,
  698. PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER);
  699. /* Check if mem accesses and Bus Mastering are enabled. */
  700. dm_pci_read_config16(dev, PCI_COMMAND, &word);
  701. if (!(word & PCI_COMMAND_MEMORY) ||
  702. (!(word & PCI_COMMAND_MASTER))) {
  703. printf("Error: Can not enable MEM access or Bus Mastering.\n");
  704. debug("PCI command: %04x\n", word);
  705. return 1;
  706. }
  707. /* GPIO off */
  708. writel(0, (void *)(sata_info.iobase[0] + HOST_FLASH_CMD));
  709. /* clear global reset & mask interrupts during initialization */
  710. writel(0, (void *)(sata_info.iobase[0] + HOST_CTRL));
  711. for (i = sata_info.portbase; i < sata_info.maxport; i++) {
  712. snprintf(sata_name, sizeof(sata_name), "sil_sata%d", i);
  713. ret = blk_create_devicef(dev, "sata_sil_blk", sata_name,
  714. IF_TYPE_SATA, -1, 512, 0, &blk);
  715. if (ret) {
  716. debug("Can't create device\n");
  717. return ret;
  718. }
  719. ret = sil_init_sata(blk, i);
  720. if (ret) {
  721. ret = sil_unbind_device(blk);
  722. if (ret)
  723. return ret;
  724. failed_number++;
  725. continue;
  726. }
  727. ret = scan_sata(blk, i);
  728. if (ret) {
  729. ret = sil_unbind_device(blk);
  730. if (ret)
  731. return ret;
  732. failed_number++;
  733. continue;
  734. }
  735. }
  736. if (failed_number == sata_info.maxport)
  737. return -ENODEV;
  738. else
  739. return 0;
  740. }
  741. static int sil_pci_remove(struct udevice *dev)
  742. {
  743. int i;
  744. struct sil_sata *sata;
  745. struct sil_sata_priv *priv;
  746. priv = dev_get_priv(dev);
  747. for (i = sata_info.portbase; i < sata_info.maxport; i++) {
  748. sata = priv->sil_sata_desc[i];
  749. if (sata)
  750. free(sata);
  751. }
  752. return 0;
  753. }
  754. static int sata_sil_scan(struct udevice *dev)
  755. {
  756. /* Nothing to do here */
  757. return 0;
  758. }
  759. struct sil_ops sata_sil_ops = {
  760. .scan = sata_sil_scan,
  761. };
  762. static const struct udevice_id sil_pci_ids[] = {
  763. { .compatible = "sil-pci-sample" },
  764. { }
  765. };
  766. U_BOOT_DRIVER(sil_ahci_pci) = {
  767. .name = "sil_ahci_pci",
  768. .id = UCLASS_AHCI,
  769. .of_match = sil_pci_ids,
  770. .ops = &sata_sil_ops,
  771. .probe = sil_pci_probe,
  772. .remove = sil_pci_remove,
  773. .priv_auto_alloc_size = sizeof(struct sil_sata_priv),
  774. };
  775. U_BOOT_PCI_DEVICE(sil_ahci_pci, supported);
  776. #endif