sata_ceva.c 5.7 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * (C) Copyright 2015 - 2016 Xilinx, Inc.
  4. * Michal Simek <michal.simek@xilinx.com>
  5. */
  6. #include <common.h>
  7. #include <dm.h>
  8. #include <ahci.h>
  9. #include <log.h>
  10. #include <scsi.h>
  11. #include <asm/io.h>
  12. #include <linux/ioport.h>
  13. /* Vendor Specific Register Offsets */
  14. #define AHCI_VEND_PCFG 0xA4
  15. #define AHCI_VEND_PPCFG 0xA8
  16. #define AHCI_VEND_PP2C 0xAC
  17. #define AHCI_VEND_PP3C 0xB0
  18. #define AHCI_VEND_PP4C 0xB4
  19. #define AHCI_VEND_PP5C 0xB8
  20. #define AHCI_VEND_AXICC 0xBc
  21. #define AHCI_VEND_PAXIC 0xC0
  22. #define AHCI_VEND_PTC 0xC8
  23. /* Vendor Specific Register bit definitions */
  24. #define PAXIC_ADBW_BW64 0x1
  25. #define PAXIC_MAWIDD (1 << 8)
  26. #define PAXIC_MARIDD (1 << 16)
  27. #define PAXIC_OTL (0x4 << 20)
  28. #define PCFG_TPSS_VAL (0x32 << 16)
  29. #define PCFG_TPRS_VAL (0x2 << 12)
  30. #define PCFG_PAD_VAL 0x2
  31. #define PPCFG_TTA 0x1FFFE
  32. #define PPCFG_PSSO_EN (1 << 28)
  33. #define PPCFG_PSS_EN (1 << 29)
  34. #define PPCFG_ESDF_EN (1 << 31)
  35. #define PP2C_CIBGMN 0x0F
  36. #define PP2C_CIBGMX (0x25 << 8)
  37. #define PP2C_CIBGN (0x18 << 16)
  38. #define PP2C_CINMP (0x29 << 24)
  39. #define PP3C_CWBGMN 0x04
  40. #define PP3C_CWBGMX (0x0B << 8)
  41. #define PP3C_CWBGN (0x08 << 16)
  42. #define PP3C_CWNMP (0x0F << 24)
  43. #define PP4C_BMX 0x0a
  44. #define PP4C_BNM (0x08 << 8)
  45. #define PP4C_SFD (0x4a << 16)
  46. #define PP4C_PTST (0x06 << 24)
  47. #define PP5C_RIT 0x60216
  48. #define PP5C_RCT (0x7f0 << 20)
  49. #define PTC_RX_WM_VAL 0x40
  50. #define PTC_RSVD (1 << 27)
  51. #define PORT0_BASE 0x100
  52. #define PORT1_BASE 0x180
  53. /* Port Control Register Bit Definitions */
  54. #define PORT_SCTL_SPD_GEN3 (0x3 << 4)
  55. #define PORT_SCTL_SPD_GEN2 (0x2 << 4)
  56. #define PORT_SCTL_SPD_GEN1 (0x1 << 4)
  57. #define PORT_SCTL_IPM (0x3 << 8)
  58. #define PORT_BASE 0x100
  59. #define PORT_OFFSET 0x80
  60. #define NR_PORTS 2
  61. #define DRV_NAME "ahci-ceva"
  62. #define CEVA_FLAG_BROKEN_GEN2 1
  63. /* flag bit definition */
  64. #define FLAG_COHERENT 1
  65. /* register config value */
  66. #define CEVA_PHY1_CFG 0xa003fffe
  67. #define CEVA_PHY2_CFG 0x28184d1f
  68. #define CEVA_PHY3_CFG 0x0e081509
  69. #define CEVA_TRANS_CFG 0x08000029
  70. #define CEVA_AXICC_CFG 0x3fffffff
  71. /* for ls1021a */
  72. #define LS1021_AHCI_VEND_AXICC 0xC0
  73. #define LS1021_CEVA_PHY2_CFG 0x28183414
  74. #define LS1021_CEVA_PHY3_CFG 0x0e080e06
  75. #define LS1021_CEVA_PHY4_CFG 0x064a080b
  76. #define LS1021_CEVA_PHY5_CFG 0x2aa86470
  77. /* ecc val pair */
  78. #define ECC_DIS_VAL_CH1 0x00020000
  79. #define ECC_DIS_VAL_CH2 0x80000000
  80. #define ECC_DIS_VAL_CH3 0x40000000
  81. enum ceva_soc {
  82. CEVA_1V84,
  83. CEVA_LS1012A,
  84. CEVA_LS1021A,
  85. CEVA_LS1028A,
  86. CEVA_LS1043A,
  87. CEVA_LS1046A,
  88. CEVA_LS1088A,
  89. CEVA_LS2080A,
  90. };
  91. struct ceva_sata_priv {
  92. ulong base;
  93. ulong ecc_base;
  94. enum ceva_soc soc;
  95. ulong flag;
  96. };
  97. static int ceva_init_sata(struct ceva_sata_priv *priv)
  98. {
  99. ulong ecc_addr = priv->ecc_base;
  100. ulong base = priv->base;
  101. ulong tmp;
  102. switch (priv->soc) {
  103. case CEVA_1V84:
  104. tmp = PAXIC_ADBW_BW64 | PAXIC_MAWIDD | PAXIC_MARIDD | PAXIC_OTL;
  105. writel(tmp, base + AHCI_VEND_PAXIC);
  106. tmp = PCFG_TPSS_VAL | PCFG_TPRS_VAL | PCFG_PAD_VAL;
  107. writel(tmp, base + AHCI_VEND_PCFG);
  108. tmp = PPCFG_TTA | PPCFG_PSS_EN | PPCFG_ESDF_EN;
  109. writel(tmp, base + AHCI_VEND_PPCFG);
  110. tmp = PTC_RX_WM_VAL | PTC_RSVD;
  111. writel(tmp, base + AHCI_VEND_PTC);
  112. break;
  113. case CEVA_LS1021A:
  114. if (!ecc_addr)
  115. return -EINVAL;
  116. writel(ECC_DIS_VAL_CH1, ecc_addr);
  117. writel(CEVA_PHY1_CFG, base + AHCI_VEND_PPCFG);
  118. writel(LS1021_CEVA_PHY2_CFG, base + AHCI_VEND_PP2C);
  119. writel(LS1021_CEVA_PHY3_CFG, base + AHCI_VEND_PP3C);
  120. writel(LS1021_CEVA_PHY4_CFG, base + AHCI_VEND_PP4C);
  121. writel(LS1021_CEVA_PHY5_CFG, base + AHCI_VEND_PP5C);
  122. writel(CEVA_TRANS_CFG, base + AHCI_VEND_PTC);
  123. break;
  124. case CEVA_LS1012A:
  125. case CEVA_LS1043A:
  126. case CEVA_LS1046A:
  127. if (!ecc_addr)
  128. return -EINVAL;
  129. writel(ECC_DIS_VAL_CH2, ecc_addr);
  130. /* fallthrough */
  131. case CEVA_LS2080A:
  132. writel(CEVA_PHY1_CFG, base + AHCI_VEND_PPCFG);
  133. writel(CEVA_TRANS_CFG, base + AHCI_VEND_PTC);
  134. break;
  135. case CEVA_LS1028A:
  136. case CEVA_LS1088A:
  137. if (!ecc_addr)
  138. return -EINVAL;
  139. writel(ECC_DIS_VAL_CH3, ecc_addr);
  140. writel(CEVA_PHY1_CFG, base + AHCI_VEND_PPCFG);
  141. writel(CEVA_TRANS_CFG, base + AHCI_VEND_PTC);
  142. break;
  143. }
  144. if (priv->flag & FLAG_COHERENT)
  145. writel(CEVA_AXICC_CFG, base + AHCI_VEND_AXICC);
  146. return 0;
  147. }
  148. static int sata_ceva_bind(struct udevice *dev)
  149. {
  150. struct udevice *scsi_dev;
  151. return ahci_bind_scsi(dev, &scsi_dev);
  152. }
  153. static int sata_ceva_probe(struct udevice *dev)
  154. {
  155. struct ceva_sata_priv *priv = dev_get_priv(dev);
  156. ceva_init_sata(priv);
  157. return ahci_probe_scsi(dev, priv->base);
  158. }
  159. static const struct udevice_id sata_ceva_ids[] = {
  160. { .compatible = "ceva,ahci-1v84", .data = CEVA_1V84 },
  161. { .compatible = "fsl,ls1012a-ahci", .data = CEVA_LS1012A },
  162. { .compatible = "fsl,ls1021a-ahci", .data = CEVA_LS1021A },
  163. { .compatible = "fsl,ls1028a-ahci", .data = CEVA_LS1028A },
  164. { .compatible = "fsl,ls1043a-ahci", .data = CEVA_LS1043A },
  165. { .compatible = "fsl,ls1046a-ahci", .data = CEVA_LS1046A },
  166. { .compatible = "fsl,ls1088a-ahci", .data = CEVA_LS1088A },
  167. { .compatible = "fsl,ls2080a-ahci", .data = CEVA_LS2080A },
  168. { }
  169. };
  170. static int sata_ceva_ofdata_to_platdata(struct udevice *dev)
  171. {
  172. struct ceva_sata_priv *priv = dev_get_priv(dev);
  173. struct resource res_regs;
  174. int ret;
  175. if (dev_read_bool(dev, "dma-coherent"))
  176. priv->flag |= FLAG_COHERENT;
  177. priv->base = dev_read_addr(dev);
  178. if (priv->base == FDT_ADDR_T_NONE)
  179. return -EINVAL;
  180. ret = dev_read_resource_byname(dev, "ecc-addr", &res_regs);
  181. if (ret)
  182. priv->ecc_base = 0;
  183. else
  184. priv->ecc_base = res_regs.start;
  185. priv->soc = dev_get_driver_data(dev);
  186. debug("ccsr-sata-base %lx\t ecc-base %lx\n",
  187. priv->base,
  188. priv->ecc_base);
  189. return 0;
  190. }
  191. U_BOOT_DRIVER(ceva_host_blk) = {
  192. .name = "ceva_sata",
  193. .id = UCLASS_AHCI,
  194. .of_match = sata_ceva_ids,
  195. .bind = sata_ceva_bind,
  196. .ops = &scsi_ops,
  197. .priv_auto_alloc_size = sizeof(struct ceva_sata_priv),
  198. .probe = sata_ceva_probe,
  199. .ofdata_to_platdata = sata_ceva_ofdata_to_platdata,
  200. };