mvsata_ide.c 5.7 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright (C) 2010 Albert ARIBAUD <albert.u.boot@aribaud.net>
  4. *
  5. * Written-by: Albert ARIBAUD <albert.u.boot@aribaud.net>
  6. */
  7. #include <common.h>
  8. #include <asm/io.h>
  9. #include <linux/delay.h>
  10. #if defined(CONFIG_ARCH_ORION5X)
  11. #include <asm/arch/orion5x.h>
  12. #elif defined(CONFIG_ARCH_KIRKWOOD)
  13. #include <asm/arch/soc.h>
  14. #elif defined(CONFIG_ARCH_MVEBU)
  15. #include <linux/mbus.h>
  16. #endif
  17. /* SATA port registers */
  18. struct mvsata_port_registers {
  19. u32 reserved0[10];
  20. u32 edma_cmd;
  21. u32 reserved1[181];
  22. /* offset 0x300 : ATA Interface registers */
  23. u32 sstatus;
  24. u32 serror;
  25. u32 scontrol;
  26. u32 ltmode;
  27. u32 phymode3;
  28. u32 phymode4;
  29. u32 reserved2[5];
  30. u32 phymode1;
  31. u32 phymode2;
  32. u32 bist_cr;
  33. u32 bist_dw1;
  34. u32 bist_dw2;
  35. u32 serrorintrmask;
  36. };
  37. /*
  38. * Sanity checks:
  39. * - to compile at all, we need CONFIG_SYS_ATA_BASE_ADDR.
  40. * - for ide_preinit to make sense, we need at least one of
  41. * CONFIG_SYS_ATA_IDE0_OFFSET or CONFIG_SYS_ATA_IDE1_OFFSET;
  42. * - for ide_preinit to be called, we need CONFIG_IDE_PREINIT.
  43. * Fail with an explanation message if these conditions are not met.
  44. * This is particularly important for CONFIG_IDE_PREINIT, because
  45. * its lack would not cause a build error.
  46. */
  47. #if !defined(CONFIG_SYS_ATA_BASE_ADDR)
  48. #error CONFIG_SYS_ATA_BASE_ADDR must be defined
  49. #elif !defined(CONFIG_SYS_ATA_IDE0_OFFSET) \
  50. && !defined(CONFIG_SYS_ATA_IDE1_OFFSET)
  51. #error CONFIG_SYS_ATA_IDE0_OFFSET or CONFIG_SYS_ATA_IDE1_OFFSET \
  52. must be defined
  53. #elif !defined(CONFIG_IDE_PREINIT)
  54. #error CONFIG_IDE_PREINIT must be defined
  55. #endif
  56. /*
  57. * Masks and values for SControl DETection and Interface Power Management,
  58. * and for SStatus DETection.
  59. */
  60. #define MVSATA_EDMA_CMD_ATA_RST 0x00000004
  61. #define MVSATA_SCONTROL_DET_MASK 0x0000000F
  62. #define MVSATA_SCONTROL_DET_NONE 0x00000000
  63. #define MVSATA_SCONTROL_DET_INIT 0x00000001
  64. #define MVSATA_SCONTROL_IPM_MASK 0x00000F00
  65. #define MVSATA_SCONTROL_IPM_NO_LP_ALLOWED 0x00000300
  66. #define MVSATA_SCONTROL_MASK \
  67. (MVSATA_SCONTROL_DET_MASK|MVSATA_SCONTROL_IPM_MASK)
  68. #define MVSATA_PORT_INIT \
  69. (MVSATA_SCONTROL_DET_INIT|MVSATA_SCONTROL_IPM_NO_LP_ALLOWED)
  70. #define MVSATA_PORT_USE \
  71. (MVSATA_SCONTROL_DET_NONE|MVSATA_SCONTROL_IPM_NO_LP_ALLOWED)
  72. #define MVSATA_SSTATUS_DET_MASK 0x0000000F
  73. #define MVSATA_SSTATUS_DET_DEVCOMM 0x00000003
  74. /*
  75. * Status codes to return to client callers. Currently, callers ignore
  76. * exact value and only care for zero or nonzero, so no need to make this
  77. * public, it is only #define'd for clarity.
  78. * If/when standard negative codes are implemented in U-Boot, then these
  79. * #defines should be moved to, or replaced by ones from, the common list
  80. * of status codes.
  81. */
  82. #define MVSATA_STATUS_OK 0
  83. #define MVSATA_STATUS_TIMEOUT -1
  84. /*
  85. * Registers for SATA MBUS memory windows
  86. */
  87. #define MVSATA_WIN_CONTROL(w) (MVEBU_AXP_SATA_BASE + 0x30 + ((w) << 4))
  88. #define MVSATA_WIN_BASE(w) (MVEBU_AXP_SATA_BASE + 0x34 + ((w) << 4))
  89. /*
  90. * Initialize SATA memory windows for Armada XP
  91. */
  92. #ifdef CONFIG_ARCH_MVEBU
  93. static void mvsata_ide_conf_mbus_windows(void)
  94. {
  95. const struct mbus_dram_target_info *dram;
  96. int i;
  97. dram = mvebu_mbus_dram_info();
  98. /* Disable windows, Set Size/Base to 0 */
  99. for (i = 0; i < 4; i++) {
  100. writel(0, MVSATA_WIN_CONTROL(i));
  101. writel(0, MVSATA_WIN_BASE(i));
  102. }
  103. for (i = 0; i < dram->num_cs; i++) {
  104. const struct mbus_dram_window *cs = dram->cs + i;
  105. writel(((cs->size - 1) & 0xffff0000) | (cs->mbus_attr << 8) |
  106. (dram->mbus_dram_target_id << 4) | 1,
  107. MVSATA_WIN_CONTROL(i));
  108. writel(cs->base & 0xffff0000, MVSATA_WIN_BASE(i));
  109. }
  110. }
  111. #endif
  112. /*
  113. * Initialize one MVSATAHC port: set SControl's IPM to "always active"
  114. * and DET to "reset", then wait for SStatus's DET to become "device and
  115. * comm ok" (or time out after 50 us if no device), then set SControl's
  116. * DET back to "no action".
  117. */
  118. static int mvsata_ide_initialize_port(struct mvsata_port_registers *port)
  119. {
  120. u32 control;
  121. u32 status;
  122. u32 timeleft = 10000; /* wait at most 10 ms for SATA reset to complete */
  123. /* Hard reset */
  124. writel(MVSATA_EDMA_CMD_ATA_RST, &port->edma_cmd);
  125. udelay(25); /* taken from original marvell port */
  126. writel(0, &port->edma_cmd);
  127. /* Set control IPM to 3 (no low power) and DET to 1 (initialize) */
  128. control = readl(&port->scontrol);
  129. control = (control & ~MVSATA_SCONTROL_MASK) | MVSATA_PORT_INIT;
  130. writel(control, &port->scontrol);
  131. /* Toggle control DET back to 0 (normal operation) */
  132. control = (control & ~MVSATA_SCONTROL_MASK) | MVSATA_PORT_USE;
  133. writel(control, &port->scontrol);
  134. /* wait for status DET to become 3 (device and communication OK) */
  135. while (--timeleft) {
  136. status = readl(&port->sstatus) & MVSATA_SSTATUS_DET_MASK;
  137. if (status == MVSATA_SSTATUS_DET_DEVCOMM)
  138. break;
  139. udelay(1);
  140. }
  141. /* return success or time-out error depending on time left */
  142. if (!timeleft)
  143. return MVSATA_STATUS_TIMEOUT;
  144. return MVSATA_STATUS_OK;
  145. }
  146. /*
  147. * ide_preinit() will be called by ide_init in cmd_ide.c and will
  148. * reset the MVSTATHC ports needed by the board.
  149. */
  150. int ide_preinit(void)
  151. {
  152. int ret = MVSATA_STATUS_TIMEOUT;
  153. int status;
  154. #ifdef CONFIG_ARCH_MVEBU
  155. mvsata_ide_conf_mbus_windows();
  156. #endif
  157. /* Enable ATA port 0 (could be SATA port 0 or 1) if declared */
  158. #if defined(CONFIG_SYS_ATA_IDE0_OFFSET)
  159. status = mvsata_ide_initialize_port(
  160. (struct mvsata_port_registers *)
  161. (CONFIG_SYS_ATA_BASE_ADDR + CONFIG_SYS_ATA_IDE0_OFFSET));
  162. if (status == MVSATA_STATUS_OK)
  163. ret = MVSATA_STATUS_OK;
  164. #endif
  165. /* Enable ATA port 1 (could be SATA port 0 or 1) if declared */
  166. #if defined(CONFIG_SYS_ATA_IDE1_OFFSET)
  167. status = mvsata_ide_initialize_port(
  168. (struct mvsata_port_registers *)
  169. (CONFIG_SYS_ATA_BASE_ADDR + CONFIG_SYS_ATA_IDE1_OFFSET));
  170. if (status == MVSATA_STATUS_OK)
  171. ret = MVSATA_STATUS_OK;
  172. #endif
  173. /* Return success if at least one port initialization succeeded */
  174. return ret;
  175. }