dwc_ahsata_priv.h 10 KB

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  1. /* SPDX-License-Identifier: GPL-2.0+ */
  2. /*
  3. * Copyright (C) 2010 Freescale Semiconductor, Inc.
  4. * Terry Lv <r65388@freescale.com>
  5. */
  6. #ifndef __DWC_AHSATA_PRIV_H__
  7. #define __DWC_AHSATA_PRIV_H__
  8. #define DWC_AHSATA_MAX_CMD_SLOTS 32
  9. /* Max host controller numbers */
  10. #define SATA_HC_MAX_NUM 4
  11. /* Max command queue depth per host controller */
  12. #define DWC_AHSATA_HC_MAX_CMD 32
  13. /* Max port number per host controller */
  14. #define SATA_HC_MAX_PORT 16
  15. /* Generic Host Register */
  16. /* HBA Capabilities Register */
  17. #define SATA_HOST_CAP_S64A 0x80000000
  18. #define SATA_HOST_CAP_SNCQ 0x40000000
  19. #define SATA_HOST_CAP_SSNTF 0x20000000
  20. #define SATA_HOST_CAP_SMPS 0x10000000
  21. #define SATA_HOST_CAP_SSS 0x08000000
  22. #define SATA_HOST_CAP_SALP 0x04000000
  23. #define SATA_HOST_CAP_SAL 0x02000000
  24. #define SATA_HOST_CAP_SCLO 0x01000000
  25. #define SATA_HOST_CAP_ISS_MASK 0x00f00000
  26. #define SATA_HOST_CAP_ISS_OFFSET 20
  27. #define SATA_HOST_CAP_SNZO 0x00080000
  28. #define SATA_HOST_CAP_SAM 0x00040000
  29. #define SATA_HOST_CAP_SPM 0x00020000
  30. #define SATA_HOST_CAP_PMD 0x00008000
  31. #define SATA_HOST_CAP_SSC 0x00004000
  32. #define SATA_HOST_CAP_PSC 0x00002000
  33. #define SATA_HOST_CAP_NCS 0x00001f00
  34. #define SATA_HOST_CAP_CCCS 0x00000080
  35. #define SATA_HOST_CAP_EMS 0x00000040
  36. #define SATA_HOST_CAP_SXS 0x00000020
  37. #define SATA_HOST_CAP_NP_MASK 0x0000001f
  38. /* Global HBA Control Register */
  39. #define SATA_HOST_GHC_AE 0x80000000
  40. #define SATA_HOST_GHC_IE 0x00000002
  41. #define SATA_HOST_GHC_HR 0x00000001
  42. /* Interrupt Status Register */
  43. /* Ports Implemented Register */
  44. /* AHCI Version Register */
  45. #define SATA_HOST_VS_MJR_MASK 0xffff0000
  46. #define SATA_HOST_VS_MJR_OFFSET 16
  47. #define SATA_HOST_VS_MJR_MNR 0x0000ffff
  48. /* Command Completion Coalescing Control */
  49. #define SATA_HOST_CCC_CTL_TV_MASK 0xffff0000
  50. #define SATA_HOST_CCC_CTL_TV_OFFSET 16
  51. #define SATA_HOST_CCC_CTL_CC_MASK 0x0000ff00
  52. #define SATA_HOST_CCC_CTL_CC_OFFSET 8
  53. #define SATA_HOST_CCC_CTL_INT_MASK 0x000000f8
  54. #define SATA_HOST_CCC_CTL_INT_OFFSET 3
  55. #define SATA_HOST_CCC_CTL_EN 0x00000001
  56. /* Command Completion Coalescing Ports */
  57. /* HBA Capabilities Extended Register */
  58. #define SATA_HOST_CAP2_APST 0x00000004
  59. /* BIST Activate FIS Register */
  60. #define SATA_HOST_BISTAFR_NCP_MASK 0x0000ff00
  61. #define SATA_HOST_BISTAFR_NCP_OFFSET 8
  62. #define SATA_HOST_BISTAFR_PD_MASK 0x000000ff
  63. #define SATA_HOST_BISTAFR_PD_OFFSET 0
  64. /* BIST Control Register */
  65. #define SATA_HOST_BISTCR_FERLB 0x00100000
  66. #define SATA_HOST_BISTCR_TXO 0x00040000
  67. #define SATA_HOST_BISTCR_CNTCLR 0x00020000
  68. #define SATA_HOST_BISTCR_NEALB 0x00010000
  69. #define SATA_HOST_BISTCR_LLC_MASK 0x00000700
  70. #define SATA_HOST_BISTCR_LLC_OFFSET 8
  71. #define SATA_HOST_BISTCR_ERREN 0x00000040
  72. #define SATA_HOST_BISTCR_FLIP 0x00000020
  73. #define SATA_HOST_BISTCR_PV 0x00000010
  74. #define SATA_HOST_BISTCR_PATTERN_MASK 0x0000000f
  75. #define SATA_HOST_BISTCR_PATTERN_OFFSET 0
  76. /* BIST FIS Count Register */
  77. /* BIST Status Register */
  78. #define SATA_HOST_BISTSR_FRAMERR_MASK 0x0000ffff
  79. #define SATA_HOST_BISTSR_FRAMERR_OFFSET 0
  80. #define SATA_HOST_BISTSR_BRSTERR_MASK 0x00ff0000
  81. #define SATA_HOST_BISTSR_BRSTERR_OFFSET 16
  82. /* BIST DWORD Error Count Register */
  83. /* OOB Register*/
  84. #define SATA_HOST_OOBR_WE 0x80000000
  85. #define SATA_HOST_OOBR_cwMin_MASK 0x7f000000
  86. #define SATA_HOST_OOBR_cwMAX_MASK 0x00ff0000
  87. #define SATA_HOST_OOBR_ciMin_MASK 0x0000ff00
  88. #define SATA_HOST_OOBR_ciMax_MASK 0x000000ff
  89. /* Timer 1-ms Register */
  90. /* Global Parameter 1 Register */
  91. #define SATA_HOST_GPARAM1R_ALIGN_M 0x80000000
  92. #define SATA_HOST_GPARAM1R_RX_BUFFER 0x40000000
  93. #define SATA_HOST_GPARAM1R_PHY_DATA_MASK 0x30000000
  94. #define SATA_HOST_GPARAM1R_PHY_RST 0x08000000
  95. #define SATA_HOST_GPARAM1R_PHY_CTRL_MASK 0x07e00000
  96. #define SATA_HOST_GPARAM1R_PHY_STAT_MASK 0x001f8000
  97. #define SATA_HOST_GPARAM1R_LATCH_M 0x00004000
  98. #define SATA_HOST_GPARAM1R_BIST_M 0x00002000
  99. #define SATA_HOST_GPARAM1R_PHY_TYPE 0x00001000
  100. #define SATA_HOST_GPARAM1R_RETURN_ERR 0x00000400
  101. #define SATA_HOST_GPARAM1R_AHB_ENDIAN_MASK 0x00000300
  102. #define SATA_HOST_GPARAM1R_S_HADDR 0X00000080
  103. #define SATA_HOST_GPARAM1R_M_HADDR 0X00000040
  104. /* Global Parameter 2 Register */
  105. #define SATA_HOST_GPARAM2R_DEV_CP 0x00004000
  106. #define SATA_HOST_GPARAM2R_DEV_MP 0x00002000
  107. #define SATA_HOST_GPARAM2R_DEV_ENCODE_M 0x00001000
  108. #define SATA_HOST_GPARAM2R_RXOOB_CLK_M 0x00000800
  109. #define SATA_HOST_GPARAM2R_RXOOB_M 0x00000400
  110. #define SATA_HOST_GPARAM2R_TX_OOB_M 0x00000200
  111. #define SATA_HOST_GPARAM2R_RXOOB_CLK_MASK 0x000001ff
  112. /* Port Parameter Register */
  113. #define SATA_HOST_PPARAMR_TX_MEM_M 0x00000200
  114. #define SATA_HOST_PPARAMR_TX_MEM_S 0x00000100
  115. #define SATA_HOST_PPARAMR_RX_MEM_M 0x00000080
  116. #define SATA_HOST_PPARAMR_RX_MEM_S 0x00000040
  117. #define SATA_HOST_PPARAMR_TXFIFO_DEPTH_MASK 0x00000038
  118. #define SATA_HOST_PPARAMR_RXFIFO_DEPTH_MASK 0x00000007
  119. /* Test Register */
  120. #define SATA_HOST_TESTR_PSEL_MASK 0x00070000
  121. #define SATA_HOST_TESTR_TEST_IF 0x00000001
  122. /* Port Register Descriptions */
  123. /* Port# Command List Base Address Register */
  124. #define SATA_PORT_CLB_CLB_MASK 0xfffffc00
  125. /* Port# Command List Base Address Upper 32-Bits Register */
  126. /* Port# FIS Base Address Register */
  127. #define SATA_PORT_FB_FB_MASK 0xfffffff0
  128. /* Port# FIS Base Address Upper 32-Bits Register */
  129. /* Port# Interrupt Status Register */
  130. #define SATA_PORT_IS_CPDS 0x80000000
  131. #define SATA_PORT_IS_TFES 0x40000000
  132. #define SATA_PORT_IS_HBFS 0x20000000
  133. #define SATA_PORT_IS_HBDS 0x10000000
  134. #define SATA_PORT_IS_IFS 0x08000000
  135. #define SATA_PORT_IS_INFS 0x04000000
  136. #define SATA_PORT_IS_OFS 0x01000000
  137. #define SATA_PORT_IS_IPMS 0x00800000
  138. #define SATA_PORT_IS_PRCS 0x00400000
  139. #define SATA_PORT_IS_DMPS 0x00000080
  140. #define SATA_PORT_IS_PCS 0x00000040
  141. #define SATA_PORT_IS_DPS 0x00000020
  142. #define SATA_PORT_IS_UFS 0x00000010
  143. #define SATA_PORT_IS_SDBS 0x00000008
  144. #define SATA_PORT_IS_DSS 0x00000004
  145. #define SATA_PORT_IS_PSS 0x00000002
  146. #define SATA_PORT_IS_DHRS 0x00000001
  147. /* Port# Interrupt Enable Register */
  148. #define SATA_PORT_IE_CPDE 0x80000000
  149. #define SATA_PORT_IE_TFEE 0x40000000
  150. #define SATA_PORT_IE_HBFE 0x20000000
  151. #define SATA_PORT_IE_HBDE 0x10000000
  152. #define SATA_PORT_IE_IFE 0x08000000
  153. #define SATA_PORT_IE_INFE 0x04000000
  154. #define SATA_PORT_IE_OFE 0x01000000
  155. #define SATA_PORT_IE_IPME 0x00800000
  156. #define SATA_PORT_IE_PRCE 0x00400000
  157. #define SATA_PORT_IE_DMPE 0x00000080
  158. #define SATA_PORT_IE_PCE 0x00000040
  159. #define SATA_PORT_IE_DPE 0x00000020
  160. #define SATA_PORT_IE_UFE 0x00000010
  161. #define SATA_PORT_IE_SDBE 0x00000008
  162. #define SATA_PORT_IE_DSE 0x00000004
  163. #define SATA_PORT_IE_PSE 0x00000002
  164. #define SATA_PORT_IE_DHRE 0x00000001
  165. /* Port# Command Register */
  166. #define SATA_PORT_CMD_ICC_MASK 0xf0000000
  167. #define SATA_PORT_CMD_ASP 0x08000000
  168. #define SATA_PORT_CMD_ALPE 0x04000000
  169. #define SATA_PORT_CMD_DLAE 0x02000000
  170. #define SATA_PORT_CMD_ATAPI 0x01000000
  171. #define SATA_PORT_CMD_APSTE 0x00800000
  172. #define SATA_PORT_CMD_ESP 0x00200000
  173. #define SATA_PORT_CMD_CPD 0x00100000
  174. #define SATA_PORT_CMD_MPSP 0x00080000
  175. #define SATA_PORT_CMD_HPCP 0x00040000
  176. #define SATA_PORT_CMD_PMA 0x00020000
  177. #define SATA_PORT_CMD_CPS 0x00010000
  178. #define SATA_PORT_CMD_CR 0x00008000
  179. #define SATA_PORT_CMD_FR 0x00004000
  180. #define SATA_PORT_CMD_MPSS 0x00002000
  181. #define SATA_PORT_CMD_CCS_MASK 0x00001f00
  182. #define SATA_PORT_CMD_FRE 0x00000010
  183. #define SATA_PORT_CMD_CLO 0x00000008
  184. #define SATA_PORT_CMD_POD 0x00000004
  185. #define SATA_PORT_CMD_SUD 0x00000002
  186. #define SATA_PORT_CMD_ST 0x00000001
  187. /* Port# Task File Data Register */
  188. #define SATA_PORT_TFD_ERR_MASK 0x0000ff00
  189. #define SATA_PORT_TFD_STS_MASK 0x000000ff
  190. #define SATA_PORT_TFD_STS_ERR 0x00000001
  191. #define SATA_PORT_TFD_STS_DRQ 0x00000008
  192. #define SATA_PORT_TFD_STS_BSY 0x00000080
  193. /* Port# Signature Register */
  194. /* Port# Serial ATA Status {SStatus} Register */
  195. #define SATA_PORT_SSTS_IPM_MASK 0x00000f00
  196. #define SATA_PORT_SSTS_SPD_MASK 0x000000f0
  197. #define SATA_PORT_SSTS_DET_MASK 0x0000000f
  198. /* Port# Serial ATA Control {SControl} Register */
  199. #define SATA_PORT_SCTL_IPM_MASK 0x00000f00
  200. #define SATA_PORT_SCTL_SPD_MASK 0x000000f0
  201. #define SATA_PORT_SCTL_DET_MASK 0x0000000f
  202. /* Port# Serial ATA Error {SError} Register */
  203. #define SATA_PORT_SERR_DIAG_X 0x04000000
  204. #define SATA_PORT_SERR_DIAG_F 0x02000000
  205. #define SATA_PORT_SERR_DIAG_T 0x01000000
  206. #define SATA_PORT_SERR_DIAG_S 0x00800000
  207. #define SATA_PORT_SERR_DIAG_H 0x00400000
  208. #define SATA_PORT_SERR_DIAG_C 0x00200000
  209. #define SATA_PORT_SERR_DIAG_D 0x00100000
  210. #define SATA_PORT_SERR_DIAG_B 0x00080000
  211. #define SATA_PORT_SERR_DIAG_W 0x00040000
  212. #define SATA_PORT_SERR_DIAG_I 0x00020000
  213. #define SATA_PORT_SERR_DIAG_N 0x00010000
  214. #define SATA_PORT_SERR_ERR_E 0x00000800
  215. #define SATA_PORT_SERR_ERR_P 0x00000400
  216. #define SATA_PORT_SERR_ERR_C 0x00000200
  217. #define SATA_PORT_SERR_ERR_T 0x00000100
  218. #define SATA_PORT_SERR_ERR_M 0x00000002
  219. #define SATA_PORT_SERR_ERR_I 0x00000001
  220. /* Port# Serial ATA Active {SActive} Register */
  221. /* Port# Command Issue Register */
  222. /* Port# Serial ATA Notification Register */
  223. /* Port# DMA Control Register */
  224. #define SATA_PORT_DMACR_RXABL_MASK 0x0000f000
  225. #define SATA_PORT_DMACR_TXABL_MASK 0x00000f00
  226. #define SATA_PORT_DMACR_RXTS_MASK 0x000000f0
  227. #define SATA_PORT_DMACR_TXTS_MASK 0x0000000f
  228. /* Port# PHY Control Register */
  229. /* Port# PHY Status Register */
  230. #define SATA_HC_CMD_HDR_ENTRY_SIZE sizeof(struct cmd_hdr_entry)
  231. /* DW0
  232. */
  233. #define CMD_HDR_DI_CFL_MASK 0x0000001f
  234. #define CMD_HDR_DI_CFL_OFFSET 0
  235. #define CMD_HDR_DI_A 0x00000020
  236. #define CMD_HDR_DI_W 0x00000040
  237. #define CMD_HDR_DI_P 0x00000080
  238. #define CMD_HDR_DI_R 0x00000100
  239. #define CMD_HDR_DI_B 0x00000200
  240. #define CMD_HDR_DI_C 0x00000400
  241. #define CMD_HDR_DI_PMP_MASK 0x0000f000
  242. #define CMD_HDR_DI_PMP_OFFSET 12
  243. #define CMD_HDR_DI_PRDTL 0xffff0000
  244. #define CMD_HDR_DI_PRDTL_OFFSET 16
  245. /* prde_fis_len
  246. */
  247. #define CMD_HDR_PRD_ENTRY_SHIFT 16
  248. #define CMD_HDR_PRD_ENTRY_MASK 0x003f0000
  249. #define CMD_HDR_FIS_LEN_SHIFT 2
  250. /* attribute
  251. */
  252. #define CMD_HDR_ATTR_RES 0x00000800 /* Reserved bit, should be 1 */
  253. #define CMD_HDR_ATTR_VBIST 0x00000400 /* Vendor BIST */
  254. /* Snoop enable for all descriptor */
  255. #define CMD_HDR_ATTR_SNOOP 0x00000200
  256. #define CMD_HDR_ATTR_FPDMA 0x00000100 /* FPDMA queued command */
  257. #define CMD_HDR_ATTR_RESET 0x00000080 /* Reset - a SRST or device reset */
  258. /* BIST - require the host to enter BIST mode */
  259. #define CMD_HDR_ATTR_BIST 0x00000040
  260. #define CMD_HDR_ATTR_ATAPI 0x00000020 /* ATAPI command */
  261. #define CMD_HDR_ATTR_TAG 0x0000001f /* TAG mask */
  262. #define FLAGS_DMA 0x00000000
  263. #define FLAGS_FPDMA 0x00000001
  264. #define SATA_FLAG_Q_DEP_MASK 0x0000000f
  265. #define SATA_FLAG_WCACHE 0x00000100
  266. #define SATA_FLAG_FLUSH 0x00000200
  267. #define SATA_FLAG_FLUSH_EXT 0x00000400
  268. #define READ_CMD 0
  269. #define WRITE_CMD 1
  270. #endif /* __DWC_AHSATA_H__ */