ahci_sunxi.c 2.8 KB

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  1. #include <common.h>
  2. #include <ahci.h>
  3. #include <dm.h>
  4. #include <log.h>
  5. #include <scsi.h>
  6. #include <errno.h>
  7. #include <asm/io.h>
  8. #include <asm/gpio.h>
  9. #include <linux/delay.h>
  10. #define AHCI_PHYCS0R 0x00c0
  11. #define AHCI_PHYCS1R 0x00c4
  12. #define AHCI_PHYCS2R 0x00c8
  13. #define AHCI_RWCR 0x00fc
  14. /* This magic PHY initialisation was taken from the Allwinner releases
  15. * and Linux driver, but is completely undocumented.
  16. */
  17. static int sunxi_ahci_phy_init(u8 *reg_base)
  18. {
  19. u32 reg_val;
  20. int timeout;
  21. writel(0, reg_base + AHCI_RWCR);
  22. mdelay(5);
  23. setbits_le32(reg_base + AHCI_PHYCS1R, 0x1 << 19);
  24. clrsetbits_le32(reg_base + AHCI_PHYCS0R,
  25. (0x7 << 24),
  26. (0x5 << 24) | (0x1 << 23) | (0x1 << 18));
  27. clrsetbits_le32(reg_base + AHCI_PHYCS1R,
  28. (0x3 << 16) | (0x1f << 8) | (0x3 << 6),
  29. (0x2 << 16) | (0x6 << 8) | (0x2 << 6));
  30. setbits_le32(reg_base + AHCI_PHYCS1R, (0x1 << 28) | (0x1 << 15));
  31. clrbits_le32(reg_base + AHCI_PHYCS1R, (0x1 << 19));
  32. clrsetbits_le32(reg_base + AHCI_PHYCS0R, (0x7 << 20), (0x3 << 20));
  33. clrsetbits_le32(reg_base + AHCI_PHYCS2R, (0x1f << 5), (0x19 << 5));
  34. mdelay(5);
  35. setbits_le32(reg_base + AHCI_PHYCS0R, (0x1 << 19));
  36. timeout = 250; /* Power up takes approx 50 us */
  37. for (;;) {
  38. reg_val = readl(reg_base + AHCI_PHYCS0R) & (0x7 << 28);
  39. if (reg_val == (0x2 << 28))
  40. break;
  41. if (--timeout == 0) {
  42. printf("AHCI PHY power up failed.\n");
  43. return -EIO;
  44. }
  45. udelay(1);
  46. };
  47. setbits_le32(reg_base + AHCI_PHYCS2R, (0x1 << 24));
  48. timeout = 100; /* Calibration takes approx 10 us */
  49. for (;;) {
  50. reg_val = readl(reg_base + AHCI_PHYCS2R) & (0x1 << 24);
  51. if (reg_val == 0x0)
  52. break;
  53. if (--timeout == 0) {
  54. printf("AHCI PHY calibration failed.\n");
  55. return -EIO;
  56. }
  57. udelay(1);
  58. }
  59. mdelay(15);
  60. writel(0x7, reg_base + AHCI_RWCR);
  61. return 0;
  62. }
  63. static int sunxi_sata_probe(struct udevice *dev)
  64. {
  65. ulong base;
  66. u8 *reg;
  67. int ret;
  68. base = dev_read_addr(dev);
  69. if (base == FDT_ADDR_T_NONE) {
  70. debug("%s: Failed to find address (err=%d\n)", __func__, ret);
  71. return -EINVAL;
  72. }
  73. reg = (u8 *)base;
  74. ret = sunxi_ahci_phy_init(reg);
  75. if (ret) {
  76. debug("%s: Failed to init phy (err=%d\n)", __func__, ret);
  77. return ret;
  78. }
  79. ret = ahci_probe_scsi(dev, base);
  80. if (ret) {
  81. debug("%s: Failed to probe (err=%d\n)", __func__, ret);
  82. return ret;
  83. }
  84. return 0;
  85. }
  86. static int sunxi_sata_bind(struct udevice *dev)
  87. {
  88. struct udevice *scsi_dev;
  89. int ret;
  90. ret = ahci_bind_scsi(dev, &scsi_dev);
  91. if (ret) {
  92. debug("%s: Failed to bind (err=%d\n)", __func__, ret);
  93. return ret;
  94. }
  95. return 0;
  96. }
  97. static const struct udevice_id sunxi_ahci_ids[] = {
  98. { .compatible = "allwinner,sun4i-a10-ahci" },
  99. { .compatible = "allwinner,sun8i-r40-ahci" },
  100. { }
  101. };
  102. U_BOOT_DRIVER(ahci_sunxi_drv) = {
  103. .name = "ahci_sunxi",
  104. .id = UCLASS_AHCI,
  105. .of_match = sunxi_ahci_ids,
  106. .bind = sunxi_sata_bind,
  107. .probe = sunxi_sata_probe,
  108. };