spi-cadence.txt 1.3 KB

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  1. Cadence QSPI controller device tree bindings
  2. --------------------------------------------
  3. Required properties:
  4. - compatible : should be "cdns,qspi-nor"
  5. - reg : 1.Physical base address and size of SPI registers map.
  6. 2. Physical base address & size of NOR Flash.
  7. - clocks : Clock phandles (see clock bindings for details).
  8. - cdns,fifo-depth : Size of the data FIFO in words.
  9. - cdns,fifo-width : Bus width of the data FIFO in bytes.
  10. - cdns,trigger-address : 32-bit indirect AHB trigger address.
  11. - cdns,is-decoded-cs : Flag to indicate whether decoder is used or not.
  12. - status : enable in requried dts.
  13. connected flash properties
  14. --------------------------
  15. - spi-max-frequency : Max supported spi frequency.
  16. - page-size : Flash page size.
  17. - block-size : Flash memory block size.
  18. - cdns,tshsl-ns : Added delay in master reference clocks (ref_clk) for
  19. the length that the master mode chip select outputs
  20. are de-asserted between transactions.
  21. - cdns,tsd2d-ns : Delay in master reference clocks (ref_clk) between one
  22. chip select being de-activated and the activation of
  23. another.
  24. - cdns,tchsh-ns : Delay in master reference clocks between last bit of
  25. current transaction and de-asserting the device chip
  26. select (n_ss_out).
  27. - cdns,tslch-ns : Delay in master reference clocks between setting
  28. n_ss_out low and first bit transfer