snps,dw-apb-ssi.txt 2.0 KB

1234567891011121314151617181920212223242526272829303132333435363738394041424344454647484950515253545556
  1. Synopsys DesignWare AMBA 2.0 Synchronous Serial Interface
  2. and Synopsys DesignWare High Performance Synchronous Serial Interface
  3. Required properties:
  4. - compatible : One of
  5. "altr,socfpga-spi",
  6. "altr,socfpga-arria10-spi",
  7. "canaan,kendryte-k210-spi",
  8. "canaan,kendryte-k210-ssi",
  9. "intel,stratix10-spi",
  10. "intel,agilex-spi",
  11. "mscc,ocelot-spi",
  12. or "mscc,jaguar2-spi";
  13. and one of
  14. "snps,dw-apb-ssi-3.20a",
  15. "snps,dw-apb-ssi-3.22a",
  16. "snps,dw-apb-ssi-3.23",
  17. "snps,dw-apb-ssi-4.00a",
  18. "snps,dw-apb-ssi-4.01",
  19. or "snps,dwc-ssi-1.01a".
  20. "snps,dw-apb-ssi" may also be used, but is deprecated in favor of specific
  21. version strings.
  22. - reg : The register base for the controller. For "mscc,<soc>-spi", a second
  23. register set is required (named ICPU_CFG:SPI_MST)
  24. - #address-cells : <1>, as required by generic SPI binding.
  25. - #size-cells : <0>, also as required by generic SPI binding.
  26. - clocks : phandles for the clocks, see the description of clock-names below.
  27. The phandle for the "ssi_clk" is required. The phandle for the "pclk" clock
  28. is optional. If a single clock is specified but no clock-name, it is the
  29. "ssi_clk" clock. If both clocks are listed, the "ssi_clk" must be first.
  30. Optional properties:
  31. - clock-names : Contains the names of the clocks:
  32. "ssi_clk", for the core clock used to generate the external SPI clock.
  33. "pclk", the interface clock, required for register access.
  34. - cs-gpios : Specifies the gpio pins to be used for chipselects.
  35. - num-cs : The number of chipselects. If omitted, this will default to 4.
  36. - reg-io-width : The I/O register width (in bytes) implemented by this
  37. device. Supported values are 2 or 4 (the default).
  38. Child nodes as per the generic SPI binding.
  39. Example:
  40. spi@fff00000 {
  41. compatible = "altr,socfpga-arria10-spi",
  42. "snps,dw-apb-ssi-4.00a", "snps,dw-apb-ssi";
  43. reg = <0xfff00000 0x1000>;
  44. interrupts = <0 154 4>;
  45. #address-cells = <1>;
  46. #size-cells = <0>;
  47. clocks = <&spi_m_clk>;
  48. num-cs = <2>;
  49. cs-gpios = <&gpio0 13 0>,
  50. <&gpio0 14 0>;
  51. };