ti,k3-r5f-rproc.txt 6.3 KB

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  1. TI K3 R5F processor subsystems
  2. ==============================
  3. The TI K3 family of SoCs usually have one or more dual-core Arm Cortex
  4. R5F processor subsystems/clusters (R5FSS). The dual core cluster can be
  5. used either in a LockStep mode providing safety/fault tolerance features
  6. or in a Split mode providing two individual compute cores for doubling
  7. the compute capacity. These are used together with other processors
  8. present on the SoC to achieve various system level goals.
  9. R5F Sub-System Device Node:
  10. ===========================
  11. Each Dual-Core R5F sub-system is represented as a single DTS node representing
  12. the cluster, with a pair of child DT nodes representing the individual R5F
  13. cores. Each node has a number of required or optional properties that enable
  14. the OS running on the host processor to perform the device management of the
  15. remote processor and to communicate with the remote processor.
  16. Required properties:
  17. --------------------
  18. The following are the mandatory properties:
  19. - compatible: Should be one of the following,
  20. "ti,am654-r5fss" for R5F clusters/subsystems on
  21. K3 AM65x SoCs
  22. "ti,j721e-r5fss" for R5F clusters/subsystems on
  23. K3 J721E SoCs
  24. "ti,j7200-r5fss" for R5F clusters/subsystems on
  25. K3 J7200 SoCs
  26. - power-domains: Should contain a phandle to a PM domain provider node
  27. and an args specifier containing the R5FSS device id
  28. value. This property is as per the binding,
  29. Documentation/devicetree/bindings/soc/ti/sci-pm-domain.txt
  30. - #address-cells: Should be 1
  31. - #size-cells: Should be 1
  32. - ranges: Standard ranges definition providing translations for
  33. R5F TCM address spaces
  34. Optional properties:
  35. --------------------
  36. - lockstep-mode: Configuration Mode for the Dual R5F cores within the R5F
  37. cluster. Should be either a value of 1 (LockStep mode) or
  38. 0 (Split mode), default is LockStep mode if omitted.
  39. R5F Processor Child Nodes:
  40. ==========================
  41. The R5F Sub-System device node should define two R5F child nodes, each node
  42. representing a TI instantiation of the Arm Cortex R5F core. There are some
  43. specific integration differences for the IP like the usage of a Region Address
  44. Translator (RAT) for translating the larger SoC bus addresses into a 32-bit
  45. address space for the processor.
  46. Required properties:
  47. --------------------
  48. The following are the mandatory properties:
  49. - compatible: Should be one of the following,
  50. "ti,am654-r5f" for the R5F cores in K3 AM65x SoCs
  51. "ti,j721e-r5f" for the R5F cores in K3 J721E SOCs
  52. "ti,j7200-r5f" for the R5F cores in K3 J7200 SOCs
  53. - reg: Should contain an entry for each value in 'reg-names'.
  54. Each entry should have the memory region's start address
  55. and the size of the region, the representation matching
  56. the parent node's '#address-cells' and '#size-cells' values.
  57. - reg-names: Should contain strings with the following names, each
  58. representing a specific internal memory region, and
  59. should be defined in this order,
  60. "atcm", "btcm"
  61. - ti,sci: Should be a phandle to the TI-SCI System Controller node
  62. - ti,sci-dev-id: Should contain the TI-SCI device id corresponding to the
  63. R5F Core. Please refer to the corresponding System
  64. Controller documentation for valid values for the R5F
  65. cores.
  66. - ti,sci-proc-ids: Should contain 2 integer values. The first cell should
  67. contain the TI-SCI processor id for the R5F core device
  68. and the second cell should contain the TI-SCI host id to
  69. which the processor control ownership should be
  70. transferred to.
  71. - resets: Should contain the phandle to the reset controller node
  72. managing the resets for this device, and a reset
  73. specifier. Please refer to the following reset bindings
  74. for the reset argument specifier,
  75. Documentation/devicetree/bindings/reset/ti,sci-reset.txt
  76. for AM65x, J721E and J7200 SoCs
  77. Optional properties:
  78. --------------------
  79. The following properties are optional properties for each of the R5F cores:
  80. - atcm-enable: R5F core configuration mode dictating if ATCM should be
  81. enabled. Should be either a value of 1 (enabled) or
  82. 0 (disabled), default is disabled if omitted. R5F view
  83. of ATCM dictated by loczrama property.
  84. - btcm-enable: R5F core configuration mode dictating if BTCM should be
  85. enabled. Should be either a value of 1 (enabled) or
  86. 0 (disabled), default is enabled if omitted. R5F view
  87. of BTCM dictated by loczrama property.
  88. - loczrama: R5F core configuration mode dictating which TCM should
  89. appear at address 0 (from core's view). Should be either
  90. a value of 1 (ATCM at 0x0) or 0 (BTCM at 0x0), default
  91. value is 1 if omitted.
  92. Example:
  93. --------
  94. 1. AM654 SoC
  95. /* AM65x remoteproc alias */
  96. aliases {
  97. remoteproc0 = &mcu_r5fss0_core0;
  98. };
  99. cbass_main: interconnect@100000 {
  100. compatible = "simple-bus";
  101. #address-cells = <2>;
  102. #size-cells = <2>;
  103. ranges = <0x00 0x41000000 0x00 0x41000000 0x00 0x00020000>,
  104. <0x00 0x41400000 0x00 0x41400000 0x00 0x00020000>,
  105. <0x00 0x41c00000 0x00 0x41c00000 0x00 0x00080000>;
  106. cbass_mcu: interconnect@28380000 {
  107. compatible = "simple-bus";
  108. #address-cells = <2>;
  109. #size-cells = <2>;
  110. ranges = <0x00 0x41000000 0x00 0x41000000 0x00 0x00020000>, /* MCU R5F Core0 */
  111. <0x00 0x41400000 0x00 0x41400000 0x00 0x00020000>, /* MCU R5F Core1 */
  112. <0x00 0x41c00000 0x00 0x41c00000 0x00 0x00080000>; /* MCU SRAM */
  113. /* AM65x MCU R5FSS node */
  114. mcu_r5fss0: r5fss@41000000 {
  115. compatible = "ti,am654-r5fss";
  116. power-domains = <&k3_pds 129>;
  117. lockstep-mode = <1>;
  118. #address-cells = <1>;
  119. #size-cells = <1>;
  120. ranges = <0x41000000 0x00 0x41000000 0x20000>,
  121. <0x41400000 0x00 0x41400000 0x20000>;
  122. mcu_r5f0: r5f@41000000 {
  123. compatible = "ti,am654-r5f";
  124. reg = <0x41000000 0x00008000>,
  125. <0x41010000 0x00008000>;
  126. reg-names = "atcm", "btcm";
  127. ti,sci = <&dmsc>;
  128. ti,sci-dev-id = <159>;
  129. ti,sci-proc-ids = <0x01 0xFF>;
  130. resets = <&k3_reset 159 1>;
  131. atcm-enable = <1>;
  132. btcm-enable = <1>;
  133. loczrama = <1>;
  134. };
  135. mcu_r5f1: r5f@41400000 {
  136. compatible = "ti,am654-r5f";
  137. reg = <0x41400000 0x00008000>,
  138. <0x41410000 0x00008000>;
  139. reg-names = "atcm", "btcm";
  140. ti,sci = <&dmsc>;
  141. ti,sci-dev-id = <245>;
  142. ti,sci-proc-ids = <0x02 0xFF>;
  143. resets = <&k3_reset 245 1>;
  144. atcm-enable = <1>;
  145. btcm-enable = <1>;
  146. loczrama = <1>;
  147. };
  148. };
  149. };
  150. };