ti,k3-dsp-rproc.txt 3.5 KB

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  1. TI K3 DSP devices
  2. =================
  3. The TI K3 family of SoCs usually have one or more TI DSP Core sub-systems that
  4. are used to offload some of the processor-intensive tasks or algorithms, for
  5. achieving various system level goals.
  6. These processor sub-systems usually contain additional sub-modules like L1
  7. and/or L2 caches/SRAMs, an Interrupt Controller, an external memory controller,
  8. a dedicated local power/sleep controller etc. The DSP processor cores in the
  9. K3 SoCs is usually either a TMS320C66x CorePac processor or a TMS320C71x CorePac
  10. processor.
  11. DSP Device Node:
  12. ================
  13. Each DSP Core sub-system is represented as a single DT node. Each node has a
  14. number of required or optional properties that enable the OS running on the
  15. host processor (Arm CorePac) to perform the device management of the remote
  16. processor and to communicate with the remote processor.
  17. Required properties:
  18. --------------------
  19. The following are the mandatory properties:
  20. - compatible: Should be one of the following,
  21. "ti,j721e-c66-dsp" for C66x DSPs on K3 J721E SoCs
  22. "ti,j721e-c71-dsp" for C71x DSPs on K3 J721E SoCs
  23. - reg: Should contain an entry for each value in 'reg-names'.
  24. Each entry should have the memory region's start address
  25. and the size of the region, the representation matching
  26. the parent node's '#address-cells' and '#size-cells' values.
  27. - reg-names: Should contain strings with the following names, each
  28. representing a specific internal memory region (if
  29. present), and should be defined in this order,
  30. "l2sram", "l1pram", "l1dram"
  31. NOTE: C71x DSPs do not have a "l1pram" memory.
  32. - ti,sci: Should be a phandle to the TI-SCI System Controller node
  33. - ti,sci-dev-id: Should contain the TI-SCI device id corresponding to the
  34. DSP Core. Please refer to the corresponding System
  35. Controller documentation for valid values for the DSP
  36. cores.
  37. - ti,sci-proc-ids: Should contain 2 integer values. The first cell should
  38. contain the TI-SCI processor id for the DSP core device
  39. and the second cell should contain the TI-SCI host id to
  40. which the processor control ownership should be
  41. transferred to.
  42. - resets: Should contain the phandle to the reset controller node
  43. managing the resets for this device, and a reset
  44. specifier. Please refer to the following reset bindings
  45. for the reset argument specifier,
  46. Documentation/devicetree/bindings/reset/ti,sci-reset.txt
  47. Example:
  48. ---------
  49. 1. J721E SoC
  50. /* J721E remoteproc alias */
  51. aliases {
  52. rproc6 = &c66_0;
  53. rproc8 = &c71_0;
  54. };
  55. cbass_main: interconnect@100000 {
  56. compatible = "simple-bus";
  57. #address-cells = <2>;
  58. #size-cells = <2>;
  59. ranges = <0x00 0x64800000 0x00 0x64800000 0x00 0x00800000>, /* C71_0 */
  60. <0x4d 0x80800000 0x4d 0x80800000 0x00 0x00800000>, /* C66_0 */
  61. <0x4d 0x81800000 0x4d 0x81800000 0x00 0x00800000>; /* C66_1 */
  62. /* J721E C66_0 DSP node */
  63. c66_0: dsp@4d80800000 {
  64. compatible = "ti,j721e-c66-dsp";
  65. reg = <0x4d 0x80800000 0x00 0x00048000>,
  66. <0x4d 0x80e00000 0x00 0x00008000>,
  67. <0x4d 0x80f00000 0x00 0x00008000>;
  68. reg-names = "l2sram", "l1pram", "l1dram";
  69. ti,sci = <&dmsc>;
  70. ti,sci-dev-id = <142>;
  71. ti,sci-proc-ids = <0x03 0xFF>;
  72. resets = <&k3_reset 142 1>;
  73. };
  74. /* J721E C71_0 DSP node */
  75. c71_0: dsp@64800000 {
  76. compatible = "ti,j721e-c71-dsp";
  77. reg = <0x00 0x64800000 0x00 0x00080000>,
  78. <0x00 0x64e00000 0x00 0x0000c000>;
  79. reg-names = "l2sram", "l1dram";
  80. ti,sci = <&dmsc>;
  81. ti,sci-dev-id = <15>;
  82. ti,sci-proc-ids = <0x30 0xFF>;
  83. resets = <&k3_reset 15 1>;
  84. };
  85. };