marvell,mvebu-pinctrl.txt 3.6 KB

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  1. The pinctrl driver enables Marvell Armada 8K SoCs to configure the multi-purpose
  2. pins (mpp) to a specific function.
  3. A Marvell SoC pin configuration node is a node of a group of pins which can
  4. be used for a specific device or function. Each node requires one or more
  5. mpp pins or group of pins and a mpp function common to all pins.
  6. Required properties for the pinctrl driver:
  7. - compatible: "marvell,mvebu-pinctrl",
  8. "marvell,ap806-pinctrl",
  9. "marvell,armada-7k-pinctrl",
  10. "marvell,armada-8k-cpm-pinctrl",
  11. "marvell,armada-8k-cps-pinctrl"
  12. - bank-name: A string defining the pinc controller bank name
  13. - reg: A pair of values defining the pin controller base address
  14. and the address space
  15. - pin-count: Numeric value defining the amount of multi purpose pins
  16. included in this bank
  17. - max-func: Numeric value defining the maximum function value for
  18. pins in this bank
  19. - pin-func: Array of pin function values for every pin in the bank.
  20. When the function value for a specific pin equal 0xFF,
  21. the pin configuration is skipped and a default function
  22. value is used for this pin.
  23. The A8K is a hybrid SoC that contains several silicon dies interconnected in
  24. a single package. Each such die may have a separate pin controller.
  25. Example:
  26. / {
  27. ap806 {
  28. config-space {
  29. pinctl: pinctl@6F4000 {
  30. compatible = "marvell,mvebu-pinctrl",
  31. "marvell,ap806-pinctrl";
  32. bank-name ="apn-806";
  33. reg = <0x6F4000 0x10>;
  34. pin-count = <20>;
  35. max-func = <3>;
  36. /* MPP Bus:
  37. * SPI0 [0-3]
  38. * I2C0 [4-5]
  39. * UART0 [11,19]
  40. */
  41. /* 0 1 2 3 4 5 6 7 8 9 */
  42. pin-func = < 3 3 3 3 3 3 0 0 0 0
  43. 0 3 0 0 0 0 0 0 0 3>;
  44. };
  45. };
  46. };
  47. cp110-master {
  48. config-space {
  49. cpm_pinctl: pinctl@44000 {
  50. compatible = "marvell,mvebu-pinctrl",
  51. "marvell,armada-7k-pinctrl",
  52. "marvell,armada-8k-cpm-pinctrl";
  53. bank-name ="cp0-110";
  54. reg = <0x440000 0x20>;
  55. pin-count = <63>;
  56. max-func = <0xf>;
  57. /* MPP Bus:
  58. * [0-31] = 0xff: Keep default CP0_shared_pins:
  59. * [11] CLKOUT_MPP_11 (out)
  60. * [23] LINK_RD_IN_CP2CP (in)
  61. * [25] CLKOUT_MPP_25 (out)
  62. * [29] AVS_FB_IN_CP2CP (in)
  63. * [32,34] SMI
  64. * [31] GPIO: push button/Wake
  65. * [35-36] GPIO
  66. * [37-38] I2C
  67. * [40-41] SATA[0/1]_PRESENT_ACTIVEn
  68. * [42-43] XSMI
  69. * [44-55] RGMII1
  70. * [56-62] SD
  71. */
  72. /* 0 1 2 3 4 5 6 7 8 9 */
  73. pin-func = < 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff
  74. 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff
  75. 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff
  76. 0xff 0 7 0 7 0 0 2 2 0
  77. 0 0 8 8 1 1 1 1 1 1
  78. 1 1 1 1 1 1 0xE 0xE 0xE 0xE
  79. 0xE 0xE 0xE>;
  80. };
  81. };
  82. };
  83. cp110-slave {
  84. config-space {
  85. cps_pinctl: pinctl@44000 {
  86. compatible = "marvell,mvebu-pinctrl",
  87. "marvell,armada-8k-cps-pinctrl";
  88. bank-name ="cp1-110";
  89. reg = <0x440000 0x20>;
  90. pin-count = <63>;
  91. max-func = <0xf>;
  92. /* MPP Bus:
  93. * [0-11] RGMII0
  94. * [27,31] GE_MDIO/MDC
  95. * [32-62] = 0xff: Keep default CP1_shared_pins:
  96. */
  97. /* 0 1 2 3 4 5 6 7 8 9 */
  98. pin-func = < 0x3 0x3 0x3 0x3 0x3 0x3 0x3 0x3 0x3 0x3
  99. 0x3 0x3 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff
  100. 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0x8 0xff 0xff
  101. 0xff 0x8 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff
  102. 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff
  103. 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff
  104. 0xff 0xff 0xff>;
  105. };
  106. };
  107. };
  108. }