marvell,armada-cp110-pinctrl.txt 8.3 KB

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  1. Functions of Armada CP110 pin controller
  2. Function 0x0 for any MPP ID activates GPIO pin mode
  3. Function 0xc for any MPP ID activates DEBUG_BUS pin mode
  4. -------------------------------------------------------------------------------
  5. MPP# 0x1 0x2 0x3 0x4
  6. -------------------------------------------------------------------------------
  7. 0 DEV_ALE[1] AU_I2SMCLK GE0_RXD[3] TDM_PCLK
  8. 1 DEV_ALE[0] AU_I2SDO_SPDIFO GE0_RXD[2] TDM_DRX
  9. 2 DEV_AD[15] AU_I2SEXTCLK GE0_RXD[1] TDM_DTX
  10. 3 DEV_AD[14] AU_I2SLRCLK GE0_RXD[0] TDM_FSYNC
  11. 4 DEV_AD[13] AU_I2SBCLK GE0_RXCTL TDM_RSTn
  12. 5 DEV_AD[12] AU_I2SDI GE0_RXCLK TDM_INTn
  13. 6 DEV_AD[11] - GE0_TXD[3] SPI0_CSn[2]
  14. 7 DEV_AD[10] - GE0_TXD[2] SPI0_CSn[1]
  15. 8 DEV_AD[9] - GE0_TXD[1] SPI0_CSn[0]
  16. 9 DEV_AD[8] - GE0_TXD[0] SPI0_MOSI
  17. 10 DEV_READYn - GE0_TXCTL SPI0_MISO
  18. 11 DEV_WEn[1] - GE0_TXCLKOUT SPI0_CLK
  19. 12 DEV_CLK_OUT NF_RBn[1] SPI1_CSn[1] GE0_RXCLK
  20. 13 DEV_BURSTn NF_RBn[0] SPI1_MISO GE0_RXCTL
  21. 14 DEV_BOOTCSn DEV_CSn[0] SPI1_CSn[0] SPI0_CSn[3]
  22. 15 DEV_AD[7] - SPI1_MOSI -
  23. 16 DEV_AD[6] - SPI1_CLK -
  24. 17 DEV_AD[5] - - GE0_TXD[3]
  25. 18 DEV_AD[4] - - GE0_TXD[2]
  26. 19 DEV_AD[3] - - GE0_TXD[1]
  27. 20 DEV_AD[2] - - GE0_TXD[0]
  28. 21 DEV_AD[1] - - GE0_TXCTL
  29. 22 DEV_AD[0] - - GE0_TXCLKOUT
  30. 23 DEV_A[1] - - -
  31. 24 DEV_A[0] - - -
  32. 25 DEV_OEn - - - -
  33. 26 DEV_WEn[0] - - -
  34. 27 DEV_CSn[0] SPI1_MISO MSS_GPIO[4] GE0_RXD[3]
  35. 28 DEV_CSn[1] SPI1_CSn[0] MSS_GPIO[5] GE0_RXD[2]
  36. 29 DEV_CSn[2] SPI1_MOSI MSS_GPIO[6] GE0_RXD[1]
  37. 30 DEV_CSn[3] SPI1_CLK MSS_GPIO[7] GE0_RXD[0]
  38. 31 DEV_A[2] - MSS_GPIO[4] -
  39. 32 MII_COL MII_TXERR MSS_SPI_MISO TDM_DRX
  40. 33 MII_TXCLK SDIO_PWR1[0] MSS_SPI_CSn TDM_FSYNC
  41. 34 MII_RXERR SDIO_PWR1[1] MSS_SPI_MOSI TDM_DTX
  42. 35 SATA1_PRESENT_ACTIVEn TWSI1_SDA MSS_SPI_CLK TDM_PCLK
  43. 36 SYNCE2_CLK TWSI1_SCK PTP_CLK SYNCE1_CLK
  44. 37 UART2_RXD TWSI0_SCK PTP_PCLK_OUT TDM_INTn
  45. 38 UART2_TXD TWSI0_SDA PTP_PULSE TDM_RSTn
  46. 39 SDIO_WR_PROTECT - - AU_I2SBCLK PTP_CLK
  47. 40 SDIO_PWR1[1] SYNCE1_CLK MSS_TWSI_SDA AU_I2SDO_SPDIFO
  48. 41 SDIO_PWR1[0] SDIO_BUS_PWR MSS_TWSI_SCK AU_I2SLRCLK
  49. 42 SDIO_V18_EN SDIO_WR_PROTECT SYNCE2_CLK AU_I2SMCLK
  50. 43 SDIO_CARD_DETECT - SYNCE1_CLK AU_I2SEXTCLK
  51. 44 GE1_TXD[2] - - -
  52. 45 GE1_TXD[3] - - -
  53. 46 GE1_TXD[1] - - -
  54. 47 GE1_TXD[0] - - -
  55. 48 GE1_TXCTL_MII_TXEN - - -
  56. 49 GE1_TXCLKOUT MII_CRS - -
  57. 50 GE1_RXCLK MSS_TWSI_SDA - -
  58. 51 GE1_RXD[0] MSS_TWSI_SCK - -
  59. 52 GE1_RXD[1] SYNCE1_CLK - SYNCE2_CLK
  60. 53 GE1_RXD[2] - PTP_CLK -
  61. 54 GE1_RXD[3] SYNCE2_CLK PTP_PCLK_OUT SYNCE1_CLK
  62. 55 GE1_RXCTL_MII_RXDV - PTP_PULSE -
  63. 56 - - - TDM_DRX
  64. 57 - MSS_TWSI_SDA PTP_PCLK_OUT TDM_INTn
  65. 58 - MSS_TWSI_SCK PTP_CLK TDM_RSTn
  66. 59 MSS_GPIO[7] SYNCE2_CLK - TDM_FSYNC
  67. 60 MSS_GPIO[6] - PTP_PULSE TDM_DTX
  68. 61 MSS_GPIO[5] - PTP_CLK TDM_PCLK
  69. 62 MSS_GPIO[4] SYNCE1_CLK PTP_PCLK_OUT -
  70. -------------------------------------------------------------------------------
  71. MPP# 0x5 0x6 0x7
  72. -------------------------------------------------------------------------------
  73. 0 - PTP_PULSE MSS_TWSI_SDA
  74. 1 - PTP_CLK MSS_TWSI_SCK
  75. 2 MSS_UART_RXD PTP_PCLK_OUT TWSI1_SCK
  76. 3 MSS_UART_TXD PCIe_RSTOUTn TWSI1_SDA
  77. 4 MSS_UART_RXD UART1_CTS PCIe0_CLKREQ
  78. 5 MSS_UART_TXD UART1_RTS PCIe1_CLKREQ
  79. 6 AU_I2SEXTCLK SATA1_PRESENT_ACTIVEn PCIe2_CLKREQ
  80. 7 SPI1_CSn[1] SATA0_PRESENT_ACTIVEn LED_DATA
  81. 8 SPI1_CSn[0] UART0_CTS LED_STB
  82. 9 SPI1_MOSI - PCIe_RSTOUTn
  83. 10 SPI1_MISO UART0_CTS SATA1_PRESENT_ACTIVEn
  84. 11 SPI1_CLK UART0_RTS LED_CLK
  85. 12 - - -
  86. 13 - - -
  87. 14 AU_I2SEXTCLK SPI0_MISO SATA0_PRESENT_ACTIVEn
  88. 15 - SPI0_MOSI -
  89. 16 - - -
  90. 17 - - -
  91. 18 - - -
  92. 19 - - -
  93. 20 - - -
  94. 21 - - -
  95. 22 - - -
  96. 23 AU_I2SMCLK - -
  97. 24 AU_I2SLRCLK - -
  98. 25 AU_I2SDO_SPDIFO - -
  99. 26 AU_I2SBCLK - -
  100. 27 SPI0_CSn[4] - -
  101. 28 SPI0_CSn[5] PCIe2_CLKREQ PTP_PULSE
  102. 29 SPI0_CSn[6] PCIe1_CLKREQ PTP_CLK
  103. 30 SPI0_CSn[7] PCIe0_CLKREQ PTP_PCLK_OUT
  104. 31 - PCIe_RSTOUTn -
  105. 32 AU_I2SEXTCLK AU_I2SDI GE_MDIO
  106. 33 AU_I2SMCLK SDIO_BUS_PWR -
  107. 34 AU_I2SLRCLK SDIO_WR_PROTECT GE_MDC
  108. 35 AU_I2SDO_SPDIFO SDIO_CARD_DETECT XG_MDIO
  109. 36 AU_I2SBCLK SATA0_PRESENT_ACTIVEn XG_MDC
  110. 37 MSS_TWSI_SCK SATA1_PRESENT_ACTIVEn GE_MDC
  111. 38 MSS_TWSI_SDA SATA0_PRESENT_ACTIVEn GE_MDIO
  112. 39 SPI0_CSn[1] - -
  113. 40 PTP_PCLK_OUT SPI0_CLK UART1_TXD
  114. 41 PTP_PULSE SPI0_MOSI UART1_RXD
  115. 42 MSS_UART_TXD SPI0_MISO UART1_CTS
  116. 43 MSS_UART_RXD SPI0_CSn[0] UART1_RTS
  117. 44 - - UART0_RTS
  118. 45 - - UART0_TXD
  119. 46 - - UART1_RTS
  120. 47 SPI1_CLK - UART1_TXD
  121. 48 SPI1_MOSI - -
  122. 49 SPI1_MISO - UART1_RXD
  123. 50 SPI1_CSn[0] UART2_TXD UART0_RXD
  124. 51 SPI1_CSn[1] UART2_RXD UART0_CTS
  125. 52 SPI1_CSn[2] - UART1_CTS
  126. 53 SPI1_CSn[3] - UART1_RXD
  127. 54 - - -
  128. 55 - - -
  129. 56 AU_I2SDO_SPDIFO SPI0_CLK UART1_RXD
  130. 57 AU_I2SBCLK SPI0_MOSI UART1_TXD
  131. 58 AU_I2SDI SPI0_MISO UART1_CTS
  132. 59 AU_I2SLRCLK SPI0_CSn[0] UART0_CTS
  133. 60 AU_I2SMCLK SPI0_CSn[1] UART0_RTS
  134. 61 AU_I2SEXTCLK SPI0_CSn[2] UART0_TXD
  135. 62 SATA1_PRESENT_ACTIVEn SPI0_CSn[3] UART0_RXD
  136. -------------------------------------------------------------------------------
  137. MPP# 0x8 0x9 0xA
  138. -------------------------------------------------------------------------------
  139. 0 UART0_RXD SATA0_PRESENT_ACTIVEn GE_MDIO
  140. 1 UART0_TXD SATA1_PRESENT_ACTIVEn GE_MDC
  141. 2 UART1_RXD SATA0_PRESENT_ACTIVEn XG_MDC
  142. 3 UART1_TXD SATA1_PRESENT_ACTIVEn XG_MDIO
  143. 4 UART3_RXD - GE_MDC
  144. 5 UART3_TXD - GE_MDIO
  145. 6 UART0_RXD PTP_PULSE -
  146. 7 UART0_TXD PTP_CLK -
  147. 8 UART2_RXD PTP_PCLK_OUT SYNCE1_CLK
  148. 9 - - SYNCE2_CLK
  149. 10 - - -
  150. 11 UART2_TXD SATA0_PRESENT_ACTIVEn -
  151. 12 - - -
  152. 13 MSS_SPI_MISO - -
  153. 14 MSS_SPI_CSn - -
  154. 15 MSS_SPI_MOSI - -
  155. 16 MSS_SPI_CLK - -
  156. 17 - - -
  157. 18 - - -
  158. 19 - - -
  159. 20 - - -
  160. 21 - - -
  161. 22 - - -
  162. 23 - - -
  163. 24 - - -
  164. 25 - - -
  165. 26 - - -
  166. 27 GE_MDIO SATA0_PRESENT_ACTIVEn UART0_RTS
  167. 28 GE_MDC SATA1_PRESENT_ACTIVEn UART0_CTS
  168. 29 MSS_TWSI_SDA SATA0_PRESENT_ACTIVEn UART0_RXD
  169. 30 MSS_TWSI_SCK SATA1_PRESENT_ACTIVEn UART0_TXD
  170. 31 GE_MDC - -
  171. 32 SDIO_V18_EN PCIe1_CLKREQ MSS_GPIO[0]
  172. 33 XG_MDIO PCIe2_CLKREQ MSS_GPIO[1]
  173. 34 - PCIe0_CLKREQ MSS_GPIO[2]
  174. 35 GE_MDIO PCIe_RSTOUTn MSS_GPIO[3]
  175. 36 GE_MDC PCIe2_CLKREQ MSS_GPIO[5]
  176. 37 XG_MDC PCIe1_CLKREQ MSS_GPIO[6]
  177. 38 XG_MDIO AU_I2SEXTCLK MSS_GPIO[7]
  178. 39 SATA1_PRESENT_ACTIVEn MSS_GPIO[0]
  179. 40 GE_MDIO SATA0_PRESENT_ACTIVEn MSS_GPIO[1]
  180. 41 GE_MDC SATA1_PRESENT_ACTIVEn MSS_GPIO[2]
  181. 42 XG_MDC SATA0_PRESENT_ACTIVEn MSS_GPIO[4]
  182. 43 XG_MDIO SATA1_PRESENT_ACTIVEn MSS_GPIO[5]
  183. 44 - - -
  184. 45 - PCIe_RSTOUTn -
  185. 46 - - -
  186. 47 GE_MDC CLKOUT -
  187. 48 XG_MDC - -
  188. 49 GE_MDIO PCIe0_CLKREQ SDIO_V18_EN
  189. 50 XG_MDIO - SDIO_PWR1[1]
  190. 51 - - SDIO_PWR1[0]
  191. 52 LED_CLK PCIe_RSTOUTn PCIe0_CLKREQ
  192. 53 LED_STB - -
  193. 54 LED_DATA - SDIO_HW_RST
  194. 55 - - SDIO_LED
  195. 56 - SATA1_PRESENT_ACTIVEn -
  196. 57 - SATA0_PRESENT_ACTIVEn -
  197. 58 LED_CLK - -
  198. 59 LED_STB UART1_TXD -
  199. 60 LED_DATA UART1_RXD -
  200. 61 UART2_TXD SATA1_PRESENT_ACTIVEn GE_MDIO
  201. 62 UART2_RXD SATA0_PRESENT_ACTIVEn GE_MDC
  202. -------------------------------------------------------------------------------
  203. MPP# 0xB 0xD 0xE
  204. -------------------------------------------------------------------------------
  205. 0 - - -
  206. 1 - - -
  207. 2 - - -
  208. 3 - - -
  209. 4 - - -
  210. 5 - - -
  211. 6 - - -
  212. 7 - - -
  213. 8 - - -
  214. 9 - - -
  215. 10 - - -
  216. 11 - CLKOUT_MPP_11 -
  217. 12 - - -
  218. 13 - - -
  219. 14 - - -
  220. 15 PTP_PULSE_CP2CP SAR_IN[5] -
  221. 16 - SAR_IN[3] -
  222. 17 - SAR_IN[6] -
  223. 18 PTP_CLK_CP2CP SAR_IN[11] -
  224. 19 WAKEUP_OUT_CP2CP SAR_IN[7] -
  225. 20 - SAR_IN[9] -
  226. 21 SEI_IN_CP2CP SAR_IN[8] -
  227. 22 WAKEUP_IN_CP2CP SAR_IN[10] -
  228. 23 LINK_RD_IN_CP2CP SAR_IN[4] -
  229. 24 - - -
  230. 25 - CLKOUT_MPP_25 -
  231. 26 - SAR_IN[0] -
  232. 27 REI_IN_CP2CP SAR_IN[1] -
  233. 28 LED_DATA SAR_IN[2] -
  234. 29 LED_STB AVS_FB_IN_CP2CP -
  235. 30 LED_CLK SAR_IN[13] -
  236. 31 - - -
  237. 32 - SAR_CP2CP_OUT[0] -
  238. 33 - SAR_CP2CP_OUT[1] -
  239. 34 - SAR_CP2CP_OUT[2] -
  240. 35 - SAR_CP2CP_OUT[3] -
  241. 36 - CLKIN -
  242. 37 LINK_RD_OUT_CP2CP SAR_CP2CP_OUT[4] -
  243. 38 PTP_PULSE_CP2CP SAR_CP2CP_OUT[5] -
  244. 39 - AVS_FB_OUT_CP2CP -
  245. 40 - - -
  246. 41 REI_OUT_CP2CP - -
  247. 42 - SAR_CP2CP_OUT[9] -
  248. 43 WAKEUP_OUT_CP2CP SAR_CP2CP_OUT[10] -
  249. 44 PTP_CLK_CP2CP SAR_CP2CP_OUT[11] -
  250. 45 - SAR_CP2CP_OUT[6] -
  251. 46 - SAR_CP2CP_OUT[13] -
  252. 47 - - -
  253. 48 WAKEUP_IN_CP2CP SAR_CP2CP_OUT[7] -
  254. 49 SEI_OUT_CP2CP SAR_CP2CP_OUT[8] -
  255. 50 - - -
  256. 51 - - -
  257. 52 - - -
  258. 53 SDIO_LED - -
  259. 54 SDIO_WR_PROTECT - -
  260. 55 SDIO_CARD_DETECT - -
  261. 56 - - SDIO0_CLK
  262. 57 - - SDIO0_CMD
  263. 58 - - SDIO0_D[0]
  264. 59 - - SDIO0_D[1]
  265. 60 - - SDIO0_D[2]
  266. 61 - - SDIO0_D[3]
  267. 62 - - -