marvell,armada-37xx-pinctrl.txt 3.5 KB

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  1. * Marvell Armada 37xx SoC pin and GPIO controller
  2. Each Armada 37xx SoC comes with two pin and GPIO controllers, one for the
  3. South Bridge and the other for the North Bridge.
  4. GPIO and pin controller:
  5. ------------------------
  6. Main node:
  7. Refer to pinctrl-bindings.txt in this directory for details of the
  8. common pinctrl bindings used by client devices, including the meaning
  9. of the phrase "pin configuration node".
  10. Required properties for pinctrl driver:
  11. - compatible: "marvell,armada3710-sb-pinctrl", "syscon, "simple-mfd"
  12. for the South Bridge
  13. "marvell,armada3710-nb-pinctrl", "syscon, "simple-mfd"
  14. for the North Bridge
  15. - reg: The first set of registers is for pinctrl/GPIO and the second
  16. set is for the interrupt controller
  17. - interrupts: list of interrupts used by the GPIO
  18. Available groups and functions for the North Bridge:
  19. group: jtag
  20. - pins 20-24
  21. - functions jtag, gpio
  22. group sdio0
  23. - pins 8-10
  24. - functions sdio, gpio
  25. group emmc_nb
  26. - pins 27-35
  27. - functions emmc, gpio
  28. group pwm0
  29. - pin 11 (GPIO1-11)
  30. - functions pwm, gpio
  31. group pwm1
  32. - pin 12
  33. - functions pwm, gpio
  34. group pwm2
  35. - pin 13
  36. - functions pwm, gpio
  37. group pwm3
  38. - pin 14
  39. - functions pwm, gpio
  40. group pmic1
  41. - pin 7
  42. - functions pmic, gpio
  43. group pmic0
  44. - pin 6
  45. - functions pmic, gpio
  46. group i2c2
  47. - pins 2-3
  48. - functions i2c, gpio
  49. group i2c1
  50. - pins 0-1
  51. - functions i2c, gpio
  52. group spi_cs1
  53. - pin 17
  54. - functions spi, gpio
  55. group spi_cs2
  56. - pin 18
  57. - functions spi, gpio
  58. group spi_cs3
  59. - pin 19
  60. - functions spi, gpio
  61. group onewire
  62. - pin 4
  63. - functions onewire, gpio
  64. group uart1
  65. - pins 25-26
  66. - functions uart, gpio
  67. group spi_quad
  68. - pins 15-16
  69. - functions spi, gpio
  70. group uart_2
  71. - pins 9-10
  72. - functions uart, gpio
  73. Available groups and functions for the South Bridge:
  74. group usb32_drvvbus0
  75. - pin 36
  76. - functions drvbus, gpio
  77. group usb2_drvvbus1
  78. - pin 37
  79. - functions drvbus, gpio
  80. group sdio_sb
  81. - pins 60-65
  82. - functions sdio, gpio
  83. group rgmii
  84. - pins 42-53
  85. - functions mii, gpio
  86. group pcie1
  87. - pins 39-41
  88. - functions pcie, gpio
  89. group smi
  90. - pins 54-55
  91. - functions smi, gpio
  92. group ptp
  93. - pins 56-58
  94. - functions ptp, gpio
  95. group ptp_clk
  96. - pin 57
  97. - functions ptp, mii
  98. group ptp_trig
  99. - pin 58
  100. - functions ptp, mii
  101. group mii_col
  102. - pin 59
  103. - functions mii, mii_err
  104. GPIO subnode:
  105. Please refer to gpio.txt in "gpio" directory for details of gpio-ranges property
  106. and the common GPIO bindings used by client devices.
  107. Required properties for the GPIO driver under the gpio subnode:
  108. - interrupts: List of interrupt specifiers for the controllers interrupt.
  109. - gpio-controller: Marks the device node as a GPIO controller.
  110. - #gpio-cells: Should be 2. The first cell is the GPIO number and the
  111. second cell specifies GPIO flags, as defined in
  112. <dt-bindings/gpio/gpio.h>. Only the GPIO_ACTIVE_HIGH and
  113. GPIO_ACTIVE_LOW flags are supported.
  114. - gpio-ranges: Range of pins managed by the GPIO controller.
  115. Example:
  116. pinctrl_sb: pinctrl-sb@18800 {
  117. compatible = "marvell,armada3710-sb-pinctrl",
  118. "syscon", "simple-mfd";
  119. reg = <0x18800 0x100>, <0x18C00 0x20>;
  120. gpiosb: gpiosb {
  121. #gpio-cells = <2>;
  122. gpio-ranges = <&pinctrl_sb 0 0 30>;
  123. gpio-controller;
  124. interrupts =
  125. <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>,
  126. <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>,
  127. <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>,
  128. <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>,
  129. <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>;
  130. };
  131. rgmii_pins: mii-pins {
  132. groups = "rgmii";
  133. function = "mii";
  134. };
  135. sdio_pins: sdio-pins {
  136. groups = "sdio_sb";
  137. function = "sdio";
  138. };
  139. pcie_pins: pcie-pins {
  140. groups = "pcie1";
  141. function = "pcie";
  142. };
  143. };