phy-stm32-usbphyc.txt 2.3 KB

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  1. STMicroelectronics STM32 USB HS PHY controller
  2. The STM32 USBPHYC block contains a dual port High Speed UTMI+ PHY and a UTMI
  3. switch. It controls PHY configuration and status, and the UTMI+ switch that
  4. selects either OTG or HOST controller for the second PHY port. It also sets
  5. PLL configuration.
  6. USBPHYC
  7. |_ PLL
  8. |
  9. |_ PHY port#1 _________________ HOST controller
  10. | _ |
  11. | / 1|________________|
  12. |_ PHY port#2 ----| |________________
  13. | \_0| |
  14. |_ UTMI switch_______| OTG controller
  15. Phy provider node
  16. =================
  17. Required properties:
  18. - compatible: must be "st,stm32mp1-usbphyc"
  19. - reg: address and length of the usb phy control register set
  20. - clocks: phandle + clock specifier for the PLL phy clock
  21. - vdda1v1-supply: phandle to the regulator providing 1V1 power to the PHY
  22. - vdda1v8-supply: phandle to the regulator providing 1V8 power to the PHY
  23. - #address-cells: number of address cells for phys sub-nodes, must be <1>
  24. - #size-cells: number of size cells for phys sub-nodes, must be <0>
  25. Optional properties:
  26. - assigned-clocks: phandle + clock specifier for the PLL phy clock
  27. - assigned-clock-parents: the PLL phy clock parent
  28. - resets: phandle + reset specifier
  29. Required nodes: one sub-node per port the controller provides.
  30. Phy sub-nodes
  31. ==============
  32. Required properties:
  33. - reg: phy port index
  34. - phy-supply: phandle to the regulator providing 3V3 power to the PHY,
  35. see phy-bindings.txt in the same directory.
  36. - #phy-cells: see phy-bindings.txt in the same directory, must be <0> for PHY
  37. port#1 and must be <1> for PHY port#2, to select USB controller
  38. Optional properties:
  39. - vbus-supply: phandle to the regulator providing 5V vbus to the USB connector
  40. Example:
  41. usbphyc: usb-phy@5a006000 {
  42. compatible = "st,stm32mp1-usbphyc";
  43. reg = <0x5a006000 0x1000>;
  44. clocks = <&rcc_clk USBPHY_K>;
  45. resets = <&rcc_rst USBPHY_R>;
  46. #address-cells = <1>;
  47. #size-cells = <0>;
  48. usbphyc_port0: usb-phy@0 {
  49. reg = <0>;
  50. phy-supply = <&vdd_usb>;
  51. vdda1v1-supply = <&reg11>;
  52. vdda1v8-supply = <&reg18>
  53. #phy-cells = <0>;
  54. };
  55. usbphyc_port1: usb-phy@1 {
  56. reg = <1>;
  57. phy-supply = <&vdd_usb>;
  58. vdda1v1-supply = <&reg11>;
  59. vdda1v8-supply = <&reg18>
  60. #phy-cells = <1>;
  61. };
  62. };