phy-mtk-tphy.txt 4.3 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144
  1. MediaTek T-PHY binding
  2. --------------------------
  3. T-phy controller supports physical layer functionality for a number of
  4. controllers on MediaTek SoCs, such as, USB2.0, USB3.0, PCIe, and SATA.
  5. Required properties (controller (parent) node):
  6. - compatible : should be one of
  7. "mediatek,generic-tphy-v1"
  8. "mediatek,generic-tphy-v2"
  9. - #address-cells: the number of cells used to represent physical
  10. base addresses.
  11. - #size-cells: the number of cells used to represent the size of an address.
  12. - ranges: the address mapping relationship to the parent, defined with
  13. - empty value: if optional 'reg' is used.
  14. - non-empty value: if optional 'reg' is not used. should set
  15. the child's base address to 0, the physical address
  16. within parent's address space, and the length of
  17. the address map.
  18. Required nodes : a sub-node is required for each port the controller
  19. provides. Address range information including the usual
  20. 'reg' property is used inside these nodes to describe
  21. the controller's topology.
  22. Optional properties (controller (parent) node):
  23. - reg : offset and length of register shared by multiple ports,
  24. exclude port's private register.
  25. - mediatek,src-ref-clk-mhz : frequency of reference clock for slew rate
  26. calibrate
  27. - mediatek,src-coef : coefficient for slew rate calibrate, depends on
  28. SoC process
  29. Required properties (port (child) node):
  30. - reg : address and length of the register set for the port.
  31. - #phy-cells : should be 1 (See second example)
  32. cell after port phandle is phy type from:
  33. - PHY_TYPE_USB2
  34. - PHY_TYPE_USB3
  35. - PHY_TYPE_PCIE
  36. - PHY_TYPE_SATA
  37. Optional properties (port (child) node):
  38. - clocks : a list of phandle + clock-specifier pairs, one for each
  39. entry in clock-names
  40. - clock-names : may contain
  41. "ref": 48M reference clock for HighSpeed (digital) phy; and 26M
  42. reference clock for SuperSpeed (digital) phy, sometimes is
  43. 24M, 25M or 27M, depended on platform.
  44. "da_ref": the reference clock of analog phy, used if the clocks
  45. of analog and digital phys are separated, otherwise uses
  46. "ref" clock only if needed.
  47. Example:
  48. u3phy2: usb-phy@1a244000 {
  49. compatible = "mediatek,generic-tphy-v1";
  50. reg = <0x1a244000 0x0700>;
  51. #address-cells = <1>;
  52. #size-cells = <1>;
  53. ranges;
  54. status = "disabled";
  55. u2port1: usb-phy@1a244800 {
  56. reg = <0x1a244800 0x0100>;
  57. clocks = <&topckgen CLK_TOP_USB_PHY48M>;
  58. clock-names = "ref";
  59. #phy-cells = <1>;
  60. status = "okay";
  61. };
  62. u3port1: usb-phy@1a244900 {
  63. reg = <0x1a244900 0x0700>;
  64. clocks = <&clk26m>;
  65. clock-names = "ref";
  66. #phy-cells = <1>;
  67. status = "okay";
  68. };
  69. };
  70. Specifying phy control of devices
  71. ---------------------------------
  72. Device nodes should specify the configuration required in their "phys"
  73. property, containing a phandle to the phy port node and a device type;
  74. phy-names for each port are optional.
  75. Example:
  76. #include <dt-bindings/phy/phy.h>
  77. usb30: usb@11270000 {
  78. ...
  79. phys = <&u2port0 PHY_TYPE_USB2>, <&u3port0 PHY_TYPE_USB3>;
  80. phy-names = "usb2-0", "usb3-0";
  81. ...
  82. };
  83. Layout differences of banks between TPHY V1 and V2
  84. -------------------------------------------------------------
  85. IP V1:
  86. port offset bank
  87. shared 0x0000 SPLLC
  88. 0x0100 FMREG
  89. u2 port0 0x0800 U2PHY_COM
  90. u3 port0 0x0900 U3PHYD
  91. 0x0a00 U3PHYD_BANK2
  92. 0x0b00 U3PHYA
  93. 0x0c00 U3PHYA_DA
  94. u2 port1 0x1000 U2PHY_COM
  95. u3 port1 0x1100 U3PHYD
  96. 0x1200 U3PHYD_BANK2
  97. 0x1300 U3PHYA
  98. 0x1400 U3PHYA_DA
  99. u2 port2 0x1800 U2PHY_COM
  100. ...
  101. IP V2:
  102. port offset bank
  103. u2 port0 0x0000 MISC
  104. 0x0100 FMREG
  105. 0x0300 U2PHY_COM
  106. u3 port0 0x0700 SPLLC
  107. 0x0800 CHIP
  108. 0x0900 U3PHYD
  109. 0x0a00 U3PHYD_BANK2
  110. 0x0b00 U3PHYA
  111. 0x0c00 U3PHYA_DA
  112. u2 port1 0x1000 MISC
  113. 0x1100 FMREG
  114. 0x1300 U2PHY_COM
  115. u3 port1 0x1700 SPLLC
  116. 0x1800 CHIP
  117. 0x1900 U3PHYD
  118. 0x1a00 U3PHYD_BANK2
  119. 0x1b00 U3PHYA
  120. 0x1c00 U3PHYA_DA
  121. u2 port2 0x2000 MISC
  122. ...
  123. SPLLC shared by u3 ports and FMREG shared by u2 ports on
  124. TPHY V1 are put back into each port; a new bank MISC for
  125. u2 ports and CHIP for u3 ports are added on TPHY V2.