snps,dwc-qos-ethernet.txt 6.9 KB

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  1. * Synopsys DWC Ethernet QoS IP version 4.10 driver (GMAC)
  2. This binding supports the Synopsys Designware Ethernet QoS (Quality Of Service)
  3. IP block. The IP supports multiple options for bus type, clocking and reset
  4. structure, and feature list. Consequently, a number of properties and list
  5. entries in properties are marked as optional, or only required in specific HW
  6. configurations.
  7. Required properties:
  8. - compatible: One of:
  9. - "axis,artpec6-eqos", "snps,dwc-qos-ethernet-4.10"
  10. Represents the IP core when integrated into the Axis ARTPEC-6 SoC.
  11. - "nvidia,tegra186-eqos", "snps,dwc-qos-ethernet-4.10"
  12. Represents the IP core when integrated into the NVIDIA Tegra186 SoC.
  13. - "snps,dwc-qos-ethernet-4.10"
  14. This combination is deprecated. It should be treated as equivalent to
  15. "axis,artpec6-eqos", "snps,dwc-qos-ethernet-4.10". It is supported to be
  16. compatible with earlier revisions of this binding.
  17. - reg: Address and length of the register set for the device
  18. - clocks: Phandle and clock specifiers for each entry in clock-names, in the
  19. same order. See ../clock/clock-bindings.txt.
  20. - clock-names: May contain any/all of the following depending on the IP
  21. configuration, in any order:
  22. - "tx"
  23. The EQOS transmit path clock. The HW signal name is clk_tx_i.
  24. In some configurations (e.g. GMII/RGMII), this clock also drives the PHY TX
  25. path. In other configurations, other clocks (such as tx_125, rmii) may
  26. drive the PHY TX path.
  27. - "rx"
  28. The EQOS receive path clock. The HW signal name is clk_rx_i.
  29. In some configurations (e.g. GMII/RGMII), this clock is derived from the
  30. PHY's RX clock output. In other configurations, other clocks (such as
  31. rx_125, rmii) may drive the EQOS RX path.
  32. In cases where the PHY clock is directly fed into the EQOS receive path
  33. without intervening logic, the DT need not represent this clock, since it
  34. is assumed to be fully under the control of the PHY device/driver. In
  35. cases where SoC integration adds additional logic to this path, such as a
  36. SW-controlled clock gate, this clock should be represented in DT.
  37. - "slave_bus"
  38. The CPU/slave-bus (CSR) interface clock. This applies to any bus type;
  39. APB, AHB, AXI, etc. The HW signal name is hclk_i (AHB) or clk_csr_i (other
  40. buses).
  41. - "master_bus"
  42. The master bus interface clock. Only required in configurations that use a
  43. separate clock for the master and slave bus interfaces. The HW signal name
  44. is hclk_i (AHB) or aclk_i (AXI).
  45. - "ptp_ref"
  46. The PTP reference clock. The HW signal name is clk_ptp_ref_i.
  47. - "phy_ref_clk"
  48. This clock is deprecated and should not be used by new compatible values.
  49. It is equivalent to "tx".
  50. - "apb_pclk"
  51. This clock is deprecated and should not be used by new compatible values.
  52. It is equivalent to "slave_bus".
  53. Note: Support for additional IP configurations may require adding the
  54. following clocks to this list in the future: clk_rx_125_i, clk_tx_125_i,
  55. clk_pmarx_0_i, clk_pmarx1_i, clk_rmii_i, clk_revmii_rx_i, clk_revmii_tx_i.
  56. Configurations exist where multiple similar clocks are used at once, e.g. all
  57. of clk_rx_125_i, clk_pmarx_0_i, clk_pmarx1_i. For this reason it is best to
  58. extend the binding with a separate clock-names entry for each of those RX
  59. clocks, rather than repurposing the existing "rx" clock-names entry as a
  60. generic/logical clock in a similar fashion to "master_bus" and "slave_bus".
  61. This will allow easy support for configurations that support multiple PHY
  62. interfaces using a mux, and hence need to have explicit control over
  63. specific RX clocks.
  64. The following compatible values require the following set of clocks:
  65. - "nvidia,tegra186-eqos", "snps,dwc-qos-ethernet-4.10":
  66. - "slave_bus"
  67. - "master_bus"
  68. - "rx"
  69. - "tx"
  70. - "ptp_ref"
  71. - "axis,artpec6-eqos", "snps,dwc-qos-ethernet-4.10":
  72. - "slave_bus"
  73. - "master_bus"
  74. - "tx"
  75. - "ptp_ref"
  76. - "snps,dwc-qos-ethernet-4.10" (deprecated):
  77. - "phy_ref_clk"
  78. - "apb_clk"
  79. - interrupt-parent: Should be the phandle for the interrupt controller
  80. that services interrupts for this device
  81. - interrupts: Should contain the core's combined interrupt signal
  82. - phy-mode: See ethernet.txt file in the same directory
  83. - resets: Phandle and reset specifiers for each entry in reset-names, in the
  84. same order. See ../reset/reset.txt.
  85. - reset-names: May contain any/all of the following depending on the IP
  86. configuration, in any order:
  87. - "eqos". The reset to the entire module. The HW signal name is hreset_n
  88. (AHB) or aresetn_i (AXI).
  89. The following compatible values require the following set of resets:
  90. (the reset properties may be omitted if empty)
  91. - "nvidia,tegra186-eqos", "snps,dwc-qos-ethernet-4.10":
  92. - "eqos".
  93. - "axis,artpec6-eqos", "snps,dwc-qos-ethernet-4.10":
  94. - None.
  95. - "snps,dwc-qos-ethernet-4.10" (deprecated):
  96. - None.
  97. Optional properties:
  98. - dma-coherent: Present if dma operations are coherent
  99. - mac-address: See ethernet.txt in the same directory
  100. - local-mac-address: See ethernet.txt in the same directory
  101. - phy-reset-gpios: Phandle and specifier for any GPIO used to reset the PHY.
  102. See ../gpio/gpio.txt.
  103. - snps,en-lpi: If present it enables use of the AXI low-power interface
  104. - snps,write-requests: Number of write requests that the AXI port can issue.
  105. It depends on the SoC configuration.
  106. - snps,read-requests: Number of read requests that the AXI port can issue.
  107. It depends on the SoC configuration.
  108. - snps,burst-map: Bitmap of allowed AXI burst lengts, with the LSB
  109. representing 4, then 8 etc.
  110. - snps,txpbl: DMA Programmable burst length for the TX DMA
  111. - snps,rxpbl: DMA Programmable burst length for the RX DMA
  112. - snps,en-tx-lpi-clockgating: Enable gating of the MAC TX clock during
  113. TX low-power mode.
  114. - phy-handle: See ethernet.txt file in the same directory
  115. - mdio device tree subnode: When the GMAC has a phy connected to its local
  116. mdio, there must be device tree subnode with the following
  117. required properties:
  118. - compatible: Must be "snps,dwc-qos-ethernet-mdio".
  119. - #address-cells: Must be <1>.
  120. - #size-cells: Must be <0>.
  121. For each phy on the mdio bus, there must be a node with the following
  122. fields:
  123. - reg: phy id used to communicate to phy.
  124. - device_type: Must be "ethernet-phy".
  125. - fixed-mode device tree subnode: see fixed-link.txt in the same directory
  126. Examples:
  127. ethernet2@40010000 {
  128. clock-names = "phy_ref_clk", "apb_pclk";
  129. clocks = <&clkc 17>, <&clkc 15>;
  130. compatible = "snps,dwc-qos-ethernet-4.10";
  131. interrupt-parent = <&intc>;
  132. interrupts = <0x0 0x1e 0x4>;
  133. reg = <0x40010000 0x4000>;
  134. phy-handle = <&phy2>;
  135. phy-mode = "gmii";
  136. phy-reset-gpios = <&gpioctlr 43 GPIO_ACTIVE_LOW>;
  137. snps,en-tx-lpi-clockgating;
  138. snps,en-lpi;
  139. snps,write-requests = <2>;
  140. snps,read-requests = <16>;
  141. snps,burst-map = <0x7>;
  142. snps,txpbl = <8>;
  143. snps,rxpbl = <2>;
  144. dma-coherent;
  145. mdio {
  146. #address-cells = <0x1>;
  147. #size-cells = <0x0>;
  148. phy2: phy@1 {
  149. compatible = "ethernet-phy-ieee802.3-c22";
  150. device_type = "ethernet-phy";
  151. reg = <0x1>;
  152. };
  153. };
  154. };