st,stm32mp1-ddr.txt 6.1 KB

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  1. ST,stm32mp1 DDR3/LPDDR2/LPDDR3 Controller (DDRCTRL and DDRPHYC)
  2. --------------------
  3. Required properties:
  4. --------------------
  5. - compatible : Should be "st,stm32mp1-ddr"
  6. - reg : controleur (DDRCTRL) and phy (DDRPHYC) base address
  7. - clocks : controller clocks handle
  8. - clock-names : associated controller clock names
  9. the "ddrphyc" clock is used to check the DDR frequency
  10. at phy level according the expected value in "mem-speed" field
  11. the next attributes are DDR parameters, they are generated by DDR tools
  12. included in STM32 Cube tool
  13. info attributes:
  14. ----------------
  15. - st,mem-name : name for DDR configuration, simple string for information
  16. - st,mem-speed : DDR expected speed for the setting in kHz
  17. - st,mem-size : DDR mem size in byte
  18. controlleur attributes:
  19. -----------------------
  20. - st,ctl-reg : controleur values depending of the DDR type
  21. (DDR3/LPDDR2/LPDDR3)
  22. for STM32MP15x: 25 values are requested in this order
  23. MSTR
  24. MRCTRL0
  25. MRCTRL1
  26. DERATEEN
  27. DERATEINT
  28. PWRCTL
  29. PWRTMG
  30. HWLPCTL
  31. RFSHCTL0
  32. RFSHCTL3
  33. CRCPARCTL0
  34. ZQCTL0
  35. DFITMG0
  36. DFITMG1
  37. DFILPCFG0
  38. DFIUPD0
  39. DFIUPD1
  40. DFIUPD2
  41. DFIPHYMSTR
  42. ODTMAP
  43. DBG0
  44. DBG1
  45. DBGCMD
  46. POISONCFG
  47. PCCFG
  48. - st,ctl-timing : controleur values depending of frequency and timing parameter
  49. of DDR
  50. for STM32MP15x: 12 values are requested in this order
  51. RFSHTMG
  52. DRAMTMG0
  53. DRAMTMG1
  54. DRAMTMG2
  55. DRAMTMG3
  56. DRAMTMG4
  57. DRAMTMG5
  58. DRAMTMG6
  59. DRAMTMG7
  60. DRAMTMG8
  61. DRAMTMG14
  62. ODTCFG
  63. - st,ctl-map : controleur values depending of address mapping
  64. for STM32MP15x: 9 values are requested in this order
  65. ADDRMAP1
  66. ADDRMAP2
  67. ADDRMAP3
  68. ADDRMAP4
  69. ADDRMAP5
  70. ADDRMAP6
  71. ADDRMAP9
  72. ADDRMAP10
  73. ADDRMAP11
  74. - st,ctl-perf : controleur values depending of performance and scheduling
  75. for STM32MP15x: 17 values are requested in this order
  76. SCHED
  77. SCHED1
  78. PERFHPR1
  79. PERFLPR1
  80. PERFWR1
  81. PCFGR_0
  82. PCFGW_0
  83. PCFGQOS0_0
  84. PCFGQOS1_0
  85. PCFGWQOS0_0
  86. PCFGWQOS1_0
  87. PCFGR_1
  88. PCFGW_1
  89. PCFGQOS0_1
  90. PCFGQOS1_1
  91. PCFGWQOS0_1
  92. PCFGWQOS1_1
  93. phyc attributes:
  94. ----------------
  95. - st,phy-reg : phy values depending of the DDR type (DDR3/LPDDR2/LPDDR3)
  96. for STM32MP15x: 11 values are requested in this order
  97. PGCR
  98. ACIOCR
  99. DXCCR
  100. DSGCR
  101. DCR
  102. ODTCR
  103. ZQ0CR1
  104. DX0GCR
  105. DX1GCR
  106. DX2GCR
  107. DX3GCR
  108. - st,phy-timing : phy values depending of frequency and timing parameter of DDR
  109. for STM32MP15x: 10 values are requested in this order
  110. PTR0
  111. PTR1
  112. PTR2
  113. DTPR0
  114. DTPR1
  115. DTPR2
  116. MR0
  117. MR1
  118. MR2
  119. MR3
  120. - st,phy-cal : phy cal depending of calibration or tuning of DDR
  121. This parameter is optional; when it is absent the built-in PHY
  122. calibration is done.
  123. for STM32MP15x: 12 values are requested in this order
  124. DX0DLLCR
  125. DX0DQTR
  126. DX0DQSTR
  127. DX1DLLCR
  128. DX1DQTR
  129. DX1DQSTR
  130. DX2DLLCR
  131. DX2DQTR
  132. DX2DQSTR
  133. DX3DLLCR
  134. DX3DQTR
  135. DX3DQSTR
  136. Example:
  137. / {
  138. soc {
  139. u-boot,dm-spl;
  140. ddr: ddr@0x5A003000{
  141. u-boot,dm-spl;
  142. u-boot,dm-pre-reloc;
  143. compatible = "st,stm32mp1-ddr";
  144. reg = <0x5A003000 0x550
  145. 0x5A004000 0x234>;
  146. clocks = <&rcc_clk AXIDCG>,
  147. <&rcc_clk DDRC1>,
  148. <&rcc_clk DDRC2>,
  149. <&rcc_clk DDRPHYC>,
  150. <&rcc_clk DDRCAPB>,
  151. <&rcc_clk DDRPHYCAPB>;
  152. clock-names = "axidcg",
  153. "ddrc1",
  154. "ddrc2",
  155. "ddrphyc",
  156. "ddrcapb",
  157. "ddrphycapb";
  158. st,mem-name = "DDR3 2x4Gb 533MHz";
  159. st,mem-speed = <533000>;
  160. st,mem-size = <0x40000000>;
  161. st,ctl-reg = <
  162. 0x00040401 /*MSTR*/
  163. 0x00000010 /*MRCTRL0*/
  164. 0x00000000 /*MRCTRL1*/
  165. 0x00000000 /*DERATEEN*/
  166. 0x00800000 /*DERATEINT*/
  167. 0x00000000 /*PWRCTL*/
  168. 0x00400010 /*PWRTMG*/
  169. 0x00000000 /*HWLPCTL*/
  170. 0x00210000 /*RFSHCTL0*/
  171. 0x00000000 /*RFSHCTL3*/
  172. 0x00000000 /*CRCPARCTL0*/
  173. 0xC2000040 /*ZQCTL0*/
  174. 0x02050105 /*DFITMG0*/
  175. 0x00000202 /*DFITMG1*/
  176. 0x07000000 /*DFILPCFG0*/
  177. 0xC0400003 /*DFIUPD0*/
  178. 0x00000000 /*DFIUPD1*/
  179. 0x00000000 /*DFIUPD2*/
  180. 0x00000000 /*DFIPHYMSTR*/
  181. 0x00000001 /*ODTMAP*/
  182. 0x00000000 /*DBG0*/
  183. 0x00000000 /*DBG1*/
  184. 0x00000000 /*DBGCMD*/
  185. 0x00000000 /*POISONCFG*/
  186. 0x00000010 /*PCCFG*/
  187. >;
  188. st,ctl-timing = <
  189. 0x0080008A /*RFSHTMG*/
  190. 0x121B2414 /*DRAMTMG0*/
  191. 0x000D041B /*DRAMTMG1*/
  192. 0x0607080E /*DRAMTMG2*/
  193. 0x0050400C /*DRAMTMG3*/
  194. 0x07040407 /*DRAMTMG4*/
  195. 0x06060303 /*DRAMTMG5*/
  196. 0x02020002 /*DRAMTMG6*/
  197. 0x00000202 /*DRAMTMG7*/
  198. 0x00001005 /*DRAMTMG8*/
  199. 0x000D041B /*DRAMTMG1*/4
  200. 0x06000600 /*ODTCFG*/
  201. >;
  202. st,ctl-map = <
  203. 0x00080808 /*ADDRMAP1*/
  204. 0x00000000 /*ADDRMAP2*/
  205. 0x00000000 /*ADDRMAP3*/
  206. 0x00001F1F /*ADDRMAP4*/
  207. 0x07070707 /*ADDRMAP5*/
  208. 0x0F070707 /*ADDRMAP6*/
  209. 0x00000000 /*ADDRMAP9*/
  210. 0x00000000 /*ADDRMAP10*/
  211. 0x00000000 /*ADDRMAP11*/
  212. >;
  213. st,ctl-perf = <
  214. 0x00001201 /*SCHED*/
  215. 0x00001201 /*SCHED*/1
  216. 0x01000001 /*PERFHPR1*/
  217. 0x08000200 /*PERFLPR1*/
  218. 0x08000400 /*PERFWR1*/
  219. 0x00010000 /*PCFGR_0*/
  220. 0x00000000 /*PCFGW_0*/
  221. 0x02100B03 /*PCFGQOS0_0*/
  222. 0x00800100 /*PCFGQOS1_0*/
  223. 0x01100B03 /*PCFGWQOS0_0*/
  224. 0x01000200 /*PCFGWQOS1_0*/
  225. 0x00010000 /*PCFGR_1*/
  226. 0x00000000 /*PCFGW_1*/
  227. 0x02100B03 /*PCFGQOS0_1*/
  228. 0x00800000 /*PCFGQOS1_1*/
  229. 0x01100B03 /*PCFGWQOS0_1*/
  230. 0x01000200 /*PCFGWQOS1_1*/
  231. >;
  232. st,phy-reg = <
  233. 0x01442E02 /*PGCR*/
  234. 0x10400812 /*ACIOCR*/
  235. 0x00000C40 /*DXCCR*/
  236. 0xF200001F /*DSGCR*/
  237. 0x0000000B /*DCR*/
  238. 0x00010000 /*ODTCR*/
  239. 0x0000007B /*ZQ0CR1*/
  240. 0x0000CE81 /*DX0GCR*/
  241. 0x0000CE81 /*DX1GCR*/
  242. 0x0000CE81 /*DX2GCR*/
  243. 0x0000CE81 /*DX3GCR*/
  244. >;
  245. st,phy-timing = <
  246. 0x0022A41B /*PTR0*/
  247. 0x047C0740 /*PTR1*/
  248. 0x042D9C80 /*PTR2*/
  249. 0x369477D0 /*DTPR0*/
  250. 0x098A00D8 /*DTPR1*/
  251. 0x10023600 /*DTPR2*/
  252. 0x00000830 /*MR0*/
  253. 0x00000000 /*MR1*/
  254. 0x00000208 /*MR2*/
  255. 0x00000000 /*MR3*/
  256. >;
  257. st,phy-cal = <
  258. 0x40000000 /*DX0DLLCR*/
  259. 0xFFFFFFFF /*DX0DQTR*/
  260. 0x3DB02000 /*DX0DQSTR*/
  261. 0x40000000 /*DX1DLLCR*/
  262. 0xFFFFFFFF /*DX1DQTR*/
  263. 0x3DB02000 /*DX1DQSTR*/
  264. 0x40000000 /*DX2DLLCR*/
  265. 0xFFFFFFFF /*DX2DQTR*/
  266. 0x3DB02000 /*DX2DQSTR*/
  267. 0x40000000 /*DX3DLLCR*/
  268. 0xFFFFFFFF /*DX3DQTR*/
  269. 0x3DB02000 /*DX3DQSTR*/
  270. >;
  271. status = "okay";
  272. };
  273. };
  274. };