st,stm32-fmc.txt 1.5 KB

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  1. ST, stm32 flexible memory controller Drive
  2. Required properties:
  3. - compatible : "st,stm32-fmc"
  4. - reg : fmc controller base address
  5. - clocks : fmc controller clock
  6. u-boot,dm-pre-reloc: flag to initialize memory before relocation.
  7. on-board sdram memory attributes:
  8. - st,sdram-control : parameters for sdram configuration, in this order:
  9. number of columns
  10. number of rows
  11. memory width
  12. number of intenal banks in memory
  13. cas latency
  14. read burst enable or disable
  15. read pipe delay
  16. - st,sdram-timing: timings for sdram, in this order:
  17. tmrd
  18. txsr
  19. tras
  20. trc
  21. trp
  22. trcd
  23. There is device tree include file at :
  24. include/dt-bindings/memory/stm32-sdram.h to define sdram control and timing
  25. parameters as MACROS.
  26. Example:
  27. fmc: fmc@A0000000 {
  28. compatible = "st,stm32-fmc";
  29. reg = <0xA0000000 0x1000>;
  30. clocks = <&rcc 0 64>;
  31. u-boot,dm-pre-reloc;
  32. };
  33. &fmc {
  34. pinctrl-0 = <&fmc_pins>;
  35. pinctrl-names = "default";
  36. status = "okay";
  37. /* sdram memory configuration from sdram datasheet */
  38. bank1: bank@0 {
  39. st,sdram-control = /bits/ 8 <NO_COL_8 NO_ROW_12 MWIDTH_16 BANKS_2
  40. CAS_3 RD_BURST_EN RD_PIPE_DL_0>;
  41. st,sdram-timing = /bits/ 8 <TMRD_1 TXSR_60 TRAS_42 TRC_60 TRP_18
  42. TRCD_18>;
  43. };
  44. /* sdram memory configuration from sdram datasheet */
  45. bank2: bank@1 {
  46. st,sdram-control = /bits/ 8 <NO_COL_8 NO_ROW_12 MWIDTH_16 BANKS_2
  47. CAS_3 RD_BURST_EN RD_PIPE_DL_0>;
  48. st,sdram-timing = /bits/ 8 <TMRD_1 TXSR_60 TRAS_42 TRC_60 TRP_18
  49. TRCD_18>;
  50. };
  51. }