k3-am654-ddrss.txt 1.6 KB

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  1. Texas Instruments' K3 AM654 DDRSS
  2. =================================
  3. K3 based AM654 devices has DDR memory subsystem that comprises
  4. Synopys DDR controller, Synopsis DDR phy and wrapper logic to
  5. integrate these blocks into the device. This DDR subsystem
  6. provides an interface to external SDRAM devices. This DDRSS driver
  7. adds support for the initialization of the external SDRAM devices by
  8. configuring the DDRSS registers and using the buitin PHY
  9. initialization routines.
  10. DDRSS device node:
  11. ==================
  12. Required properties:
  13. --------------------
  14. - compatible: Shall be: "ti,am654-ddrss"
  15. - reg-names ss - Map the sub system wrapper logic region
  16. ctl - Map the controller region
  17. phy - Map the PHY region
  18. - reg: Contains the register map per reg-names.
  19. - power-domains: Should contain a phandle to a PM domain provider node
  20. and an args specifier containing the DDRSS device id
  21. value. This property is as per the binding,
  22. doc/device-tree-bindings/power/ti,sci-pm-domain.txt
  23. - clocks: Must contain an entry for enabling DDR clock. Should
  24. be defined as per the appropriate clock bindings consumer
  25. usage in doc/device-tree-bindings/clock/ti,sci-clk.txt
  26. Optional Properties:
  27. --------------------
  28. - clock-frequency: Frequency at which DDR pll should be locked.
  29. If not provided, default frequency will be used.
  30. Example (AM65x):
  31. ================
  32. memory-controller: memory-controller@298e000 {
  33. compatible = "ti,am654-ddrss";
  34. reg = <0x0298e000 0x200>,
  35. <0x02980000 0x4000>,
  36. <0x02988000 0x2000>;
  37. reg-names = "ss", "ctl", "phy";
  38. clocks = <&k3_clks 20 0>;
  39. power-domains = <&k3_pds 20>;
  40. u-boot,dm-spl;
  41. };