st,stm32mp1.txt 9.4 KB

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  1. STMicroelectronics STM32MP1 clock tree initialization
  2. =====================================================
  3. The STM32MP1 clock tree initialization is based on device tree information
  4. for RCC IP node (st,stm32mp1-rcc) and on fixed-clock nodes.
  5. RCC IP = st,stm32mp1-rcc
  6. ========================
  7. The RCC IP is both a reset and a clock controller but this documentation only
  8. describes the fields added for clock tree initialization which are not present
  9. in Linux binding for compatible "st,stm32mp1-rcc" defined in st,stm32mp1-rcc.txt
  10. file.
  11. This parent node may optionally have additional children nodes which define
  12. specific init values for RCC elements.
  13. The added properties for clock tree initialization are:
  14. Required properties:
  15. - st,clksrc : The clock sources configuration array in a platform specific
  16. order.
  17. For the STM32MP15x family there are 9 clock sources selector which are
  18. configured in the following order:
  19. MPU AXI MCU PLL12 PLL3 PLL4 RTC MCO1 MCO2
  20. Clock source configuration values are defined by macros CLK_<NAME>_<SOURCE>
  21. from dt-bindings/clock/stm32mp1-clksrc.h.
  22. Example:
  23. st,clksrc = <
  24. CLK_MPU_PLL1P
  25. CLK_AXI_PLL2P
  26. CLK_MCU_PLL3P
  27. CLK_PLL12_HSE
  28. CLK_PLL3_HSE
  29. CLK_PLL4_HSE
  30. CLK_RTC_LSE
  31. CLK_MCO1_DISABLED
  32. CLK_MCO2_DISABLED
  33. >;
  34. - st,clkdiv : The clock main dividers value specified in an array
  35. in a platform specific order.
  36. When used, it shall describe the whole clock dividers tree.
  37. For the STM32MP15x family there are 11 dividers values expected.
  38. They shall be configured in the following order:
  39. MPU AXI MCU APB1 APB2 APB3 APB4 APB5 RTC MCO1 MCO2
  40. The each divider value uses the DIV coding defined in RCC associated
  41. register RCC_xxxDIVR. In most the case, it is:
  42. 0x0: not divided
  43. 0x1: division by 2
  44. 0x2: division by 4
  45. 0x3: division by 8
  46. ...
  47. Note that for RTC MCO1 MCO2, the coding is different:
  48. 0x0: not divided
  49. 0x1: division by 2
  50. 0x2: division by 3
  51. 0x3: division by 4
  52. ...
  53. Example:
  54. st,clkdiv = <
  55. 1 /*MPU*/
  56. 0 /*AXI*/
  57. 0 /*MCU*/
  58. 1 /*APB1*/
  59. 1 /*APB2*/
  60. 1 /*APB3*/
  61. 1 /*APB4*/
  62. 2 /*APB5*/
  63. 23 /*RTC*/
  64. 0 /*MCO1*/
  65. 0 /*MCO2*/
  66. >;
  67. Optional Properties:
  68. - children for a PLL configuration with "st,stm32mp1-pll" compatible
  69. each PLL children nodes for PLL1 to PLL4 (see ref manual for details)
  70. are listed with associated reg 0 to 3.
  71. PLLx is off when the associated node is absent or deactivated.
  72. For PLL1, when the node is absent, the frequency of the OPP node is used
  73. to compute the PLL setting (see compatible "operating-points-v2" in
  74. opp/opp.txt for details).
  75. Here are the available properties for each PLL node:
  76. - compatible: should be "st,stm32mp1-pll"
  77. - reg: index of the pll instance
  78. - cfg: The parameters for PLL configuration in the following order:
  79. DIVM DIVN DIVP DIVQ DIVR Output.
  80. DIVx values are defined as in RCC spec:
  81. 0x0: bypass (division by 1)
  82. 0x1: division by 2
  83. 0x2: division by 3
  84. 0x3: division by 4
  85. ...
  86. Output contains a bitfield for each output value (1:ON/0:OFF)
  87. BIT(0) => output P : DIVPEN
  88. BIT(1) => output Q : DIVQEN
  89. BIT(2) => output R : DIVREN
  90. NB: macro PQR(p,q,r) can be used to build this value
  91. with p,q,r = 0 or 1.
  92. - frac : Fractional part of the multiplication factor
  93. (optional, PLL is in integer mode when absent).
  94. - csg : Clock Spreading Generator (optional) with parameters in the
  95. following order: MOD_PER INC_STEP SSCG_MODE.
  96. MOD_PER: Modulation Period Adjustment
  97. INC_STEP: Modulation Depth Adjustment
  98. SSCG_MODE: Spread spectrum clock generator mode, with associated
  99. defined from stm32mp1-clksrc.h:
  100. - SSCG_MODE_CENTER_SPREAD = 0
  101. - SSCG_MODE_DOWN_SPREAD = 1
  102. Example:
  103. st,pll@0 {
  104. compatible = "st,stm32mp1-pll";
  105. reg = <0>;
  106. cfg = < 1 53 0 0 0 1 >;
  107. frac = < 0x810 >;
  108. };
  109. st,pll@1 {
  110. compatible = "st,stm32mp1-pll";
  111. reg = <1>;
  112. cfg = < 1 43 1 0 0 PQR(0,1,1) >;
  113. csg = < 10 20 1 >;
  114. };
  115. st,pll@2 {
  116. compatible = "st,stm32mp1-pll";
  117. reg = <2>;
  118. cfg = < 2 85 3 13 3 0 >;
  119. csg = < 10 20 SSCG_MODE_CENTER_SPREAD >;
  120. };
  121. st,pll@3 {
  122. compatible = "st,stm32mp1-pll";
  123. reg = <3>;
  124. cfg = < 2 78 4 7 9 3 >;
  125. };
  126. - st,pkcs : used to configure the peripherals kernel clock selection.
  127. The property is a list of peripheral kernel clock source identifiers defined
  128. by macros CLK_<KERNEL-CLOCK>_<PARENT-CLOCK> as defined by header file
  129. dt-bindings/clock/stm32mp1-clksrc.h.
  130. st,pkcs may not list all the kernel clocks and has no ordering requirements.
  131. Example:
  132. st,pkcs = <
  133. CLK_STGEN_HSE
  134. CLK_CKPER_HSI
  135. CLK_USBPHY_PLL2P
  136. CLK_DSI_PLL2Q
  137. CLK_I2C46_HSI
  138. CLK_UART1_HSI
  139. CLK_UART24_HSI
  140. >;
  141. other clocks = fixed-clock
  142. ==========================
  143. The clock tree is also based on 5 fixed-clock in clocks node
  144. used to define the state of associated ST32MP1 oscillators:
  145. - clk-lsi
  146. - clk-lse
  147. - clk-hsi
  148. - clk-hse
  149. - clk-csi
  150. At boot the clock tree initialization will
  151. - enable oscillators present in device tree and not disabled
  152. (node with status="disabled"),
  153. - disable HSI oscillator if the node is absent (always activated by bootrom)
  154. and not disabled (node with status="disabled").
  155. Optional properties :
  156. a) for external oscillator: "clk-lse", "clk-hse"
  157. 4 optional fields are managed
  158. - "st,bypass" configures the oscillator bypass mode (HSEBYP, LSEBYP)
  159. - "st,digbypass" configures the bypass mode as full-swing digital
  160. signal (DIGBYP)
  161. - "st,css" activates the clock security system (HSECSSON, LSECSSON)
  162. - "st,drive" (only for LSE) contains the value of the drive for the
  163. oscillator (see LSEDRV_ defined in the file
  164. dt-bindings/clock/stm32mp1-clksrc.h)
  165. Example board file:
  166. / {
  167. clocks {
  168. clk_hse: clk-hse {
  169. #clock-cells = <0>;
  170. compatible = "fixed-clock";
  171. clock-frequency = <64000000>;
  172. st,bypass;
  173. };
  174. clk_lse: clk-lse {
  175. #clock-cells = <0>;
  176. compatible = "fixed-clock";
  177. clock-frequency = <32768>;
  178. st,css;
  179. st,drive = <LSEDRV_LOWEST>;
  180. };
  181. };
  182. b) for internal oscillator: "clk-hsi"
  183. Internally HSI clock is fixed to 64MHz for STM32MP157 SoC.
  184. In device tree, clk-hsi is the clock after HSIDIV (clk_hsi in RCC
  185. doc). So this clock frequency is used to compute the expected HSI_DIV
  186. for the clock tree initialization.
  187. Example with HSIDIV = /1:
  188. / {
  189. clocks {
  190. clk_hsi: clk-hsi {
  191. #clock-cells = <0>;
  192. compatible = "fixed-clock";
  193. clock-frequency = <64000000>;
  194. };
  195. };
  196. Example with HSIDIV = /2
  197. / {
  198. clocks {
  199. clk_hsi: clk-hsi {
  200. #clock-cells = <0>;
  201. compatible = "fixed-clock";
  202. clock-frequency = <32000000>;
  203. };
  204. };
  205. Example of clock tree initialization
  206. ====================================
  207. / {
  208. clocks {
  209. u-boot,dm-pre-reloc;
  210. clk_hse: clk-hse {
  211. u-boot,dm-pre-reloc;
  212. #clock-cells = <0>;
  213. compatible = "fixed-clock";
  214. clock-frequency = <24000000>;
  215. st,digbypass;
  216. };
  217. clk_hsi: clk-hsi {
  218. u-boot,dm-pre-reloc;
  219. #clock-cells = <0>;
  220. compatible = "fixed-clock";
  221. clock-frequency = <64000000>;
  222. };
  223. clk_lse: clk-lse {
  224. u-boot,dm-pre-reloc;
  225. #clock-cells = <0>;
  226. compatible = "fixed-clock";
  227. clock-frequency = <32768>;
  228. };
  229. clk_lsi: clk-lsi {
  230. u-boot,dm-pre-reloc;
  231. #clock-cells = <0>;
  232. compatible = "fixed-clock";
  233. clock-frequency = <32000>;
  234. };
  235. clk_csi: clk-csi {
  236. u-boot,dm-pre-reloc;
  237. #clock-cells = <0>;
  238. compatible = "fixed-clock";
  239. clock-frequency = <4000000>;
  240. };
  241. };
  242. soc {
  243. rcc: rcc@50000000 {
  244. u-boot,dm-pre-reloc;
  245. compatible = "st,stm32mp1-rcc", "syscon";
  246. reg = <0x50000000 0x1000>;
  247. #address-cells = <1>;
  248. #size-cells = <0>;
  249. #clock-cells = <1>;
  250. #reset-cells = <1>;
  251. interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
  252. st,clksrc = <
  253. CLK_MPU_PLL1P
  254. CLK_AXI_PLL2P
  255. CLK_MCU_PLL3P
  256. CLK_PLL12_HSE
  257. CLK_PLL3_HSE
  258. CLK_PLL4_HSE
  259. CLK_RTC_LSE
  260. CLK_MCO1_DISABLED
  261. CLK_MCO2_DISABLED
  262. >;
  263. st,clkdiv = <
  264. 1 /*MPU*/
  265. 0 /*AXI*/
  266. 0 /*MCU*/
  267. 1 /*APB1*/
  268. 1 /*APB2*/
  269. 1 /*APB3*/
  270. 1 /*APB4*/
  271. 2 /*APB5*/
  272. 23 /*RTC*/
  273. 0 /*MCO1*/
  274. 0 /*MCO2*/
  275. >;
  276. st,pkcs = <
  277. CLK_CKPER_HSE
  278. CLK_FMC_ACLK
  279. CLK_QSPI_ACLK
  280. CLK_ETH_DISABLED
  281. CLK_SDMMC12_PLL4P
  282. CLK_DSI_DSIPLL
  283. CLK_STGEN_HSE
  284. CLK_USBPHY_HSE
  285. CLK_SPI2S1_PLL3Q
  286. CLK_SPI2S23_PLL3Q
  287. CLK_SPI45_HSI
  288. CLK_SPI6_HSI
  289. CLK_I2C46_HSI
  290. CLK_SDMMC3_PLL4P
  291. CLK_USBO_USBPHY
  292. CLK_ADC_CKPER
  293. CLK_CEC_LSE
  294. CLK_I2C12_HSI
  295. CLK_I2C35_HSI
  296. CLK_UART1_HSI
  297. CLK_UART24_HSI
  298. CLK_UART35_HSI
  299. CLK_UART6_HSI
  300. CLK_UART78_HSI
  301. CLK_SPDIF_PLL4P
  302. CLK_FDCAN_PLL4Q
  303. CLK_SAI1_PLL3Q
  304. CLK_SAI2_PLL3Q
  305. CLK_SAI3_PLL3Q
  306. CLK_SAI4_PLL3Q
  307. CLK_RNG1_LSI
  308. CLK_RNG2_LSI
  309. CLK_LPTIM1_PCLK1
  310. CLK_LPTIM23_PCLK3
  311. CLK_LPTIM45_LSE
  312. >;
  313. /* VCO = 1300.0 MHz => P = 650 (CPU) */
  314. pll1: st,pll@0 {
  315. compatible = "st,stm32mp1-pll";
  316. reg = <0>;
  317. cfg = < 2 80 0 0 0 PQR(1,0,0) >;
  318. frac = < 0x800 >;
  319. u-boot,dm-pre-reloc;
  320. };
  321. /* VCO = 1066.0 MHz => P = 266 (AXI), Q = 533 (GPU),
  322. R = 533 (DDR) */
  323. pll2: st,pll@1 {
  324. compatible = "st,stm32mp1-pll";
  325. reg = <1>;
  326. cfg = < 2 65 1 0 0 PQR(1,1,1) >;
  327. frac = < 0x1400 >;
  328. u-boot,dm-pre-reloc;
  329. };
  330. /* VCO = 417.8 MHz => P = 209, Q = 24, R = 11 */
  331. pll3: st,pll@2 {
  332. compatible = "st,stm32mp1-pll";
  333. reg = <2>;
  334. cfg = < 1 33 1 16 36 PQR(1,1,1) >;
  335. frac = < 0x1a04 >;
  336. u-boot,dm-pre-reloc;
  337. };
  338. /* VCO = 594.0 MHz => P = 99, Q = 74, R = 74 */
  339. pll4: st,pll@3 {
  340. compatible = "st,stm32mp1-pll";
  341. reg = <3>;
  342. cfg = < 3 98 5 7 7 PQR(1,1,1) >;
  343. u-boot,dm-pre-reloc;
  344. };
  345. };
  346. };
  347. };